lxfb: rearrange/rename MSR bitfields
Finally, move the MSR bitfields around in lxfb.h, and rename them. Alas, most of that crap appears to be undocumented. Signed-off-by: Andres Salomon <dilinger@debian.org> Cc: "Antonino A. Daplas" <adaplas@pol.net> Cc: Jordan Crouse <jordan.crouse@amd.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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31f51fa8d4
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aec40532c4
2 changed files with 46 additions and 43 deletions
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@ -27,31 +27,6 @@ int lx_blank_display(struct fb_info *, int);
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void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
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unsigned int, unsigned int);
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/* MSRS */
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#define GLCP_DOTPLL_RESET (1 << 0)
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#define GLCP_DOTPLL_BYPASS (1 << 15)
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#define GLCP_DOTPLL_HALFPIX (1 << 24)
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#define GLCP_DOTPLL_LOCK (1 << 25)
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#define DF_CONFIG_OUTPUT_MASK 0x38
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#define DF_OUTPUT_PANEL 0x08
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#define DF_OUTPUT_CRT 0x00
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#define DF_SIMULTANEOUS_CRT_AND_FP (1 << 15)
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#define DF_DEFAULT_TFT_PAD_SEL_LOW 0xDFFFFFFF
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#define DF_DEFAULT_TFT_PAD_SEL_HIGH 0x0000003F
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#define DC_SPARE_DISABLE_CFIFO_HGO 0x00000800
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#define DC_SPARE_VFIFO_ARB_SELECT 0x00000400
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#define DC_SPARE_WM_LPEN_OVRD 0x00000200
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#define DC_SPARE_LOAD_WM_LPEN_MASK 0x00000100
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#define DC_SPARE_DISABLE_INIT_VID_PRI 0x00000080
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#define DC_SPARE_DISABLE_VFIFO_WM 0x00000040
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#define DC_SPARE_DISABLE_CWD_CHECK 0x00000020
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#define DC_SPARE_PIX8_PAN_FIX 0x00000010
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#define DC_SPARE_FIRST_REQ_MASK 0x00000002
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/* Graphics Processor registers (table 6-29 from the data book) */
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enum gp_registers {
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@ -390,4 +365,31 @@ static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val)
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writel(val, par->vp_regs + 8*reg + VP_FP_START);
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}
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/* MSRs are defined in asm/geode.h; their bitfields are here */
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#define MSR_GLCP_DOTPLL_LOCK (1 << 25) /* r/o */
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#define MSR_GLCP_DOTPLL_HALFPIX (1 << 24)
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#define MSR_GLCP_DOTPLL_BYPASS (1 << 15)
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#define MSR_GLCP_DOTPLL_DOTRESET (1 << 0)
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/* note: this is actually the VP's GLD_MSR_CONFIG */
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#define MSR_LX_GLD_MSR_CONFIG_FMT ((1 << 3) | (1 << 4) | (1 << 5))
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#define MSR_LX_GLD_MSR_CONFIG_FMT_FP (1 << 3)
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#define MSR_LX_GLD_MSR_CONFIG_FMT_CRT (0)
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#define MSR_LX_GLD_MSR_CONFIG_FPC (1 << 15) /* FP *and* CRT */
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#define MSR_LX_MSR_PADSEL_TFT_SEL_LOW 0xDFFFFFFF /* ??? */
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#define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH 0x0000003F /* ??? */
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#define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO (1 << 11) /* undocumented */
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#define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL (1 << 10) /* undocumented */
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#define MSR_LX_SPARE_MSR_WM_LPEN_OVRD (1 << 9) /* undocumented */
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#define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M (1 << 8) /* undocumented */
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#define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI (1 << 7) /* undocumented */
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#define MSR_LX_SPARE_MSR_DIS_VIFO_WM (1 << 6)
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#define MSR_LX_SPARE_MSR_DIS_CWD_CHECK (1 << 5) /* undocumented */
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#define MSR_LX_SPARE_MSR_PIX8_PAN_FIX (1 << 4) /* undocumented */
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#define MSR_LX_SPARE_MSR_FIRST_REQ_MASK (1 << 1) /* undocumented */
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#endif
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@ -154,12 +154,12 @@ static void lx_set_dotpll(u32 pllval)
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rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
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if ((dotpll_lo & GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval))
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if ((dotpll_lo & MSR_GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval))
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return;
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dotpll_hi = pllval;
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dotpll_lo &= ~(GLCP_DOTPLL_BYPASS | GLCP_DOTPLL_HALFPIX);
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dotpll_lo |= GLCP_DOTPLL_RESET;
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dotpll_lo &= ~(MSR_GLCP_DOTPLL_BYPASS | MSR_GLCP_DOTPLL_HALFPIX);
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dotpll_lo |= MSR_GLCP_DOTPLL_DOTRESET;
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wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
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@ -171,13 +171,13 @@ static void lx_set_dotpll(u32 pllval)
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for (i = 0; i < 1000; i++) {
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rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
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if (dotpll_lo & GLCP_DOTPLL_LOCK)
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if (dotpll_lo & MSR_GLCP_DOTPLL_LOCK)
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break;
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}
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/* Clear the reset bit */
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dotpll_lo &= ~GLCP_DOTPLL_RESET;
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dotpll_lo &= ~MSR_GLCP_DOTPLL_DOTRESET;
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wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
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}
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@ -299,8 +299,8 @@ static void lx_graphics_enable(struct fb_info *info)
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write_fp(par, FP_PT2, FP_PT2_SCRC);
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write_fp(par, FP_DFC, FP_DFC_BC);
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msrlo = DF_DEFAULT_TFT_PAD_SEL_LOW;
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msrhi = DF_DEFAULT_TFT_PAD_SEL_HIGH;
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msrlo = MSR_LX_MSR_PADSEL_TFT_SEL_LOW;
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msrhi = MSR_LX_MSR_PADSEL_TFT_SEL_HIGH;
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wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi);
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}
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@ -366,18 +366,17 @@ void lx_set_mode(struct fb_info *info)
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/* Set output mode */
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rdmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
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msrval &= ~DF_CONFIG_OUTPUT_MASK;
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msrval &= ~MSR_LX_GLD_MSR_CONFIG_FMT;
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if (par->output & OUTPUT_PANEL) {
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msrval |= DF_OUTPUT_PANEL;
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msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_FP;
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if (par->output & OUTPUT_CRT)
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msrval |= DF_SIMULTANEOUS_CRT_AND_FP;
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msrval |= MSR_LX_GLD_MSR_CONFIG_FPC;
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else
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msrval &= ~DF_SIMULTANEOUS_CRT_AND_FP;
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} else {
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msrval |= DF_OUTPUT_CRT;
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}
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msrval &= ~MSR_LX_GLD_MSR_CONFIG_FPC;
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} else
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msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_CRT;
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wrmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
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@ -429,10 +428,12 @@ void lx_set_mode(struct fb_info *info)
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rdmsrl(MSR_LX_SPARE_MSR, msrval);
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msrval &= ~(DC_SPARE_DISABLE_CFIFO_HGO | DC_SPARE_VFIFO_ARB_SELECT |
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DC_SPARE_LOAD_WM_LPEN_MASK | DC_SPARE_WM_LPEN_OVRD |
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DC_SPARE_DISABLE_INIT_VID_PRI | DC_SPARE_DISABLE_VFIFO_WM);
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msrval |= DC_SPARE_DISABLE_VFIFO_WM | DC_SPARE_DISABLE_INIT_VID_PRI;
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msrval &= ~(MSR_LX_SPARE_MSR_DIS_CFIFO_HGO
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| MSR_LX_SPARE_MSR_VFIFO_ARB_SEL
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| MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M
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| MSR_LX_SPARE_MSR_WM_LPEN_OVRD);
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msrval |= MSR_LX_SPARE_MSR_DIS_VIFO_WM |
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MSR_LX_SPARE_MSR_DIS_INIT_V_PRI;
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wrmsrl(MSR_LX_SPARE_MSR, msrval);
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gcfg = DC_GENERAL_CFG_DFLE; /* Display fifo enable */
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