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Fix io ordering problems in e100 

Checking e100.c code against Documentation/io_ordering.txt I found the
following problem:

spin_lock_irq...
write
spin-unlock
e100_write_flush

The attached patch fix the code like this:

spin_lock_irq...
write
e100_write_flush
spin-unlock

Signed-off-by: Catalin BOIE <catab@umbrella.ro>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Catalin(ux aka Dino) BOIE 2006-03-04 12:18:59 -05:00 committed by Jeff Garzik
parent e72fd96e8e
commit ad8c48ad3b
1 changed files with 3 additions and 3 deletions
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6
drivers/net/e100.c
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@ -598,8 +598,8 @@ static void e100_enable_irq(struct nic *nic)
spin_lock_irqsave(&nic->cmd_lock, flags);
writeb(irq_mask_none, &nic->csr->scb.cmd_hi);
spin_unlock_irqrestore(&nic->cmd_lock, flags);
e100_write_flush(nic);
spin_unlock_irqrestore(&nic->cmd_lock, flags);
}
static void e100_disable_irq(struct nic *nic)
@ -608,8 +608,8 @@ static void e100_disable_irq(struct nic *nic)
spin_lock_irqsave(&nic->cmd_lock, flags);
writeb(irq_mask_all, &nic->csr->scb.cmd_hi);
spin_unlock_irqrestore(&nic->cmd_lock, flags);
e100_write_flush(nic);
spin_unlock_irqrestore(&nic->cmd_lock, flags);
}
static void e100_hw_reset(struct nic *nic)
@ -1582,8 +1582,8 @@ static void e100_watchdog(unsigned long data)
* interrupt mask bit and the SW Interrupt generation bit */
spin_lock_irq(&nic->cmd_lock);
writeb(readb(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
spin_unlock_irq(&nic->cmd_lock);
e100_write_flush(nic);
spin_unlock_irq(&nic->cmd_lock);
e100_update_stats(nic);
e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);