video: exynos_dp: Check DPCD return codes
Add return code checks to the DPCD transactions in the SW link training Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Jingoo Han <jg1.han@samsung.com>
This commit is contained in:
Sean Paul
Jingoo Han
parent
825e90d0a1
commit
ace2d7f2b5
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@ -262,11 +262,10 @@ static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
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}
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}
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static void exynos_dp_link_start(struct exynos_dp_device *dp)
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static int exynos_dp_link_start(struct exynos_dp_device *dp)
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{
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u8 buf[4];
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int lane;
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int lane_count;
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int lane, lane_count, retval;
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lane_count = dp->link_train.lane_count;
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@ -277,8 +276,10 @@ static void exynos_dp_link_start(struct exynos_dp_device *dp)
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dp->link_train.cr_loop[lane] = 0;
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/* Set sink to D0 (Sink Not Ready) mode. */
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exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
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retval = exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
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DPCD_SET_POWER_STATE_D0);
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if (retval)
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return retval;
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/* Set link rate and count as you want to establish*/
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exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
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@ -287,8 +288,10 @@ static void exynos_dp_link_start(struct exynos_dp_device *dp)
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/* Setup RX configuration */
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buf[0] = dp->link_train.link_rate;
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buf[1] = dp->link_train.lane_count;
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exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET,
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retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET,
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2, buf);
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if (retval)
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return retval;
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/* Set TX pre-emphasis to minimum */
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for (lane = 0; lane < lane_count; lane++)
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@ -307,9 +310,11 @@ static void exynos_dp_link_start(struct exynos_dp_device *dp)
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for (lane = 0; lane < lane_count; lane++)
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buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
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DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
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exynos_dp_write_bytes_to_dpcd(dp,
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retval = exynos_dp_write_bytes_to_dpcd(dp,
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DPCD_ADDR_TRAINING_LANE0_SET,
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lane_count, buf);
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return retval;
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}
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static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
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@ -431,8 +436,7 @@ static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
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static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
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{
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u8 link_status[2];
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int lane;
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int lane_count;
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int lane, lane_count, retval;
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u8 adjust_request[2];
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u8 voltage_swing;
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@ -443,17 +447,22 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
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lane_count = dp->link_train.lane_count;
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exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
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retval = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
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2, link_status);
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if (retval)
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return retval;
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if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
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/* set training pattern 2 for EQ */
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exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
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for (lane = 0; lane < lane_count; lane++) {
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exynos_dp_read_bytes_from_dpcd(dp,
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retval = exynos_dp_read_bytes_from_dpcd(dp,
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DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
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2, adjust_request);
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if (retval)
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return retval;
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voltage_swing = exynos_dp_get_adjust_request_voltage(
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adjust_request, lane);
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pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
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@ -473,15 +482,19 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
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lane);
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}
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exynos_dp_write_byte_to_dpcd(dp,
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retval = exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TRAINING_PATTERN_SET,
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DPCD_SCRAMBLING_DISABLED |
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DPCD_TRAINING_PATTERN_2);
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if (retval)
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return retval;
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exynos_dp_write_bytes_to_dpcd(dp,
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retval = exynos_dp_write_bytes_to_dpcd(dp,
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DPCD_ADDR_TRAINING_LANE0_SET,
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lane_count,
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dp->link_train.training_lane);
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if (retval)
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return retval;
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dev_info(dp->dev, "Link Training Clock Recovery success\n");
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dp->link_train.lt_state = EQUALIZER_TRAINING;
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@ -489,9 +502,12 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
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for (lane = 0; lane < lane_count; lane++) {
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training_lane = exynos_dp_get_lane_link_training(
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dp, lane);
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exynos_dp_read_bytes_from_dpcd(dp,
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retval = exynos_dp_read_bytes_from_dpcd(dp,
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DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
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2, adjust_request);
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if (retval)
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return retval;
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voltage_swing = exynos_dp_get_adjust_request_voltage(
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adjust_request, lane);
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pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
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@ -528,13 +544,14 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
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dp->link_train.training_lane[lane], lane);
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}
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exynos_dp_write_bytes_to_dpcd(dp,
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DPCD_ADDR_TRAINING_LANE0_SET,
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lane_count,
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dp->link_train.training_lane);
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retval = exynos_dp_write_bytes_to_dpcd(dp,
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DPCD_ADDR_TRAINING_LANE0_SET, lane_count,
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dp->link_train.training_lane);
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if (retval)
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return retval;
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}
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return 0;
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return retval;
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reduce_link_rate:
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exynos_dp_reduce_link_rate(dp);
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@ -545,8 +562,7 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
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{
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u8 link_status[2];
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u8 link_align[3];
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int lane;
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int lane_count;
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int lane, lane_count, retval;
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u32 reg;
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u8 adjust_request[2];
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@ -558,8 +574,10 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
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lane_count = dp->link_train.lane_count;
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exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
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retval = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
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2, link_status);
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if (retval)
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return retval;
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if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
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link_align[0] = link_status[0];
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@ -570,9 +588,12 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
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&link_align[2]);
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for (lane = 0; lane < lane_count; lane++) {
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exynos_dp_read_bytes_from_dpcd(dp,
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retval = exynos_dp_read_bytes_from_dpcd(dp,
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DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
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2, adjust_request);
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if (retval)
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return retval;
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voltage_swing = exynos_dp_get_adjust_request_voltage(
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adjust_request, lane);
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pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
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@ -621,10 +642,12 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
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dp->link_train.training_lane[lane],
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lane);
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exynos_dp_write_bytes_to_dpcd(dp,
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DPCD_ADDR_TRAINING_LANE0_SET,
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lane_count,
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dp->link_train.training_lane);
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retval = exynos_dp_write_bytes_to_dpcd(dp,
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DPCD_ADDR_TRAINING_LANE0_SET,
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lane_count,
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dp->link_train.training_lane);
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if (retval)
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return retval;
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}
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} else {
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goto reduce_link_rate;
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@ -702,16 +725,17 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
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static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
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{
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int retval = 0;
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int training_finished = 0;
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int retval = 0, training_finished = 0;
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dp->link_train.lt_state = START;
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/* Process here */
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while (!training_finished) {
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while (!retval && !training_finished) {
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switch (dp->link_train.lt_state) {
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case START:
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exynos_dp_link_start(dp);
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retval = exynos_dp_link_start(dp);
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if (retval)
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dev_err(dp->dev, "LT link start failed!\n");
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break;
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case CLOCK_RECOVERY:
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retval = exynos_dp_process_clock_recovery(dp);
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@ -730,6 +754,8 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
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return -EREMOTEIO;
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}
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}
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if (retval)
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dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
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return retval;
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}
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