dect
/
linux-2.6
Archived
13
0
Fork 0
Code Releases Activity

drm/i915: rip out sanitize_pm again 

We believe to have squashed all issues around the gen6+ rps interrupt
generation and why the gpu sometimes got stuck. With that cleared up,
there's no user left for the sanitize_pm infrastructure, so let's just
rip it out.

Note that 'intel_reg_write 0xa014 0x13070000' is the w/a if we find
ourselves stuck again.

Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2012-07-26 11:50:05 +02:00
parent 20b46e59dd
commit acbe947550
4 changed files with 5 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/i915/i915_drv.h
View File

@ -249,7 +249,6 @@ struct drm_i915_display_funcs {
void (*update_wm)(struct drm_device *dev);
void (*update_sprite_wm)(struct drm_device *dev, int pipe,
uint32_t sprite_width, int pixel_size);
void (*sanitize_pm)(struct drm_device *dev);
void (*update_linetime_wm)(struct drm_device *dev, int pipe,
struct drm_display_mode *mode);
int (*crtc_mode_set)(struct drm_crtc *crtc,

2
drivers/gpu/drm/i915/intel_display.c
View File

@ -5929,13 +5929,11 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
void intel_mark_busy(struct drm_device *dev)
{
intel_sanitize_pm(dev);
i915_update_gfx_val(dev->dev_private);
}
void intel_mark_idle(struct drm_device *dev)
{
intel_sanitize_pm(dev);
}
void intel_mark_fb_busy(struct drm_i915_gem_object *obj)

2
drivers/gpu/drm/i915/intel_drv.h
View File

@ -390,8 +390,6 @@ extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
enum plane plane);
void intel_sanitize_pm(struct drm_device *dev);
/* intel_panel.c */
extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode);

39
drivers/gpu/drm/i915/intel_pm.c
View File

@ -2267,6 +2267,11 @@ static void ironlake_disable_drps(struct drm_device *dev)
}
/* There's a funny hw issue where the hw returns all 0 when reading from
* GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
* ourselves, instead of doing a rmw cycle (which might result in us clearing
* all limits and the gpu stuck at whatever frequency it is at atm).
*/
static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
{
u32 limits;
@ -3750,37 +3755,6 @@ void intel_init_clock_gating(struct drm_device *dev)
dev_priv->display.init_pch_clock_gating(dev);
}
static void gen6_sanitize_pm(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
u32 limits, current_limits;
gen6_gt_force_wake_get(dev_priv);
current_limits = I915_READ(GEN6_RP_INTERRUPT_LIMITS);
/* Make sure we continue to get interrupts
* until we hit the minimum or maximum frequencies.
*/
limits = gen6_rps_limits(dev_priv, dev_priv->cur_delay);
if (current_limits != limits) {
/* Note that the known failure case is to read back 0. */
DRM_DEBUG_DRIVER("Power management discrepancy: GEN6_RP_INTERRUPT_LIMITS "
"expected %08x, was %08x\n", limits, current_limits);
I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
}
gen6_gt_force_wake_put(dev_priv);
}
void intel_sanitize_pm(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
if (dev_priv->display.sanitize_pm)
dev_priv->display.sanitize_pm(dev);
}
/* Starting with Haswell, we have different power wells for
* different parts of the GPU. This attempts to enable them all.
*/
@ -3866,7 +3840,6 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->display.update_wm = NULL;
}
dev_priv->display.init_clock_gating = gen6_init_clock_gating;
dev_priv->display.sanitize_pm = gen6_sanitize_pm;
} else if (IS_IVYBRIDGE(dev)) {
/* FIXME: detect B0+ stepping and use auto training */
if (SNB_READ_WM0_LATENCY()) {
@ -3878,7 +3851,6 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->display.update_wm = NULL;
}
dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
dev_priv->display.sanitize_pm = gen6_sanitize_pm;
} else if (IS_HASWELL(dev)) {
if (SNB_READ_WM0_LATENCY()) {
dev_priv->display.update_wm = sandybridge_update_wm;
@ -3890,7 +3862,6 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->display.update_wm = NULL;
}
dev_priv->display.init_clock_gating = haswell_init_clock_gating;
dev_priv->display.sanitize_pm = gen6_sanitize_pm;
} else
dev_priv->display.update_wm = NULL;
} else if (IS_VALLEYVIEW(dev)) {