OMAP: DSS2: Add new registers for NV12 support
Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Amber Jain
Tomi Valkeinen
parent
5719d35cce
commit
ab5ca071e2
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@ -217,6 +217,25 @@ void dispc_save_context(void)
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for (i = 0; i < 8; i++)
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SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
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if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
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SR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
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SR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
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SR(OVL_FIR2(OMAP_DSS_VIDEO1));
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SR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
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SR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
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for (i = 0; i < 8; i++)
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SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
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for (i = 0; i < 8; i++)
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SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
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for (i = 0; i < 8; i++)
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SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
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}
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if (dss_has_feature(FEAT_ATTR2))
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SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
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SR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
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/* VID2 */
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@ -245,6 +264,25 @@ void dispc_save_context(void)
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for (i = 0; i < 8; i++)
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SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
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if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
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SR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
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SR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
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SR(OVL_FIR2(OMAP_DSS_VIDEO2));
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SR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
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SR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
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for (i = 0; i < 8; i++)
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SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
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for (i = 0; i < 8; i++)
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SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
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for (i = 0; i < 8; i++)
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SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
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}
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if (dss_has_feature(FEAT_ATTR2))
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SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
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SR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
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if (dss_has_feature(FEAT_CORE_CLK_DIV))
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@ -338,6 +376,25 @@ void dispc_restore_context(void)
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for (i = 0; i < 8; i++)
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RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
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if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
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RR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
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RR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
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RR(OVL_FIR2(OMAP_DSS_VIDEO1));
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RR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
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RR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
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for (i = 0; i < 8; i++)
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RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
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for (i = 0; i < 8; i++)
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RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
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for (i = 0; i < 8; i++)
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RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
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}
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if (dss_has_feature(FEAT_ATTR2))
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RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
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RR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
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/* VID2 */
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@ -366,6 +423,25 @@ void dispc_restore_context(void)
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for (i = 0; i < 8; i++)
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RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
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if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
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RR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
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RR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
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RR(OVL_FIR2(OMAP_DSS_VIDEO2));
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RR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
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RR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
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for (i = 0; i < 8; i++)
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RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
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for (i = 0; i < 8; i++)
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RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
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for (i = 0; i < 8; i++)
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RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
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}
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if (dss_has_feature(FEAT_ATTR2))
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RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
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RR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
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if (dss_has_feature(FEAT_CORE_CLK_DIV))
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@ -476,6 +552,27 @@ static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
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dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
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}
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static void _dispc_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
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{
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BUG_ON(plane == OMAP_DSS_GFX);
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dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
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}
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static void _dispc_write_firhv2_reg(enum omap_plane plane, int reg, u32 value)
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{
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BUG_ON(plane == OMAP_DSS_GFX);
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dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
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}
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static void _dispc_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
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{
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BUG_ON(plane == OMAP_DSS_GFX);
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dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
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}
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static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
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int vscaleup, int five_taps)
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{
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@ -645,6 +742,16 @@ static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
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dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
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}
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static void _dispc_set_plane_ba0_uv(enum omap_plane plane, u32 paddr)
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{
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dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
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}
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static void _dispc_set_plane_ba1_uv(enum omap_plane plane, u32 paddr)
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{
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dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
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}
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static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
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{
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u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
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@ -1025,6 +1132,21 @@ static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
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dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
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}
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static void _dispc_set_vid_accu2_0(enum omap_plane plane, int haccu, int vaccu)
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{
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u32 val;
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val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
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dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
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}
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static void _dispc_set_vid_accu2_1(enum omap_plane plane, int haccu, int vaccu)
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{
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u32 val;
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val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
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dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
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}
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static void _dispc_set_scaling(enum omap_plane plane,
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u16 orig_width, u16 orig_height,
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@ -2496,6 +2618,44 @@ void dispc_dump_regs(struct seq_file *s)
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DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
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DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
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if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
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DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO1));
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DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO1));
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DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO1));
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DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO1));
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DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO1));
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DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 0));
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DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 1));
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DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 2));
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DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 3));
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DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 4));
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DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 5));
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DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 6));
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DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 7));
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DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 0));
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DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 1));
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DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 2));
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DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 3));
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DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 4));
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DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 5));
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DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 6));
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DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 7));
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DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 0));
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DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 1));
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DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 2));
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DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 3));
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DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 4));
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DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 5));
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DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 6));
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DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 7));
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}
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if (dss_has_feature(FEAT_ATTR2))
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DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
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DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
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DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
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DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
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@ -2526,6 +2686,43 @@ void dispc_dump_regs(struct seq_file *s)
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DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
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DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
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if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
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DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO2));
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DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO2));
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DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO2));
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DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO2));
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DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO2));
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DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 0));
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DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 1));
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DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 2));
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DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 3));
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DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 4));
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DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 5));
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DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 6));
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DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 7));
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DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 0));
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DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 1));
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DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 2));
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DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 3));
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DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 4));
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DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 5));
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DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 6));
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DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 7));
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DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 0));
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DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 1));
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DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 2));
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DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 3));
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DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 4));
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DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 5));
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DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 6));
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DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 7));
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}
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if (dss_has_feature(FEAT_ATTR2))
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DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
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DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO1));
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DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO2));
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@ -42,12 +42,18 @@
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DISPC_BA0_OFFSET(n))
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#define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \
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DISPC_BA1_OFFSET(n))
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#define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \
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DISPC_BA0_UV_OFFSET(n))
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#define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \
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DISPC_BA1_UV_OFFSET(n))
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#define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \
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DISPC_POS_OFFSET(n))
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#define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \
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DISPC_SIZE_OFFSET(n))
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#define DISPC_OVL_ATTRIBUTES(n) (DISPC_OVL_BASE(n) + \
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DISPC_ATTR_OFFSET(n))
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#define DISPC_OVL_ATTRIBUTES2(n) (DISPC_OVL_BASE(n) + \
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DISPC_ATTR2_OFFSET(n))
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#define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
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DISPC_FIFO_THRESH_OFFSET(n))
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#define DISPC_OVL_FIFO_SIZE_STATUS(n) (DISPC_OVL_BASE(n) + \
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@ -62,20 +68,32 @@
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DISPC_TABLE_BA_OFFSET(n))
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#define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \
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DISPC_FIR_OFFSET(n))
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#define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \
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DISPC_FIR2_OFFSET(n))
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#define DISPC_OVL_PICTURE_SIZE(n) (DISPC_OVL_BASE(n) + \
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DISPC_PIC_SIZE_OFFSET(n))
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#define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \
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DISPC_ACCU0_OFFSET(n))
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#define DISPC_OVL_ACCU1(n) (DISPC_OVL_BASE(n) + \
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DISPC_ACCU1_OFFSET(n))
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#define DISPC_OVL_ACCU2_0(n) (DISPC_OVL_BASE(n) + \
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DISPC_ACCU2_0_OFFSET(n))
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#define DISPC_OVL_ACCU2_1(n) (DISPC_OVL_BASE(n) + \
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DISPC_ACCU2_1_OFFSET(n))
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#define DISPC_OVL_FIR_COEF_H(n, i) (DISPC_OVL_BASE(n) + \
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DISPC_FIR_COEF_H_OFFSET(n, i))
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#define DISPC_OVL_FIR_COEF_HV(n, i) (DISPC_OVL_BASE(n) + \
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DISPC_FIR_COEF_HV_OFFSET(n, i))
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#define DISPC_OVL_FIR_COEF_H2(n, i) (DISPC_OVL_BASE(n) + \
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DISPC_FIR_COEF_H2_OFFSET(n, i))
|
||||
#define DISPC_OVL_FIR_COEF_HV2(n, i) (DISPC_OVL_BASE(n) + \
|
||||
DISPC_FIR_COEF_HV2_OFFSET(n, i))
|
||||
#define DISPC_OVL_CONV_COEF(n, i) (DISPC_OVL_BASE(n) + \
|
||||
DISPC_CONV_COEF_OFFSET(n, i))
|
||||
#define DISPC_OVL_FIR_COEF_V(n, i) (DISPC_OVL_BASE(n) + \
|
||||
DISPC_FIR_COEF_V_OFFSET(n, i))
|
||||
#define DISPC_OVL_FIR_COEF_V2(n, i) (DISPC_OVL_BASE(n) + \
|
||||
DISPC_FIR_COEF_V2_OFFSET(n, i))
|
||||
#define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \
|
||||
DISPC_PRELOAD_OFFSET(n))
|
||||
|
||||
|
|
@ -303,6 +321,34 @@ static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
|
|||
}
|
||||
}
|
||||
|
||||
static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
|
||||
{
|
||||
switch (plane) {
|
||||
case OMAP_DSS_GFX:
|
||||
BUG();
|
||||
case OMAP_DSS_VIDEO1:
|
||||
return 0x0544;
|
||||
case OMAP_DSS_VIDEO2:
|
||||
return 0x04BC;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
|
||||
{
|
||||
switch (plane) {
|
||||
case OMAP_DSS_GFX:
|
||||
BUG();
|
||||
case OMAP_DSS_VIDEO1:
|
||||
return 0x0548;
|
||||
case OMAP_DSS_VIDEO2:
|
||||
return 0x04C0;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
|
||||
{
|
||||
switch (plane) {
|
||||
|
|
@ -340,6 +386,20 @@ static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
|
|||
}
|
||||
}
|
||||
|
||||
static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
|
||||
{
|
||||
switch (plane) {
|
||||
case OMAP_DSS_GFX:
|
||||
BUG();
|
||||
case OMAP_DSS_VIDEO1:
|
||||
return 0x0568;
|
||||
case OMAP_DSS_VIDEO2:
|
||||
return 0x04DC;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
|
||||
{
|
||||
switch (plane) {
|
||||
|
|
@ -431,6 +491,20 @@ static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
|
|||
}
|
||||
}
|
||||
|
||||
static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
|
||||
{
|
||||
switch (plane) {
|
||||
case OMAP_DSS_GFX:
|
||||
BUG();
|
||||
case OMAP_DSS_VIDEO1:
|
||||
return 0x0580;
|
||||
case OMAP_DSS_VIDEO2:
|
||||
return 0x055C;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
|
||||
{
|
||||
switch (plane) {
|
||||
|
|
@ -458,6 +532,20 @@ static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
|
|||
}
|
||||
}
|
||||
|
||||
static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
|
||||
{
|
||||
switch (plane) {
|
||||
case OMAP_DSS_GFX:
|
||||
BUG();
|
||||
case OMAP_DSS_VIDEO1:
|
||||
return 0x0584;
|
||||
case OMAP_DSS_VIDEO2:
|
||||
return 0x0560;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
|
||||
{
|
||||
switch (plane) {
|
||||
|
|
@ -471,6 +559,20 @@ static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
|
|||
}
|
||||
}
|
||||
|
||||
static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
|
||||
{
|
||||
switch (plane) {
|
||||
case OMAP_DSS_GFX:
|
||||
BUG();
|
||||
case OMAP_DSS_VIDEO1:
|
||||
return 0x0588;
|
||||
case OMAP_DSS_VIDEO2:
|
||||
return 0x0564;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
|
||||
static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
|
||||
{
|
||||
|
|
@ -485,6 +587,21 @@ static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
|
|||
}
|
||||
}
|
||||
|
||||
/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
|
||||
static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
|
||||
{
|
||||
switch (plane) {
|
||||
case OMAP_DSS_GFX:
|
||||
BUG();
|
||||
case OMAP_DSS_VIDEO1:
|
||||
return 0x058C + i * 0x8;
|
||||
case OMAP_DSS_VIDEO2:
|
||||
return 0x0568 + i * 0x8;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
|
||||
static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
|
||||
{
|
||||
|
|
@ -499,6 +616,21 @@ static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
|
|||
}
|
||||
}
|
||||
|
||||
/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
|
||||
static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
|
||||
{
|
||||
switch (plane) {
|
||||
case OMAP_DSS_GFX:
|
||||
BUG();
|
||||
case OMAP_DSS_VIDEO1:
|
||||
return 0x0590 + i * 8;
|
||||
case OMAP_DSS_VIDEO2:
|
||||
return 0x056C + i * 0x8;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
/* coef index i = {0, 1, 2, 3, 4,} */
|
||||
static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
|
||||
{
|
||||
|
|
@ -528,6 +660,21 @@ static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
|
|||
}
|
||||
}
|
||||
|
||||
/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
|
||||
static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
|
||||
{
|
||||
switch (plane) {
|
||||
case OMAP_DSS_GFX:
|
||||
BUG();
|
||||
case OMAP_DSS_VIDEO1:
|
||||
return 0x05CC + i * 0x4;
|
||||
case OMAP_DSS_VIDEO2:
|
||||
return 0x05A8 + i * 0x4;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
|
||||
{
|
||||
switch (plane) {
|
||||
|
|
|
|||
|
|
@ -327,7 +327,7 @@ static const struct omap_dss_features omap4430_es1_0_dss_features = {
|
|||
FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 |
|
||||
FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
|
||||
FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
|
||||
FEAT_DSI_GNQ,
|
||||
FEAT_DSI_GNQ | FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2,
|
||||
|
||||
.num_mgrs = 3,
|
||||
.num_ovls = 3,
|
||||
|
|
@ -347,7 +347,8 @@ static const struct omap_dss_features omap4_dss_features = {
|
|||
FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 |
|
||||
FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
|
||||
FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
|
||||
FEAT_DSI_GNQ | FEAT_HDMI_CTS_SWMODE,
|
||||
FEAT_DSI_GNQ | FEAT_HDMI_CTS_SWMODE |
|
||||
FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2,
|
||||
|
||||
.num_mgrs = 3,
|
||||
.num_ovls = 3,
|
||||
|
|
|
|||
|
|
@ -49,6 +49,8 @@ enum dss_feat_id {
|
|||
FEAT_DSI_REVERSE_TXCLKESC = 1 << 17,
|
||||
FEAT_DSI_GNQ = 1 << 18,
|
||||
FEAT_HDMI_CTS_SWMODE = 1 << 19,
|
||||
FEAT_HANDLE_UV_SEPARATE = 1 << 20,
|
||||
FEAT_ATTR2 = 1 << 21,
|
||||
};
|
||||
|
||||
/* DSS register field id */
|
||||
|
|
|
|||
Reference in New Issue