amd64_edac: Cleanup NBCFG handling
The fact whether we are chipkill capable or not does not have any bearing when computing the channel index on a ganged DCT configuration so remove that. Also, simplify debug statements. Finally, remove old error injection leftovers, while at it. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Borislav Petkov
parent
c9f4f26eae
commit
a97fa68ec4
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@ -1011,7 +1011,7 @@ static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
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syndrome = extract_syndrome(err_info);
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/* CHIPKILL enabled */
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if (err_info->nbcfg & K8_NBCFG_CHIPKILL) {
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if (err_info->nbcfg & NBCFG_CHIPKILL) {
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channel = get_channel_from_ecc_syndrome(mci, syndrome);
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if (channel < 0) {
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/*
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@ -1461,7 +1461,7 @@ static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
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* ganged. Otherwise @chan should already contain the channel at
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* this point.
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*/
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if (dct_ganging_enabled(pvt) && (pvt->nbcfg & K8_NBCFG_CHIPKILL))
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if (dct_ganging_enabled(pvt))
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chan = get_channel_from_ecc_syndrome(mci, syndrome);
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if (chan >= 0)
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@ -2050,14 +2050,13 @@ static int init_csrows(struct mem_ctl_info *mci)
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u32 val;
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int i, empty = 1;
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amd64_read_pci_cfg(pvt->F3, K8_NBCFG, &val);
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amd64_read_pci_cfg(pvt->F3, NBCFG, &val);
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pvt->nbcfg = val;
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pvt->ctl_error_info.nbcfg = val;
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debugf0("node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",
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pvt->mc_node_id, val,
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!!(val & K8_NBCFG_CHIPKILL), !!(val & K8_NBCFG_ECC_ENABLE));
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!!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE));
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for_each_chip_select(i, 0, pvt) {
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csrow = &mci->csrows[i];
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@ -2099,9 +2098,9 @@ static int init_csrows(struct mem_ctl_info *mci)
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/*
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* determine whether CHIPKILL or JUST ECC or NO ECC is operating
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*/
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if (pvt->nbcfg & K8_NBCFG_ECC_ENABLE)
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if (pvt->nbcfg & NBCFG_ECC_ENABLE)
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csrow->edac_mode =
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(pvt->nbcfg & K8_NBCFG_CHIPKILL) ?
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(pvt->nbcfg & NBCFG_CHIPKILL) ?
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EDAC_S4ECD4ED : EDAC_SECDED;
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else
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csrow->edac_mode = EDAC_NONE;
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@ -2211,24 +2210,23 @@ static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid,
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value |= mask;
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amd64_write_pci_cfg(F3, NBCTL, value);
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amd64_read_pci_cfg(F3, K8_NBCFG, &value);
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amd64_read_pci_cfg(F3, NBCFG, &value);
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debugf0("1: node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",
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nid, value,
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!!(value & K8_NBCFG_CHIPKILL), !!(value & K8_NBCFG_ECC_ENABLE));
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debugf0("1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
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nid, value, !!(value & NBCFG_ECC_ENABLE));
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if (!(value & K8_NBCFG_ECC_ENABLE)) {
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if (!(value & NBCFG_ECC_ENABLE)) {
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amd64_warn("DRAM ECC disabled on this node, enabling...\n");
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s->flags.nb_ecc_prev = 0;
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/* Attempt to turn on DRAM ECC Enable */
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value |= K8_NBCFG_ECC_ENABLE;
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amd64_write_pci_cfg(F3, K8_NBCFG, value);
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value |= NBCFG_ECC_ENABLE;
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amd64_write_pci_cfg(F3, NBCFG, value);
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amd64_read_pci_cfg(F3, K8_NBCFG, &value);
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amd64_read_pci_cfg(F3, NBCFG, &value);
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if (!(value & K8_NBCFG_ECC_ENABLE)) {
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if (!(value & NBCFG_ECC_ENABLE)) {
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amd64_warn("Hardware rejected DRAM ECC enable,"
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"check memory DIMM configuration.\n");
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ret = false;
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@ -2239,9 +2237,8 @@ static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid,
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s->flags.nb_ecc_prev = 1;
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}
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debugf0("2: node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",
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nid, value,
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!!(value & K8_NBCFG_CHIPKILL), !!(value & K8_NBCFG_ECC_ENABLE));
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debugf0("2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
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nid, value, !!(value & NBCFG_ECC_ENABLE));
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return ret;
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}
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@ -2263,9 +2260,9 @@ static void restore_ecc_error_reporting(struct ecc_settings *s, u8 nid,
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/* restore previous BIOS DRAM ECC "off" setting we force-enabled */
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if (!s->flags.nb_ecc_prev) {
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amd64_read_pci_cfg(F3, K8_NBCFG, &value);
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value &= ~K8_NBCFG_ECC_ENABLE;
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amd64_write_pci_cfg(F3, K8_NBCFG, value);
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amd64_read_pci_cfg(F3, NBCFG, &value);
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value &= ~NBCFG_ECC_ENABLE;
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amd64_write_pci_cfg(F3, NBCFG, value);
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}
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/* restore the NB Enable MCGCTL bit */
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@ -2291,9 +2288,9 @@ static bool ecc_enabled(struct pci_dev *F3, u8 nid)
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u8 ecc_en = 0;
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bool nb_mce_en = false;
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amd64_read_pci_cfg(F3, K8_NBCFG, &value);
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amd64_read_pci_cfg(F3, NBCFG, &value);
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ecc_en = !!(value & K8_NBCFG_ECC_ENABLE);
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ecc_en = !!(value & NBCFG_ECC_ENABLE);
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amd64_info("DRAM ECC %s.\n", (ecc_en ? "enabled" : "disabled"));
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nb_mce_en = amd64_nb_mce_bank_enabled_on_node(nid);
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@ -246,9 +246,9 @@
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*/
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#define NBCTL 0x40
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#define K8_NBCFG 0x44
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#define K8_NBCFG_CHIPKILL BIT(23)
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#define K8_NBCFG_ECC_ENABLE BIT(22)
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#define NBCFG 0x44
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#define NBCFG_CHIPKILL BIT(23)
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#define NBCFG_ECC_ENABLE BIT(22)
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#define K8_NBSL 0x48
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@ -420,9 +420,6 @@ struct amd64_pvt {
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/* x4 or x8 syndromes in use */
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u8 syn_type;
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/* temp storage for when input is received from sysfs */
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struct err_regs ctl_error_info;
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/* place to store error injection parameters prior to issue */
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struct error_injection injection;
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