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tg3: Reduce 57765 core clock when link at 10Mbps 

This patch reduces the core clock to 6.25MHz when operating at 10Mbps
link speed.  This is needed to prevent a bug that will ultimately cause
transmits to cease.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson 2010-04-12 06:58:26 +00:00 committed by David S. Miller
parent 1a3190254c
commit a977dbe844
1 changed files with 5 additions and 0 deletions
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5
drivers/net/tg3.c
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@ -7654,6 +7654,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
tw32(GRC_MODE, grc_mode);
val = tr32(TG3_CPMU_LSPD_10MB_CLK);
val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
val |= CPMU_LSPD_10MB_MACCLK_6_25;
tw32(TG3_CPMU_LSPD_10MB_CLK, val);
}
/* This works around an issue with Athlon chipsets on