e1000: Flush shadow RAM
Flush shadow RAM to save updates to ASF related bits for 82573 controllers. These bits are past the first 63 words of NVM. Signed-off-by: Mallikarjuna R Chilakala <mallikarjuna.chilakala@intel.com> Signed-off-by: Ganesh Venkatesan <ganesh.venkatesan@intel.com> Signed-off-by: John Ronciak <john.ronciak@intel.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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2 changed files with 5 additions and 2 deletions
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@ -547,8 +547,10 @@ e1000_set_eeprom(struct net_device *netdev,
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ret_val = e1000_write_eeprom(hw, first_word,
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ret_val = e1000_write_eeprom(hw, first_word,
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last_word - first_word + 1, eeprom_buff);
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last_word - first_word + 1, eeprom_buff);
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/* Update the checksum over the first part of the EEPROM if needed */
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/* Update the checksum over the first part of the EEPROM if needed
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if((ret_val == 0) && first_word <= EEPROM_CHECKSUM_REG)
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* and flush shadow RAM for 82573 conrollers */
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if((ret_val == 0) && ((first_word <= EEPROM_CHECKSUM_REG) ||
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(hw->mac_type == e1000_82573)))
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e1000_update_eeprom_checksum(hw);
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e1000_update_eeprom_checksum(hw);
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kfree(eeprom_buff);
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kfree(eeprom_buff);
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@ -717,6 +717,7 @@ e1000_init_hw(struct e1000_hw *hw)
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default:
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default:
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break;
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break;
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case e1000_82571:
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case e1000_82571:
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case e1000_82572:
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ctrl = E1000_READ_REG(hw, TXDCTL1);
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ctrl = E1000_READ_REG(hw, TXDCTL1);
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ctrl &= ~E1000_TXDCTL_WTHRESH;
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ctrl &= ~E1000_TXDCTL_WTHRESH;
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ctrl |= E1000_TXDCTL_COUNT_DESC | E1000_TXDCTL_FULL_TX_DESC_WB;
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ctrl |= E1000_TXDCTL_COUNT_DESC | E1000_TXDCTL_FULL_TX_DESC_WB;
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