sh: clkfwk: Update SH7785 for refactored clock framework.
This updates the SH7785 CPU code as well as the SH7785LCR board support code for making use of the newly refactored clock framework. Support for the legacy CPG clocks is dropped at this point, with the extal frequency fed in from the board code. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
253b0887b3
commit
a77b5ac0ea
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@ -514,7 +514,7 @@ config SH_PCLK_FREQ
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platforms lacking an RTC.
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config SH_CLK_CPG_LEGACY
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def_bool y
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def_bool y if !CPU_SUBTYPE_SH7785
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config SH_CLK_MD
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int "CPU Mode Pin Setting"
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@ -2,12 +2,12 @@
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* Renesas Technology Corp. R0P7785LC0011RL Support.
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*
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* Copyright (C) 2008 Yoshihiro Shimoda
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* Copyright (C) 2009 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/sm501.h>
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@ -19,8 +19,11 @@
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#include <linux/i2c-pca-platform.h>
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#include <linux/i2c-algo-pca.h>
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#include <linux/irq.h>
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#include <asm/heartbeat.h>
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#include <linux/clk.h>
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#include <linux/errno.h>
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#include <mach/sh7785lcr.h>
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#include <asm/heartbeat.h>
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#include <asm/clock.h>
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/*
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* NOTE: This board has 2 physical memory maps.
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@ -273,6 +276,20 @@ void __init init_sh7785lcr_IRQ(void)
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plat_irq_setup_pins(IRQ_MODE_IRQ3210);
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}
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static int sh7785lcr_clk_init(void)
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{
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struct clk *clk;
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int ret;
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clk = clk_get(NULL, "extal");
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if (!clk || IS_ERR(clk))
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return PTR_ERR(clk);
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ret = clk_set_rate(clk, 33333333);
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clk_put(clk);
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return ret;
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}
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static void sh7785lcr_power_off(void)
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{
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unsigned char *p;
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@ -309,6 +326,7 @@ static void __init sh7785lcr_setup(char **cmdline_p)
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static struct sh_machine_vector mv_sh7785lcr __initmv = {
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.mv_name = "SH7785LCR",
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.mv_setup = sh7785lcr_setup,
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.mv_clk_init = sh7785lcr_clk_init,
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.mv_init_irq = init_sh7785lcr_IRQ,
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};
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@ -34,7 +34,9 @@ struct clk {
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unsigned long rate;
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unsigned long flags;
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unsigned long arch_flags;
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void *priv;
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};
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struct clk_lookup {
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@ -3,7 +3,7 @@
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*
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* SH7785 support for the clock framework
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*
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* Copyright (C) 2007 Paul Mundt
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* Copyright (C) 2007 - 2009 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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@ -11,145 +11,146 @@
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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#include <asm/io.h>
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static int ifc_divisors[] = { 1, 2, 4, 6 };
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static int ufc_divisors[] = { 1, 1, 4, 6 };
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static int sfc_divisors[] = { 1, 1, 4, 6 };
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static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18,
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24, 32, 36, 48, 1, 1, 1, 1 };
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static int mfc_divisors[] = { 1, 1, 4, 6 };
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static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18,
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24, 32, 36, 48, 1, 1, 1, 1 };
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static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
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24, 32, 36, 48 };
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struct clk_priv {
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unsigned int shift;
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};
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static void master_clk_init(struct clk *clk)
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#define FRQMR_CLK_DATA(_name, _shift) \
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static struct clk_priv _name##_data = { .shift = _shift, }
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FRQMR_CLK_DATA(pfc, 0);
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FRQMR_CLK_DATA(s3fc, 4);
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FRQMR_CLK_DATA(s2fc, 8);
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FRQMR_CLK_DATA(mfc, 12);
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FRQMR_CLK_DATA(bfc, 16);
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FRQMR_CLK_DATA(sfc, 20);
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FRQMR_CLK_DATA(ufc, 24);
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FRQMR_CLK_DATA(ifc, 28);
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static unsigned long frqmr_clk_recalc(struct clk *clk)
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{
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clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
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struct clk_priv *data = clk->priv;
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unsigned int idx;
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idx = (__raw_readl(FRQMR1) >> data->shift) & 0x000f;
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/*
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* XXX: PLL1 multiplier is locked for the default clock mode,
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* when mode pin detection and configuration support is added,
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* select the multiplier dynamically.
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*/
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return clk->parent->rate * 36 / div2[idx];
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}
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static struct clk_ops sh7785_master_clk_ops = {
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.init = master_clk_init,
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};
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static unsigned long module_clk_recalc(struct clk *clk)
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{
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int idx = (ctrl_inl(FRQMR1) & 0x000f);
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return clk->parent->rate / pfc_divisors[idx];
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}
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static struct clk_ops sh7785_module_clk_ops = {
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.recalc = module_clk_recalc,
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};
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static unsigned long bus_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
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return clk->parent->rate / bfc_divisors[idx];
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}
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static struct clk_ops sh7785_bus_clk_ops = {
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.recalc = bus_clk_recalc,
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};
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static unsigned long cpu_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
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return clk->parent->rate / ifc_divisors[idx];
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}
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static struct clk_ops sh7785_cpu_clk_ops = {
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.recalc = cpu_clk_recalc,
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};
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static struct clk_ops *sh7785_clk_ops[] = {
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&sh7785_master_clk_ops,
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&sh7785_module_clk_ops,
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&sh7785_bus_clk_ops,
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&sh7785_cpu_clk_ops,
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};
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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{
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if (idx < ARRAY_SIZE(sh7785_clk_ops))
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*ops = sh7785_clk_ops[idx];
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}
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static unsigned long shyway_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
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return clk->parent->rate / sfc_divisors[idx];
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}
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static struct clk_ops sh7785_shyway_clk_ops = {
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.recalc = shyway_clk_recalc,
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};
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static struct clk sh7785_shyway_clk = {
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.name = "shyway_clk",
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.flags = CLK_ENABLE_ON_INIT,
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.ops = &sh7785_shyway_clk_ops,
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};
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static unsigned long ddr_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
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return clk->parent->rate / mfc_divisors[idx];
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}
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static struct clk_ops sh7785_ddr_clk_ops = {
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.recalc = ddr_clk_recalc,
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};
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static struct clk sh7785_ddr_clk = {
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.name = "ddr_clk",
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.flags = CLK_ENABLE_ON_INIT,
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.ops = &sh7785_ddr_clk_ops,
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};
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static unsigned long ram_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQMR1) >> 24) & 0x0003);
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return clk->parent->rate / ufc_divisors[idx];
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}
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static struct clk_ops sh7785_ram_clk_ops = {
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.recalc = ram_clk_recalc,
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};
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static struct clk sh7785_ram_clk = {
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.name = "ram_clk",
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.flags = CLK_ENABLE_ON_INIT,
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.ops = &sh7785_ram_clk_ops,
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static struct clk_ops frqmr_clk_ops = {
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.recalc = frqmr_clk_recalc,
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};
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/*
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* Additional SH7785-specific on-chip clocks that aren't already part of the
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* clock framework
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* Default rate for the root input clock, reset this with clk_set_rate()
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* from the platform code.
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*/
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static struct clk *sh7785_onchip_clocks[] = {
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&sh7785_shyway_clk,
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&sh7785_ddr_clk,
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&sh7785_ram_clk,
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static struct clk extal_clk = {
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.name = "extal",
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.id = -1,
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.rate = 33333333,
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};
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static struct clk cpu_clk = {
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.name = "cpu_clk", /* Ick */
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.id = -1,
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.ops = &frqmr_clk_ops,
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.parent = &extal_clk,
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.flags = CLK_ENABLE_ON_INIT,
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.priv = &ifc_data,
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};
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static struct clk shyway_clk = {
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.name = "shyway_clk", /* SHck */
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.id = -1,
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.ops = &frqmr_clk_ops,
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.parent = &extal_clk,
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.flags = CLK_ENABLE_ON_INIT,
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.priv = &sfc_data,
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};
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static struct clk peripheral_clk = {
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.name = "peripheral_clk", /* Pck */
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.id = -1,
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.ops = &frqmr_clk_ops,
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.parent = &extal_clk,
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.flags = CLK_ENABLE_ON_INIT,
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.priv = &pfc_data,
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};
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static struct clk ddr_clk = {
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.name = "ddr_clk", /* DDRck */
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.id = -1,
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.ops = &frqmr_clk_ops,
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.parent = &extal_clk,
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.flags = CLK_ENABLE_ON_INIT,
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.priv = &mfc_data,
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};
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static struct clk bus_clk = {
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.name = "bus_clk", /* Bck */
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.id = -1,
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.ops = &frqmr_clk_ops,
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.parent = &extal_clk,
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.flags = CLK_ENABLE_ON_INIT,
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.priv = &bfc_data,
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};
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static struct clk ga_clk = {
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.name = "ga_clk", /* GAck */
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.id = -1,
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.ops = &frqmr_clk_ops,
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.parent = &extal_clk,
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.priv = &s2fc_data,
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};
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static struct clk du_clk = {
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.name = "du_clk", /* DUck */
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.id = -1,
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.ops = &frqmr_clk_ops,
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.parent = &extal_clk,
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.priv = &s3fc_data,
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};
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static struct clk umem_clk = {
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.name = "umem_clk", /* uck */
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.id = -1,
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.ops = &frqmr_clk_ops,
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.parent = &extal_clk,
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.flags = CLK_ENABLE_ON_INIT,
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.priv = &ufc_data,
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};
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static struct clk *clks[] = {
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&extal_clk,
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&cpu_clk,
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­way_clk,
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&peripheral_clk,
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&ddr_clk,
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&bus_clk,
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&ga_clk,
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&du_clk,
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&umem_clk,
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};
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int __init arch_clk_init(void)
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{
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struct clk *clk;
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int i, ret = 0;
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cpg_clk_init();
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clk = clk_get(NULL, "master_clk");
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for (i = 0; i < ARRAY_SIZE(sh7785_onchip_clocks); i++) {
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struct clk *clkp = sh7785_onchip_clocks[i];
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clkp->parent = clk;
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ret |= clk_register(clkp);
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}
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clk_put(clk);
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for (i = 0; i < ARRAY_SIZE(clks); i++)
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ret |= clk_register(clks[i]);
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return ret;
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}
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