pinctrl: samsung: Use per-bank IRQ domain for wake-up interrupts
This patch reworks wake-up interrupt handling in pinctrl-exynos driver,
so each pin bank, which provides wake-up interrupts, has its own IRQ
domain.
Information about whether given pin bank provides wake-up interrupts,
how many and whether they are separate or muxed are parsed from device
tree.
It gives following advantages:
- interrupts can be specified in device tree in a more readable way,
e.g. :
device {
/* ... */
interrupt-parent = <&gpx2>;
interrupts = <4 0>;
/* ... */
};
- the amount and layout of interrupts is not hardcoded in the code
anymore, but defined in SoC-specific structure
- bank and pin of each wake-up interrupt can be easily identified, to
allow operations, such as setting the pin to EINT function, from
irq_set_type() callback
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Tomasz Figa
Linus Walleij
parent
d3a7b9e3a1
commit
a04b07c0fc
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@ -445,6 +445,9 @@
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#gpio-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
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<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
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#interrupt-cells = <2>;
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};
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@ -453,6 +456,9 @@
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#gpio-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
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<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
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#interrupt-cells = <2>;
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};
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@ -56,13 +56,7 @@
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wakup_eint: wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
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<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
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<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
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<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
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<0 32 0>;
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interrupts = <0 32 0>;
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};
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};
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@ -218,46 +218,43 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
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static void exynos_wkup_irq_unmask(struct irq_data *irqd)
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{
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struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
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unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
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unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
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unsigned long reg_mask = d->ctrl->weint_mask + (bank << 2);
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struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *d = b->drvdata;
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unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
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unsigned long mask;
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mask = readl(d->virt_base + reg_mask);
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mask &= ~(1 << pin);
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mask &= ~(1 << irqd->hwirq);
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writel(mask, d->virt_base + reg_mask);
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}
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static void exynos_wkup_irq_mask(struct irq_data *irqd)
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{
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struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
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unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
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unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
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unsigned long reg_mask = d->ctrl->weint_mask + (bank << 2);
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struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *d = b->drvdata;
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unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
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unsigned long mask;
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mask = readl(d->virt_base + reg_mask);
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mask |= 1 << pin;
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mask |= 1 << irqd->hwirq;
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writel(mask, d->virt_base + reg_mask);
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}
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static void exynos_wkup_irq_ack(struct irq_data *irqd)
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{
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struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
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unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
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unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
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unsigned long pend = d->ctrl->weint_pend + (bank << 2);
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struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *d = b->drvdata;
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unsigned long pend = d->ctrl->weint_pend + b->eint_offset;
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writel(1 << pin, d->virt_base + pend);
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writel(1 << irqd->hwirq, d->virt_base + pend);
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}
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static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
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{
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struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
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unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
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unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
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unsigned long reg_con = d->ctrl->weint_con + (bank << 2);
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned int pin = irqd->hwirq;
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unsigned long reg_con = d->ctrl->weint_con + bank->eint_offset;
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unsigned long shift = EXYNOS_EINT_CON_LEN * pin;
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unsigned long con, trig_type;
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@ -309,6 +306,7 @@ static struct irq_chip exynos_wkup_irq_chip = {
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static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
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{
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struct exynos_weint_data *eintd = irq_get_handler_data(irq);
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struct samsung_pin_bank *bank = eintd->bank;
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struct irq_chip *chip = irq_get_chip(irq);
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int eint_irq;
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@ -318,20 +316,20 @@ static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
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if (chip->irq_ack)
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chip->irq_ack(&desc->irq_data);
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eint_irq = irq_linear_revmap(eintd->domain, eintd->irq);
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eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);
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generic_handle_irq(eint_irq);
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chip->irq_unmask(&desc->irq_data);
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chained_irq_exit(chip, desc);
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}
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static inline void exynos_irq_demux_eint(int irq_base, unsigned long pend,
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struct irq_domain *domain)
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static inline void exynos_irq_demux_eint(unsigned long pend,
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struct irq_domain *domain)
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{
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unsigned int irq;
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while (pend) {
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irq = fls(pend) - 1;
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generic_handle_irq(irq_find_mapping(domain, irq_base + irq));
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generic_handle_irq(irq_find_mapping(domain, irq));
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pend &= ~(1 << irq);
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}
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}
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@ -340,18 +338,22 @@ static inline void exynos_irq_demux_eint(int irq_base, unsigned long pend,
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static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_get_chip(irq);
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struct exynos_weint_data *eintd = irq_get_handler_data(irq);
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struct samsung_pinctrl_drv_data *d = eintd->domain->host_data;
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struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq);
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struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata;
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struct samsung_pin_ctrl *ctrl = d->ctrl;
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unsigned long pend;
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unsigned long mask;
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int i;
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chained_irq_enter(chip, desc);
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pend = readl(d->virt_base + d->ctrl->weint_pend + 0x8);
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mask = readl(d->virt_base + d->ctrl->weint_mask + 0x8);
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exynos_irq_demux_eint(16, pend & ~mask, eintd->domain);
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pend = readl(d->virt_base + d->ctrl->weint_pend + 0xC);
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mask = readl(d->virt_base + d->ctrl->weint_mask + 0xC);
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exynos_irq_demux_eint(24, pend & ~mask, eintd->domain);
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for (i = 0; i < eintd->nr_banks; ++i) {
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struct samsung_pin_bank *b = eintd->banks[i];
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pend = readl(d->virt_base + ctrl->weint_pend + b->eint_offset);
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mask = readl(d->virt_base + ctrl->weint_mask + b->eint_offset);
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exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
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}
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chained_irq_exit(chip, desc);
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}
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@ -381,7 +383,11 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
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struct device *dev = d->dev;
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struct device_node *wkup_np = NULL;
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struct device_node *np;
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struct samsung_pin_bank *bank;
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struct exynos_weint_data *weint_data;
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struct exynos_muxed_weint_data *muxed_data;
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unsigned int muxed_banks = 0;
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unsigned int i;
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int idx, irq;
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for_each_child_of_node(dev->of_node, np) {
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@ -393,40 +399,74 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
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if (!wkup_np)
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return -ENODEV;
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d->wkup_irqd = irq_domain_add_linear(wkup_np, d->ctrl->nr_wint,
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&exynos_wkup_irqd_ops, d);
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if (!d->wkup_irqd) {
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dev_err(dev, "wakeup irq domain allocation failed\n");
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return -ENXIO;
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bank = d->ctrl->pin_banks;
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for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
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if (bank->eint_type != EINT_TYPE_WKUP)
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continue;
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bank->irq_domain = irq_domain_add_linear(bank->of_node,
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bank->nr_pins, &exynos_wkup_irqd_ops, bank);
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if (!bank->irq_domain) {
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dev_err(dev, "wkup irq domain add failed\n");
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return -ENXIO;
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}
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if (!of_find_property(bank->of_node, "interrupts", NULL)) {
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bank->eint_type = EINT_TYPE_WKUP_MUX;
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++muxed_banks;
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continue;
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}
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weint_data = devm_kzalloc(dev, bank->nr_pins
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* sizeof(*weint_data), GFP_KERNEL);
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if (!weint_data) {
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dev_err(dev, "could not allocate memory for weint_data\n");
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return -ENOMEM;
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}
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for (idx = 0; idx < bank->nr_pins; ++idx) {
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irq = irq_of_parse_and_map(bank->of_node, idx);
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if (!irq) {
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dev_err(dev, "irq number for eint-%s-%d not found\n",
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bank->name, idx);
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continue;
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}
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weint_data[idx].irq = idx;
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weint_data[idx].bank = bank;
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irq_set_handler_data(irq, &weint_data[idx]);
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irq_set_chained_handler(irq, exynos_irq_eint0_15);
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}
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}
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weint_data = devm_kzalloc(dev, sizeof(*weint_data) * 17, GFP_KERNEL);
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if (!weint_data) {
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dev_err(dev, "could not allocate memory for weint_data\n");
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if (!muxed_banks)
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return 0;
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irq = irq_of_parse_and_map(wkup_np, 0);
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if (!irq) {
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dev_err(dev, "irq number for muxed EINTs not found\n");
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return 0;
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}
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muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
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+ muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
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if (!muxed_data) {
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dev_err(dev, "could not allocate memory for muxed_data\n");
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return -ENOMEM;
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}
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irq = irq_of_parse_and_map(wkup_np, 16);
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if (irq) {
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weint_data[16].domain = d->wkup_irqd;
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irq_set_chained_handler(irq, exynos_irq_demux_eint16_31);
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irq_set_handler_data(irq, &weint_data[16]);
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} else {
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dev_err(dev, "irq number for EINT16-32 not found\n");
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}
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irq_set_chained_handler(irq, exynos_irq_demux_eint16_31);
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irq_set_handler_data(irq, muxed_data);
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for (idx = 0; idx < 16; idx++) {
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weint_data[idx].domain = d->wkup_irqd;
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weint_data[idx].irq = idx;
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bank = d->ctrl->pin_banks;
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idx = 0;
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for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
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if (bank->eint_type != EINT_TYPE_WKUP_MUX)
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continue;
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irq = irq_of_parse_and_map(wkup_np, idx);
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if (irq) {
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irq_set_handler_data(irq, &weint_data[idx]);
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irq_set_chained_handler(irq, exynos_irq_eint0_15);
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} else {
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dev_err(dev, "irq number for eint-%x not found\n", idx);
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}
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muxed_data->banks[idx++] = bank;
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}
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muxed_data->nr_banks = muxed_banks;
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return 0;
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}
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@ -468,10 +508,10 @@ static struct samsung_pin_bank exynos4210_pin_banks1[] = {
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EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
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EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
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EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
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EXYNOS_PIN_BANK_EINTN(8, 0xC00, "gpx0"),
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EXYNOS_PIN_BANK_EINTN(8, 0xC20, "gpx1"),
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EXYNOS_PIN_BANK_EINTN(8, 0xC40, "gpx2"),
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EXYNOS_PIN_BANK_EINTN(8, 0xC60, "gpx3"),
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EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
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EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
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EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
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EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
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};
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/* pin banks of exynos4210 pin-controller 2 */
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@ -498,7 +538,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
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/* pin-controller instance 1 data */
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.pin_banks = exynos4210_pin_banks1,
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.nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
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.nr_wint = 32,
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.geint_con = EXYNOS_GPIO_ECON_OFFSET,
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.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
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.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
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@ -73,13 +73,36 @@
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.name = id \
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}
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#define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \
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{ \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.func_width = 4, \
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.pud_width = 2, \
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.drv_width = 2, \
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.eint_type = EINT_TYPE_WKUP, \
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.eint_offset = offs, \
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.name = id \
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}
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/**
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* struct exynos_weint_data: irq specific data for all the wakeup interrupts
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* generated by the external wakeup interrupt controller.
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* @domain: irq domain representing the external wakeup interrupts
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* @irq: interrupt number within the domain.
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* @bank: bank responsible for this interrupt
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*/
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struct exynos_weint_data {
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struct irq_domain *domain;
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u32 irq;
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unsigned int irq;
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struct samsung_pin_bank *bank;
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};
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/**
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* struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts
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* generated by the external wakeup interrupt controller.
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* @nr_banks: count of banks being part of the mux
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* @banks: array of banks being part of the mux
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*/
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struct exynos_muxed_weint_data {
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unsigned int nr_banks;
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struct samsung_pin_bank *banks[];
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};
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@ -66,6 +66,7 @@ enum pincfg_type {
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* @EINT_TYPE_NONE: bank does not support external interrupts
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* @EINT_TYPE_GPIO: bank supportes external gpio interrupts
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* @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
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* @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
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*
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* Samsung GPIO controller groups all the available pins into banks. The pins
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* in a pin bank can support external gpio interrupts or external wakeup
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@ -78,6 +79,7 @@ enum eint_type {
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EINT_TYPE_NONE,
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EINT_TYPE_GPIO,
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EINT_TYPE_WKUP,
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EINT_TYPE_WKUP_MUX,
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};
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/* maximum length of a pin in pin descriptor (example: "gpa0-0") */
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@ -143,7 +145,6 @@ struct samsung_pin_bank {
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* @nr_banks: number of pin banks.
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* @base: starting system wide pin number.
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* @nr_pins: number of pins supported by the controller.
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* @nr_wint: number of external wakeup interrupts supported.
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* @geint_con: offset of the ext-gpio controller registers.
|
||||
* @geint_mask: offset of the ext-gpio interrupt mask registers.
|
||||
* @geint_pend: offset of the ext-gpio interrupt pending registers.
|
||||
|
|
@ -163,7 +164,6 @@ struct samsung_pin_ctrl {
|
|||
|
||||
u32 base;
|
||||
u32 nr_pins;
|
||||
u32 nr_wint;
|
||||
|
||||
u32 geint_con;
|
||||
u32 geint_mask;
|
||||
|
|
@ -206,8 +206,6 @@ struct samsung_pinctrl_drv_data {
|
|||
unsigned int nr_groups;
|
||||
const struct samsung_pmx_func *pmx_functions;
|
||||
unsigned int nr_functions;
|
||||
|
||||
struct irq_domain *wkup_irqd;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
|||
Reference in New Issue