OF: MIPS: lantiq: implement OF support
Activate USE_OF, add a sample DTS file and convert the core soc code to OF. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3803/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
John Crispin
Ralf Baechle
parent
cd93b4895e
commit
a0392222d9
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@ -229,6 +229,7 @@ config LANTIQ
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select SWAP_IO_SPACE
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select BOOT_RAW
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select HAVE_CLK
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select USE_OF
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config LASAT
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bool "LASAT Networks platforms"
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@ -18,4 +18,13 @@ config SOC_XWAY
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select HW_HAS_PCI
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endchoice
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choice
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prompt "Devicetree"
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config DT_EASY50712
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bool "Easy50712"
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depends on SOC_XWAY
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endchoice
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endif
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@ -4,7 +4,9 @@
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# under the terms of the GNU General Public License version 2 as published
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# by the Free Software Foundation.
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obj-y := irq.o setup.o clk.o prom.o
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obj-y := irq.o clk.o prom.o
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obj-y += dts/
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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@ -0,0 +1,4 @@
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obj-$(CONFIG_DT_EASY50712) := easy50712.dtb.o
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$(obj)/%.dtb: $(obj)/%.dts
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$(call if_changed,dtc)
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@ -0,0 +1,105 @@
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,xway", "lantiq,danube";
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cpus {
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cpu@0 {
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compatible = "mips,mips24Kc";
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};
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};
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biu@1F800000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,biu", "simple-bus";
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reg = <0x1F800000 0x800000>;
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ranges = <0x0 0x1F800000 0x7FFFFF>;
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icu0: icu@80200 {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "lantiq,icu";
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reg = <0x80200 0x120>;
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};
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watchdog@803F0 {
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compatible = "lantiq,wdt";
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reg = <0x803F0 0x10>;
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};
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};
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sram@1F000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,sram";
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reg = <0x1F000000 0x800000>;
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ranges = <0x0 0x1F000000 0x7FFFFF>;
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eiu0: eiu@101000 {
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-parent;
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compatible = "lantiq,eiu-xway";
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reg = <0x101000 0x1000>;
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};
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pmu0: pmu@102000 {
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compatible = "lantiq,pmu-xway";
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reg = <0x102000 0x1000>;
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};
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cgu0: cgu@103000 {
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compatible = "lantiq,cgu-xway";
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reg = <0x103000 0x1000>;
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#clock-cells = <1>;
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};
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rcu0: rcu@203000 {
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compatible = "lantiq,rcu-xway";
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reg = <0x203000 0x1000>;
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};
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};
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fpi@10000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,fpi", "simple-bus";
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ranges = <0x0 0x10000000 0xEEFFFFF>;
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reg = <0x10000000 0xEF00000>;
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gptu@E100A00 {
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compatible = "lantiq,gptu-xway";
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reg = <0xE100A00 0x100>;
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};
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serial@E100C00 {
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compatible = "lantiq,asc";
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reg = <0xE100C00 0x400>;
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interrupt-parent = <&icu0>;
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interrupts = <112 113 114>;
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};
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dma0: dma@E104100 {
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compatible = "lantiq,dma-xway";
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reg = <0xE104100 0x800>;
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};
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ebu0: ebu@E105300 {
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compatible = "lantiq,ebu-xway";
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reg = <0xE105300 0x100>;
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};
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pci0: pci@E105400 {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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compatible = "lantiq,pci-xway";
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bus-range = <0x0 0x0>;
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ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
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0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
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reg = <0x7000000 0x8000 /* config space */
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0xE105400 0x400>; /* pci bridge */
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};
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};
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};
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@ -0,0 +1,113 @@
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/dts-v1/;
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/include/ "danube.dtsi"
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/ {
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chosen {
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bootargs = "console=ttyLTQ0,115200 init=/etc/preinit";
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};
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memory@0 {
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reg = <0x0 0x2000000>;
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};
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fpi@10000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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localbus@0 {
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
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1 0 0x4000000 0x4000010>; /* addsel1 */
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compatible = "lantiq,localbus", "simple-bus";
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nor-boot@0 {
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compatible = "lantiq,nor";
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bank-width = <2>;
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reg = <0 0x0 0x2000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "uboot";
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reg = <0x00000 0x10000>; /* 64 KB */
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};
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partition@10000 {
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label = "uboot_env";
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reg = <0x10000 0x10000>; /* 64 KB */
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};
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partition@20000 {
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label = "linux";
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reg = <0x20000 0x3d0000>;
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};
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partition@400000 {
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label = "rootfs";
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reg = <0x400000 0x400000>;
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};
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};
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};
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gpio: pinmux@E100B10 {
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compatible = "lantiq,pinctrl-xway";
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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#gpio-cells = <2>;
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gpio-controller;
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reg = <0xE100B10 0xA0>;
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state_default: pinmux {
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stp {
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lantiq,groups = "stp";
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lantiq,function = "stp";
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};
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exin {
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lantiq,groups = "exin1";
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lantiq,function = "exin";
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};
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pci {
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lantiq,groups = "gnt1";
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lantiq,function = "pci";
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};
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conf_out {
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lantiq,pins = "io4", "io5", "io6"; /* stp */
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lantiq,open-drain;
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lantiq,pull = <0>;
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};
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};
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};
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etop@E180000 {
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compatible = "lantiq,etop-xway";
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reg = <0xE180000 0x40000>;
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interrupt-parent = <&icu0>;
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interrupts = <73 78>;
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phy-mode = "rmii";
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mac-address = [ 00 11 22 33 44 55 ];
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};
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stp0: stp@E100BB0 {
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#gpio-cells = <2>;
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compatible = "lantiq,gpio-stp-xway";
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gpio-controller;
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reg = <0xE100BB0 0x40>;
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lantiq,shadow = <0xfff>;
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lantiq,groups = <0x3>;
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};
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pci@E105400 {
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lantiq,bus-clock = <33333333>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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0x7000 0 0 1 &icu0 29 1 // slot 14, irq 29
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>;
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gpios-reset = <&gpio 21 0>;
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req-mask = <0x1>; /* GNT1 */
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};
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};
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};
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@ -8,6 +8,7 @@
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#include <linux/export.h>
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#include <linux/clk.h>
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#include <linux/of_platform.h>
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#include <asm/bootinfo.h>
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#include <asm/time.h>
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@ -16,13 +17,15 @@
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#include "prom.h"
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#include "clk.h"
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static struct ltq_soc_info soc_info;
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/* access to the ebu needs to be locked between different drivers */
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DEFINE_SPINLOCK(ebu_lock);
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EXPORT_SYMBOL_GPL(ebu_lock);
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unsigned int ltq_get_cpu_ver(void)
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{
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return soc_info.rev;
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}
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EXPORT_SYMBOL(ltq_get_cpu_ver);
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/*
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* this struct is filled by the soc specific detection code and holds
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* information about the specific soc type, revision and name
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*/
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static struct ltq_soc_info soc_info;
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unsigned int ltq_get_soc_type(void)
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{
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@ -57,16 +60,28 @@ static void __init prom_init_cmdline(void)
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}
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}
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void __init plat_mem_setup(void)
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{
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ioport_resource.start = IOPORT_RESOURCE_START;
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ioport_resource.end = IOPORT_RESOURCE_END;
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iomem_resource.start = IOMEM_RESOURCE_START;
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iomem_resource.end = IOMEM_RESOURCE_END;
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set_io_port_base((unsigned long) KSEG1);
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/*
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* Load the builtin devicetree. This causes the chosen node to be
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* parsed resulting in our memory appearing
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*/
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__dt_setup_arch(&__dtb_start);
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}
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void __init prom_init(void)
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{
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struct clk *clk;
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/* call the soc specific detetcion code and get it to fill soc_info */
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ltq_soc_detect(&soc_info);
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clk_init();
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clk = clk_get(0, "cpu");
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snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d",
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soc_info.name, soc_info.rev);
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clk_put(clk);
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snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
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soc_info.name, soc_info.rev_type);
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soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
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pr_info("SoC: %s\n", soc_info.sys_type);
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prom_init_cmdline();
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@ -76,3 +91,19 @@ void __init prom_init(void)
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panic("failed to register_vsmp_smp_ops()");
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#endif
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}
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int __init plat_of_setup(void)
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{
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static struct of_device_id of_ids[3];
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if (!of_have_populated_dt())
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panic("device tree not present");
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strncpy(of_ids[0].compatible, soc_info.compatible,
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sizeof(of_ids[0].compatible));
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strncpy(of_ids[1].compatible, "simple-bus",
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sizeof(of_ids[1].compatible));
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return of_platform_bus_probe(NULL, of_ids, NULL);
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}
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arch_initcall(plat_of_setup);
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@ -26,4 +26,6 @@ struct ltq_soc_info {
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extern void ltq_soc_detect(struct ltq_soc_info *i);
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extern void ltq_soc_init(void);
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extern struct boot_param_header __dtb_start;
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#endif
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@ -1,43 +0,0 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <asm/bootinfo.h>
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#include <lantiq_soc.h>
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#include "prom.h"
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void __init plat_mem_setup(void)
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{
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/* assume 16M as default incase uboot fails to pass proper ramsize */
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unsigned long memsize = 16;
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char **envp = (char **) KSEG1ADDR(fw_arg2);
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ioport_resource.start = IOPORT_RESOURCE_START;
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ioport_resource.end = IOPORT_RESOURCE_END;
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iomem_resource.start = IOMEM_RESOURCE_START;
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iomem_resource.end = IOMEM_RESOURCE_END;
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set_io_port_base((unsigned long) KSEG1);
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while (*envp) {
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char *e = (char *)KSEG1ADDR(*envp);
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if (!strncmp(e, "memsize=", 8)) {
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e += 8;
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if (strict_strtoul(e, 0, &memsize))
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pr_warn("bad memsize specified\n");
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}
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envp++;
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}
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memsize *= 1024 * 1024;
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add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
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}
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@ -14,10 +14,6 @@
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#include <lantiq_soc.h>
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/* all access to the ebu must be locked */
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DEFINE_SPINLOCK(ebu_lock);
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EXPORT_SYMBOL_GPL(ebu_lock);
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static struct resource ltq_ebu_resource = {
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.name = "ebu",
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.start = LTQ_EBU_BASE_ADDR,
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@ -37,13 +37,6 @@
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#define RCU_BOOT_SEL_SHIFT 26
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#define RCU_BOOT_SEL_MASK 0x7
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static struct resource ltq_rcu_resource = {
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.name = "rcu",
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.start = LTQ_RCU_BASE_ADDR,
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.end = LTQ_RCU_BASE_ADDR + LTQ_RCU_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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/* remapped base addr of the reset control unit */
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static void __iomem *ltq_rcu_membase;
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@ -91,17 +84,21 @@ static void ltq_machine_power_off(void)
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static int __init mips_reboot_setup(void)
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{
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/* insert and request the memory region */
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if (insert_resource(&iomem_resource, <q_rcu_resource) < 0)
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panic("Failed to insert rcu memory");
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struct resource res;
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struct device_node *np =
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of_find_compatible_node(NULL, NULL, "lantiq,rcu-xway");
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if (request_mem_region(ltq_rcu_resource.start,
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resource_size(<q_rcu_resource), "rcu") < 0)
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panic("Failed to request rcu memory");
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/* check if all the reset register range is available */
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if (!np)
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panic("Failed to load reset resources from devicetree");
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/* remap rcu register range */
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ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start,
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resource_size(<q_rcu_resource));
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if (of_address_to_resource(np, 0, &res))
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panic("Failed to get rcu memory range");
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if (request_mem_region(res.start, resource_size(&res), res.name) < 0)
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pr_err("Failed to request rcu memory");
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ltq_rcu_membase = ioremap_nocache(res.start, resource_size(&res));
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if (!ltq_rcu_membase)
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panic("Failed to remap core memory");
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