m68knommu: Use symbolic constants for cache operations on M54xx
Now that we have meaningfull symbolic constants for bit definitions of the cache registers of m5407 and m548x chips, use them to improve readability, portability and efficiency of the cache operations. This also fixes __flush_cache_all for m548x chips : implicit DCACHE_SIZE was exact for m5407, but wrong for m548x. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
Philippe De Muyter
Greg Ungerer
parent
b3d75b09bf
commit
9c68015b14
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@ -14,7 +14,9 @@
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) __flush_cache_all()
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#define flush_cache_page(vma, vmaddr) do { } while (0)
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#ifndef flush_dcache_range
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#define flush_dcache_range(start,len) __flush_cache_all()
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#endif
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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@ -40,31 +40,75 @@
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#define ACR_CM 0x00000060 /* Cache mode mask */
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#define ACR_WPROTECT 0x00000004 /* Write protect */
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#if defined(CONFIG_M5407)
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#define ICACHE_SIZE 0x4000 /* instruction - 16k */
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#define DCACHE_SIZE 0x2000 /* data - 8k */
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#elif defined(CONFIG_M548x)
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#define ICACHE_SIZE 0x8000 /* instruction - 32k */
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#define DCACHE_SIZE 0x8000 /* data - 32k */
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#endif
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#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
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#define CACHE_WAYS 4 /* 4 ways */
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/*
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* Version 4 cores have a true harvard style separate instruction
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* and data cache. Enable data and instruction caches, also enable write
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* buffers and branch accelerator.
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*/
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/* attention : enabling CACR_DESB requires a "nop" to flush the store buffer */
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/* use '+' instead of '|' for assembler's sake */
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/* Enable data cache */
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/* Enable data store buffer */
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/* outside ACRs : No cache, precise */
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/* Enable instruction+branch caches */
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#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC)
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#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT)
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#define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY)
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#ifndef __ASSEMBLY__
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#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_WT)
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#define flush_dcache_range(a, l) do { asm("nop"); } while (0)
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#endif
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static inline void __m54xx_flush_cache_all(void)
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{
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__asm__ __volatile__ (
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#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP)
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/*
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* Use cpushl to push and invalidate all cache lines.
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* Gas doesn't seem to know how to generate the ColdFire
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* cpushl instruction... Oh well, bit stuff it for now.
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*/
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__asm__ __volatile__ (
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"nop\n\t"
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"clrl %%d0\n\t"
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"1:\n\t"
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"movel %%d0,%%a0\n\t"
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"2:\n\t"
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".word 0xf468\n\t"
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"addl #0x10,%%a0\n\t"
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"cmpl #0x00000800,%%a0\n\t"
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"addl %0,%%a0\n\t"
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"cmpl %1,%%a0\n\t"
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"blt 2b\n\t"
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"addql #1,%%d0\n\t"
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"cmpil #4,%%d0\n\t"
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"cmpil %2,%%d0\n\t"
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"bne 1b\n\t"
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"movel #0xb6088500,%%d0\n\t"
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#endif
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"movel %3,%%d0\n\t"
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"movec %%d0,%%CACR\n\t"
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: : : "d0", "a0" );
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"nop\n\t" /* forces flush of Store Buffer */
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: /* No output */
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: "i" (CACHE_LINE_SIZE),
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"i" (DCACHE_SIZE / CACHE_WAYS),
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"i" (CACHE_WAYS),
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"i" (CACHE_MODE|CACR_DCINVA|CACR_BCINVA|CACR_ICINVA)
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: "d0", "a0" );
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}
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#define __flush_cache_all() __m54xx_flush_cache_all()
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@ -108,28 +108,30 @@
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#endif /* CONFIG_M532x */
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#if defined(CONFIG_M5407) || defined(CONFIG_M548x)
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/*
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* Version 4 cores have a true harvard style separate instruction
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* and data cache. Invalidate and enable cache, also enable write
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* buffers and branch accelerator.
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*/
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#include <asm/m54xxacr.h>
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.macro CACHE_ENABLE
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movel #0x01040100,%d0 /* invalidate whole cache */
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/* invalidate whole cache */
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movel #(CACR_DCINVA+CACR_BCINVA+CACR_ICINVA),%d0
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movec %d0,%CACR
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nop
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movel #0x000fc000,%d0 /* set SDRAM cached only */
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/* addresses range for data cache : 0x00000000-0x0fffffff */
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movel #(0x000f0000+DATA_CACHE_MODE),%d0 /* set SDRAM cached */
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movec %d0, %ACR0
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movel #0x00000000,%d0 /* no other regions cached */
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movec %d0, %ACR1
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movel #0x000fc000,%d0 /* set SDRAM cached only */
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/* addresses range for instruction cache : 0x00000000-0x0fffffff */
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movel #(0x000f0000+INSN_CACHE_MODE),%d0 /* set SDRAM cached */
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movec %d0, %ACR2
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movel #0x00000000,%d0 /* no other regions cached */
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movec %d0, %ACR3
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movel #0xb6088400,%d0 /* enable caches */
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/* enable caches */
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movel #(CACHE_MODE),%d0
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movec %d0,%CACR
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nop
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.endm
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#endif /* CONFIG_M5407 */
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#endif /* CONFIG_M5407 || CONFIG_M548x */
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#if defined(CONFIG_M520x)
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.macro CACHE_ENABLE
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