arm-soc: First batch of cleanups
These cleanups are basically all over the place. The idea is to collect
changes with minimal impact but large number of changes so we can avoid
them from distracting in the diffstat in the other series.
A significant number of lines get removed here, in particular because
the ixp2000 and ixp23xx platforms get removed. These have never been
extremely popular and have fallen into disuse over time with no active
maintainer taking care of them. The u5500 soc never made it into a
product, so we are removing it from the ux500 platform.
Many good cleanups also went into the at91 and omap platforms, as has
been the case for a number of releases.
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Merge tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull first batch of arm-soc cleanups from Olof Johansson:
"These cleanups are basically all over the place. The idea is to
collect changes with minimal impact but large number of changes so we
can avoid them from distracting in the diffstat in the other series.
A significant number of lines get removed here, in particular because
the ixp2000 and ixp23xx platforms get removed. These have never been
extremely popular and have fallen into disuse over time with no active
maintainer taking care of them. The u5500 soc never made it into a
product, so we are removing it from the ux500 platform.
Many good cleanups also went into the at91 and omap platforms, as has
been the case for a number of releases."
Trivial modify-delete conflicts in arch/arm/mach-{ixp2000,ixp23xx}
* tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (152 commits)
ARM: clps711x: Cleanup IRQ handling
ARM clps711x: Removed unused header mach/time.h
ARM: clps711x: Added note about support EP731x CPU to Kconfig
ARM: clps711x: Added missing register definitions
ARM: clps711x: Used own subarch directory for store header file
Dove: Fix Section mismatch warnings
ARM: orion5x: ts78xx debugging changes
ARM: orion5x: remove PM dependency from ts78xx
ARM: orion5x: ts78xx fix NAND resource off by one
ARM: orion5x: ts78xx whitespace cleanups
Orion5x: Fix Section mismatch warnings
Orion5x: Fix warning: struct pci_dev declared inside paramter list
ARM: clps711x: Combine header files into one for clps711x-targets
ARM: S3C24XX: Use common macro to define resources on mach-qt2410.c
ARM: S3C24XX: Use common macro to define resources on mach-osiris.c
ARM: EXYNOS: Adapt to cpuidle core time keeping and irq enable
ARM: S5PV210: Use common macro to define resources on mach-smdkv210.c
ARM: S5PV210: Use common macro to define resources on dev-audio.c
ARM: S5PC100: Use common macro to define resources on dev-audio.c
ARM: S5P64X0: Use common macro to define resources on dev-audio.c
...
This commit is contained in:
Linus Torvalds
commit
9bc747bea5
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|
@ -4,8 +4,6 @@ Booting
|
|||
- requirements for booting
|
||||
Interrupts
|
||||
- ARM Interrupt subsystem documentation
|
||||
IXP2000
|
||||
- Release Notes for Linux on Intel's IXP2000 Network Processor
|
||||
msm
|
||||
- MSM specific documentation
|
||||
Netwinder
|
||||
|
|
|
|||
|
|
@ -1,69 +0,0 @@
|
|||
|
||||
-------------------------------------------------------------------------
|
||||
Release Notes for Linux on Intel's IXP2000 Network Processor
|
||||
|
||||
Maintained by Deepak Saxena <dsaxena@plexity.net>
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
1. Overview
|
||||
|
||||
Intel's IXP2000 family of NPUs (IXP2400, IXP2800, IXP2850) is designed
|
||||
for high-performance network applications such high-availability
|
||||
telecom systems. In addition to an XScale core, it contains up to 8
|
||||
"MicroEngines" that run special code, several high-end networking
|
||||
interfaces (UTOPIA, SPI, etc), a PCI host bridge, one serial port,
|
||||
flash interface, and some other odds and ends. For more information, see:
|
||||
|
||||
http://developer.intel.com
|
||||
|
||||
2. Linux Support
|
||||
|
||||
Linux currently supports the following features on the IXP2000 NPUs:
|
||||
|
||||
- On-chip serial
|
||||
- PCI
|
||||
- Flash (MTD/JFFS2)
|
||||
- I2C through GPIO
|
||||
- Timers (watchdog, OS)
|
||||
|
||||
That is about all we can support under Linux ATM b/c the core networking
|
||||
components of the chip are accessed via Intel's closed source SDK.
|
||||
Please contact Intel directly on issues with using those. There is
|
||||
also a mailing list run by some folks at Princeton University that might
|
||||
be of help: https://lists.cs.princeton.edu/mailman/listinfo/ixp2xxx
|
||||
|
||||
WHATEVER YOU DO, DO NOT POST EMAIL TO THE LINUX-ARM OR LINUX-ARM-KERNEL
|
||||
MAILING LISTS REGARDING THE INTEL SDK.
|
||||
|
||||
3. Supported Platforms
|
||||
|
||||
- Intel IXDP2400 Reference Platform
|
||||
- Intel IXDP2800 Reference Platform
|
||||
- Intel IXDP2401 Reference Platform
|
||||
- Intel IXDP2801 Reference Platform
|
||||
- RadiSys ENP-2611
|
||||
|
||||
4. Usage Notes
|
||||
|
||||
- The IXP2000 platforms usually have rather complex PCI bus topologies
|
||||
with large memory space requirements. In addition, b/c of the way the
|
||||
Intel SDK is designed, devices are enumerated in a very specific
|
||||
way. B/c of this this, we use "pci=firmware" option in the kernel
|
||||
command line so that we do not re-enumerate the bus.
|
||||
|
||||
- IXDP2x01 systems have variable clock tick rates that we cannot determine
|
||||
via HW registers. The "ixdp2x01_clk=XXX" cmd line options allow you
|
||||
to pass the clock rate to the board port.
|
||||
|
||||
5. Thanks
|
||||
|
||||
The IXP2000 work has been funded by Intel Corp. and MontaVista Software, Inc.
|
||||
|
||||
The following people have contributed patches/comments/etc:
|
||||
|
||||
Naeem F. Afzal
|
||||
Lennert Buytenhek
|
||||
Jeffrey Daly
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
Last Update: 8/09/2004
|
||||
17
MAINTAINERS
17
MAINTAINERS
|
|
@ -640,13 +640,6 @@ S: Maintained
|
|||
F: drivers/amba/
|
||||
F: include/linux/amba/bus.h
|
||||
|
||||
ARM/ADI ROADRUNNER MACHINE SUPPORT
|
||||
M: Lennert Buytenhek <kernel@wantstofly.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-ixp23xx/
|
||||
F: arch/arm/mach-ixp23xx/include/mach/
|
||||
|
||||
ARM/ADS SPHERE MACHINE SUPPORT
|
||||
M: Lennert Buytenhek <kernel@wantstofly.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
|
@ -862,21 +855,11 @@ M: Dan Williams <dan.j.williams@intel.com>
|
|||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
|
||||
ARM/INTEL IXP2000 ARM ARCHITECTURE
|
||||
M: Lennert Buytenhek <kernel@wantstofly.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
|
||||
ARM/INTEL IXDP2850 MACHINE SUPPORT
|
||||
M: Lennert Buytenhek <kernel@wantstofly.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
|
||||
ARM/INTEL IXP23XX ARM ARCHITECTURE
|
||||
M: Lennert Buytenhek <kernel@wantstofly.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
|
||||
ARM/INTEL IXP4XX ARM ARCHITECTURE
|
||||
M: Imre Kaloz <kaloz@openwrt.org>
|
||||
M: Krzysztof Halasa <khc@pm.waw.pl>
|
||||
|
|
|
|||
|
|
@ -336,8 +336,8 @@ config ARCH_AT91
|
|||
select IRQ_DOMAIN
|
||||
select NEED_MACH_IO_H if PCCARD
|
||||
help
|
||||
This enables support for systems based on the Atmel AT91RM9200,
|
||||
AT91SAM9 processors.
|
||||
This enables support for systems based on Atmel
|
||||
AT91RM9200 and AT91SAM9* processors.
|
||||
|
||||
config ARCH_BCMRING
|
||||
bool "Broadcom BCMRING"
|
||||
|
|
@ -369,12 +369,12 @@ config ARCH_HIGHBANK
|
|||
Support for the Calxeda Highbank SoC based boards.
|
||||
|
||||
config ARCH_CLPS711X
|
||||
bool "Cirrus Logic CLPS711x/EP721x-based"
|
||||
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
|
||||
select CPU_ARM720T
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select NEED_MACH_MEMORY_H
|
||||
help
|
||||
Support for Cirrus Logic 711x/721x based boards.
|
||||
Support for Cirrus Logic 711x/721x/731x based boards.
|
||||
|
||||
config ARCH_CNS3XXX
|
||||
bool "Cavium Networks CNS3XXX family"
|
||||
|
|
@ -524,28 +524,6 @@ config ARCH_IOP33X
|
|||
help
|
||||
Support for Intel's IOP33X (XScale) family of processors.
|
||||
|
||||
config ARCH_IXP23XX
|
||||
bool "IXP23XX-based"
|
||||
depends on MMU
|
||||
select CPU_XSC3
|
||||
select PCI
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select NEED_MACH_IO_H
|
||||
select NEED_MACH_MEMORY_H
|
||||
help
|
||||
Support for Intel's IXP23xx (XScale) family of processors.
|
||||
|
||||
config ARCH_IXP2000
|
||||
bool "IXP2400/2800-based"
|
||||
depends on MMU
|
||||
select CPU_XSCALE
|
||||
select PCI
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select NEED_MACH_IO_H
|
||||
select NEED_MACH_MEMORY_H
|
||||
help
|
||||
Support for Intel's IXP2400/2800 (XScale) family of processors.
|
||||
|
||||
config ARCH_IXP4XX
|
||||
bool "IXP4xx-based"
|
||||
depends on MMU
|
||||
|
|
@ -1039,10 +1017,6 @@ source "arch/arm/mach-iop13xx/Kconfig"
|
|||
|
||||
source "arch/arm/mach-ixp4xx/Kconfig"
|
||||
|
||||
source "arch/arm/mach-ixp2000/Kconfig"
|
||||
|
||||
source "arch/arm/mach-ixp23xx/Kconfig"
|
||||
|
||||
source "arch/arm/mach-kirkwood/Kconfig"
|
||||
|
||||
source "arch/arm/mach-ks8695/Kconfig"
|
||||
|
|
|
|||
|
|
@ -147,8 +147,6 @@ machine-$(CONFIG_ARCH_INTEGRATOR) := integrator
|
|||
machine-$(CONFIG_ARCH_IOP13XX) := iop13xx
|
||||
machine-$(CONFIG_ARCH_IOP32X) := iop32x
|
||||
machine-$(CONFIG_ARCH_IOP33X) := iop33x
|
||||
machine-$(CONFIG_ARCH_IXP2000) := ixp2000
|
||||
machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
|
||||
machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
|
||||
machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood
|
||||
machine-$(CONFIG_ARCH_KS8695) := ks8695
|
||||
|
|
|
|||
|
|
@ -32,10 +32,3 @@ __XScale_start:
|
|||
bic r0, r0, #0x1000 @ clear Icache
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
#ifdef CONFIG_ARCH_IXP2000
|
||||
mov r1, #-1
|
||||
mov r0, #0xd6000000
|
||||
str r1, [r0, #0x14]
|
||||
str r1, [r0, #0x18]
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -11,7 +11,5 @@ obj-$(CONFIG_DMABOUNCE) += dmabounce.o
|
|||
obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
|
||||
obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
|
||||
obj-$(CONFIG_SHARP_SCOOP) += scoop.o
|
||||
obj-$(CONFIG_ARCH_IXP2000) += uengine.o
|
||||
obj-$(CONFIG_ARCH_IXP23XX) += uengine.o
|
||||
obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
|
||||
obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
|
||||
|
|
|
|||
|
|
@ -1,507 +0,0 @@
|
|||
/*
|
||||
* Generic library functions for the microengines found on the Intel
|
||||
* IXP2000 series of network processors.
|
||||
*
|
||||
* Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
|
||||
* Dedicated to Marija Kulikova.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as
|
||||
* published by the Free Software Foundation; either version 2.1 of the
|
||||
* License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/hardware/uengine.h>
|
||||
|
||||
#if defined(CONFIG_ARCH_IXP2000)
|
||||
#define IXP_UENGINE_CSR_VIRT_BASE IXP2000_UENGINE_CSR_VIRT_BASE
|
||||
#define IXP_PRODUCT_ID IXP2000_PRODUCT_ID
|
||||
#define IXP_MISC_CONTROL IXP2000_MISC_CONTROL
|
||||
#define IXP_RESET1 IXP2000_RESET1
|
||||
#else
|
||||
#if defined(CONFIG_ARCH_IXP23XX)
|
||||
#define IXP_UENGINE_CSR_VIRT_BASE IXP23XX_UENGINE_CSR_VIRT_BASE
|
||||
#define IXP_PRODUCT_ID IXP23XX_PRODUCT_ID
|
||||
#define IXP_MISC_CONTROL IXP23XX_MISC_CONTROL
|
||||
#define IXP_RESET1 IXP23XX_RESET1
|
||||
#else
|
||||
#error unknown platform
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define USTORE_ADDRESS 0x000
|
||||
#define USTORE_DATA_LOWER 0x004
|
||||
#define USTORE_DATA_UPPER 0x008
|
||||
#define CTX_ENABLES 0x018
|
||||
#define CC_ENABLE 0x01c
|
||||
#define CSR_CTX_POINTER 0x020
|
||||
#define INDIRECT_CTX_STS 0x040
|
||||
#define ACTIVE_CTX_STS 0x044
|
||||
#define INDIRECT_CTX_SIG_EVENTS 0x048
|
||||
#define INDIRECT_CTX_WAKEUP_EVENTS 0x050
|
||||
#define NN_PUT 0x080
|
||||
#define NN_GET 0x084
|
||||
#define TIMESTAMP_LOW 0x0c0
|
||||
#define TIMESTAMP_HIGH 0x0c4
|
||||
#define T_INDEX_BYTE_INDEX 0x0f4
|
||||
#define LOCAL_CSR_STATUS 0x180
|
||||
|
||||
u32 ixp2000_uengine_mask;
|
||||
|
||||
static void *ixp2000_uengine_csr_area(int uengine)
|
||||
{
|
||||
return ((void *)IXP_UENGINE_CSR_VIRT_BASE) + (uengine << 10);
|
||||
}
|
||||
|
||||
/*
|
||||
* LOCAL_CSR_STATUS=1 after a read or write to a microengine's CSR
|
||||
* space means that the microengine we tried to access was also trying
|
||||
* to access its own CSR space on the same clock cycle as we did. When
|
||||
* this happens, we lose the arbitration process by default, and the
|
||||
* read or write we tried to do was not actually performed, so we try
|
||||
* again until it succeeds.
|
||||
*/
|
||||
u32 ixp2000_uengine_csr_read(int uengine, int offset)
|
||||
{
|
||||
void *uebase;
|
||||
u32 *local_csr_status;
|
||||
u32 *reg;
|
||||
u32 value;
|
||||
|
||||
uebase = ixp2000_uengine_csr_area(uengine);
|
||||
|
||||
local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
|
||||
reg = (u32 *)(uebase + offset);
|
||||
do {
|
||||
value = ixp2000_reg_read(reg);
|
||||
} while (ixp2000_reg_read(local_csr_status) & 1);
|
||||
|
||||
return value;
|
||||
}
|
||||
EXPORT_SYMBOL(ixp2000_uengine_csr_read);
|
||||
|
||||
void ixp2000_uengine_csr_write(int uengine, int offset, u32 value)
|
||||
{
|
||||
void *uebase;
|
||||
u32 *local_csr_status;
|
||||
u32 *reg;
|
||||
|
||||
uebase = ixp2000_uengine_csr_area(uengine);
|
||||
|
||||
local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
|
||||
reg = (u32 *)(uebase + offset);
|
||||
do {
|
||||
ixp2000_reg_write(reg, value);
|
||||
} while (ixp2000_reg_read(local_csr_status) & 1);
|
||||
}
|
||||
EXPORT_SYMBOL(ixp2000_uengine_csr_write);
|
||||
|
||||
void ixp2000_uengine_reset(u32 uengine_mask)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
value = ixp2000_reg_read(IXP_RESET1) & ~ixp2000_uengine_mask;
|
||||
|
||||
uengine_mask &= ixp2000_uengine_mask;
|
||||
ixp2000_reg_wrb(IXP_RESET1, value | uengine_mask);
|
||||
ixp2000_reg_wrb(IXP_RESET1, value);
|
||||
}
|
||||
EXPORT_SYMBOL(ixp2000_uengine_reset);
|
||||
|
||||
void ixp2000_uengine_set_mode(int uengine, u32 mode)
|
||||
{
|
||||
/*
|
||||
* CTL_STR_PAR_EN: unconditionally enable parity checking on
|
||||
* control store.
|
||||
*/
|
||||
mode |= 0x10000000;
|
||||
ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mode);
|
||||
|
||||
/*
|
||||
* Enable updating of condition codes.
|
||||
*/
|
||||
ixp2000_uengine_csr_write(uengine, CC_ENABLE, 0x00002000);
|
||||
|
||||
/*
|
||||
* Initialise other per-microengine registers.
|
||||
*/
|
||||
ixp2000_uengine_csr_write(uengine, NN_PUT, 0x00);
|
||||
ixp2000_uengine_csr_write(uengine, NN_GET, 0x00);
|
||||
ixp2000_uengine_csr_write(uengine, T_INDEX_BYTE_INDEX, 0);
|
||||
}
|
||||
EXPORT_SYMBOL(ixp2000_uengine_set_mode);
|
||||
|
||||
static int make_even_parity(u32 x)
|
||||
{
|
||||
return hweight32(x) & 1;
|
||||
}
|
||||
|
||||
static void ustore_write(int uengine, u64 insn)
|
||||
{
|
||||
/*
|
||||
* Generate even parity for top and bottom 20 bits.
|
||||
*/
|
||||
insn |= (u64)make_even_parity((insn >> 20) & 0x000fffff) << 41;
|
||||
insn |= (u64)make_even_parity(insn & 0x000fffff) << 40;
|
||||
|
||||
/*
|
||||
* Write to microstore. The second write auto-increments
|
||||
* the USTORE_ADDRESS index register.
|
||||
*/
|
||||
ixp2000_uengine_csr_write(uengine, USTORE_DATA_LOWER, (u32)insn);
|
||||
ixp2000_uengine_csr_write(uengine, USTORE_DATA_UPPER, (u32)(insn >> 32));
|
||||
}
|
||||
|
||||
void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Start writing to microstore at address 0.
|
||||
*/
|
||||
ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x80000000);
|
||||
for (i = 0; i < insns; i++) {
|
||||
u64 insn;
|
||||
|
||||
insn = (((u64)ucode[0]) << 32) |
|
||||
(((u64)ucode[1]) << 24) |
|
||||
(((u64)ucode[2]) << 16) |
|
||||
(((u64)ucode[3]) << 8) |
|
||||
((u64)ucode[4]);
|
||||
ucode += 5;
|
||||
|
||||
ustore_write(uengine, insn);
|
||||
}
|
||||
|
||||
/*
|
||||
* Pad with a few NOPs at the end (to avoid the microengine
|
||||
* aborting as it prefetches beyond the last instruction), unless
|
||||
* we run off the end of the instruction store first, at which
|
||||
* point the address register will wrap back to zero.
|
||||
*/
|
||||
for (i = 0; i < 4; i++) {
|
||||
u32 addr;
|
||||
|
||||
addr = ixp2000_uengine_csr_read(uengine, USTORE_ADDRESS);
|
||||
if (addr == 0x80000000)
|
||||
break;
|
||||
ustore_write(uengine, 0xf0000c0300ULL);
|
||||
}
|
||||
|
||||
/*
|
||||
* End programming.
|
||||
*/
|
||||
ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x00000000);
|
||||
}
|
||||
EXPORT_SYMBOL(ixp2000_uengine_load_microcode);
|
||||
|
||||
void ixp2000_uengine_init_context(int uengine, int context, int pc)
|
||||
{
|
||||
/*
|
||||
* Select the right context for indirect access.
|
||||
*/
|
||||
ixp2000_uengine_csr_write(uengine, CSR_CTX_POINTER, context);
|
||||
|
||||
/*
|
||||
* Initialise signal masks to immediately go to Ready state.
|
||||
*/
|
||||
ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_SIG_EVENTS, 1);
|
||||
ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_WAKEUP_EVENTS, 1);
|
||||
|
||||
/*
|
||||
* Set program counter.
|
||||
*/
|
||||
ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_STS, pc);
|
||||
}
|
||||
EXPORT_SYMBOL(ixp2000_uengine_init_context);
|
||||
|
||||
void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask)
|
||||
{
|
||||
u32 mask;
|
||||
|
||||
/*
|
||||
* Enable the specified context to go to Executing state.
|
||||
*/
|
||||
mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
|
||||
mask |= ctx_mask << 8;
|
||||
ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
|
||||
}
|
||||
EXPORT_SYMBOL(ixp2000_uengine_start_contexts);
|
||||
|
||||
void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask)
|
||||
{
|
||||
u32 mask;
|
||||
|
||||
/*
|
||||
* Disable the Ready->Executing transition. Note that this
|
||||
* does not stop the context until it voluntarily yields.
|
||||
*/
|
||||
mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
|
||||
mask &= ~(ctx_mask << 8);
|
||||
ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
|
||||
}
|
||||
EXPORT_SYMBOL(ixp2000_uengine_stop_contexts);
|
||||
|
||||
static int check_ixp_type(struct ixp2000_uengine_code *c)
|
||||
{
|
||||
u32 product_id;
|
||||
u32 rev;
|
||||
|
||||
product_id = ixp2000_reg_read(IXP_PRODUCT_ID);
|
||||
if (((product_id >> 16) & 0x1f) != 0)
|
||||
return 0;
|
||||
|
||||
switch ((product_id >> 8) & 0xff) {
|
||||
#ifdef CONFIG_ARCH_IXP2000
|
||||
case 0: /* IXP2800 */
|
||||
if (!(c->cpu_model_bitmask & 4))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case 1: /* IXP2850 */
|
||||
if (!(c->cpu_model_bitmask & 8))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case 2: /* IXP2400 */
|
||||
if (!(c->cpu_model_bitmask & 2))
|
||||
return 0;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_IXP23XX
|
||||
case 4: /* IXP23xx */
|
||||
if (!(c->cpu_model_bitmask & 0x3f0))
|
||||
return 0;
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
rev = product_id & 0xff;
|
||||
if (rev < c->cpu_min_revision || rev > c->cpu_max_revision)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b)
|
||||
{
|
||||
int offset;
|
||||
int i;
|
||||
|
||||
offset = 0;
|
||||
|
||||
for (i = 0; i < 128; i++) {
|
||||
u8 b3;
|
||||
u8 b2;
|
||||
u8 b1;
|
||||
u8 b0;
|
||||
|
||||
b3 = (gpr_a[i] >> 24) & 0xff;
|
||||
b2 = (gpr_a[i] >> 16) & 0xff;
|
||||
b1 = (gpr_a[i] >> 8) & 0xff;
|
||||
b0 = gpr_a[i] & 0xff;
|
||||
|
||||
/* immed[@ai, (b1 << 8) | b0] */
|
||||
/* 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII */
|
||||
ucode[offset++] = 0xf0;
|
||||
ucode[offset++] = (b1 >> 4);
|
||||
ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6);
|
||||
ucode[offset++] = (b0 << 2);
|
||||
ucode[offset++] = 0x80 | i;
|
||||
|
||||
/* immed_w1[@ai, (b3 << 8) | b2] */
|
||||
/* 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII */
|
||||
ucode[offset++] = 0xf4;
|
||||
ucode[offset++] = 0x40 | (b3 >> 4);
|
||||
ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6);
|
||||
ucode[offset++] = (b2 << 2);
|
||||
ucode[offset++] = 0x80 | i;
|
||||
}
|
||||
|
||||
for (i = 0; i < 128; i++) {
|
||||
u8 b3;
|
||||
u8 b2;
|
||||
u8 b1;
|
||||
u8 b0;
|
||||
|
||||
b3 = (gpr_b[i] >> 24) & 0xff;
|
||||
b2 = (gpr_b[i] >> 16) & 0xff;
|
||||
b1 = (gpr_b[i] >> 8) & 0xff;
|
||||
b0 = gpr_b[i] & 0xff;
|
||||
|
||||
/* immed[@bi, (b1 << 8) | b0] */
|
||||
/* 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV */
|
||||
ucode[offset++] = 0xf0;
|
||||
ucode[offset++] = (b1 >> 4);
|
||||
ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6);
|
||||
ucode[offset++] = (i << 2) | 0x03;
|
||||
ucode[offset++] = b0;
|
||||
|
||||
/* immed_w1[@bi, (b3 << 8) | b2] */
|
||||
/* 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV */
|
||||
ucode[offset++] = 0xf4;
|
||||
ucode[offset++] = 0x40 | (b3 >> 4);
|
||||
ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6);
|
||||
ucode[offset++] = (i << 2) | 0x03;
|
||||
ucode[offset++] = b2;
|
||||
}
|
||||
|
||||
/* ctx_arb[kill] */
|
||||
ucode[offset++] = 0xe0;
|
||||
ucode[offset++] = 0x00;
|
||||
ucode[offset++] = 0x01;
|
||||
ucode[offset++] = 0x00;
|
||||
ucode[offset++] = 0x00;
|
||||
}
|
||||
|
||||
static int set_initial_registers(int uengine, struct ixp2000_uengine_code *c)
|
||||
{
|
||||
int per_ctx_regs;
|
||||
u32 *gpr_a;
|
||||
u32 *gpr_b;
|
||||
u8 *ucode;
|
||||
int i;
|
||||
|
||||
gpr_a = kzalloc(128 * sizeof(u32), GFP_KERNEL);
|
||||
gpr_b = kzalloc(128 * sizeof(u32), GFP_KERNEL);
|
||||
ucode = kmalloc(513 * 5, GFP_KERNEL);
|
||||
if (gpr_a == NULL || gpr_b == NULL || ucode == NULL) {
|
||||
kfree(ucode);
|
||||
kfree(gpr_b);
|
||||
kfree(gpr_a);
|
||||
return 1;
|
||||
}
|
||||
|
||||
per_ctx_regs = 16;
|
||||
if (c->uengine_parameters & IXP2000_UENGINE_4_CONTEXTS)
|
||||
per_ctx_regs = 32;
|
||||
|
||||
for (i = 0; i < 256; i++) {
|
||||
struct ixp2000_reg_value *r = c->initial_reg_values + i;
|
||||
u32 *bank;
|
||||
int inc;
|
||||
int j;
|
||||
|
||||
if (r->reg == -1)
|
||||
break;
|
||||
|
||||
bank = (r->reg & 0x400) ? gpr_b : gpr_a;
|
||||
inc = (r->reg & 0x80) ? 128 : per_ctx_regs;
|
||||
|
||||
j = r->reg & 0x7f;
|
||||
while (j < 128) {
|
||||
bank[j] = r->value;
|
||||
j += inc;
|
||||
}
|
||||
}
|
||||
|
||||
generate_ucode(ucode, gpr_a, gpr_b);
|
||||
ixp2000_uengine_load_microcode(uengine, ucode, 513);
|
||||
ixp2000_uengine_init_context(uengine, 0, 0);
|
||||
ixp2000_uengine_start_contexts(uengine, 0x01);
|
||||
for (i = 0; i < 100; i++) {
|
||||
u32 status;
|
||||
|
||||
status = ixp2000_uengine_csr_read(uengine, ACTIVE_CTX_STS);
|
||||
if (!(status & 0x80000000))
|
||||
break;
|
||||
}
|
||||
ixp2000_uengine_stop_contexts(uengine, 0x01);
|
||||
|
||||
kfree(ucode);
|
||||
kfree(gpr_b);
|
||||
kfree(gpr_a);
|
||||
|
||||
return !!(i == 100);
|
||||
}
|
||||
|
||||
int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c)
|
||||
{
|
||||
int ctx;
|
||||
|
||||
if (!check_ixp_type(c))
|
||||
return 1;
|
||||
|
||||
if (!(ixp2000_uengine_mask & (1 << uengine)))
|
||||
return 1;
|
||||
|
||||
ixp2000_uengine_reset(1 << uengine);
|
||||
ixp2000_uengine_set_mode(uengine, c->uengine_parameters);
|
||||
if (set_initial_registers(uengine, c))
|
||||
return 1;
|
||||
ixp2000_uengine_load_microcode(uengine, c->insns, c->num_insns);
|
||||
|
||||
for (ctx = 0; ctx < 8; ctx++)
|
||||
ixp2000_uengine_init_context(uengine, ctx, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(ixp2000_uengine_load);
|
||||
|
||||
|
||||
static int __init ixp2000_uengine_init(void)
|
||||
{
|
||||
int uengine;
|
||||
u32 value;
|
||||
|
||||
/*
|
||||
* Determine number of microengines present.
|
||||
*/
|
||||
switch ((ixp2000_reg_read(IXP_PRODUCT_ID) >> 8) & 0x1fff) {
|
||||
#ifdef CONFIG_ARCH_IXP2000
|
||||
case 0: /* IXP2800 */
|
||||
case 1: /* IXP2850 */
|
||||
ixp2000_uengine_mask = 0x00ff00ff;
|
||||
break;
|
||||
|
||||
case 2: /* IXP2400 */
|
||||
ixp2000_uengine_mask = 0x000f000f;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_IXP23XX
|
||||
case 4: /* IXP23xx */
|
||||
ixp2000_uengine_mask = (*IXP23XX_EXP_CFG_FUSE >> 8) & 0xf;
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
printk(KERN_INFO "Detected unknown IXP2000 model (%.8x)\n",
|
||||
(unsigned int)ixp2000_reg_read(IXP_PRODUCT_ID));
|
||||
ixp2000_uengine_mask = 0x00000000;
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset microengines.
|
||||
*/
|
||||
ixp2000_uengine_reset(ixp2000_uengine_mask);
|
||||
|
||||
/*
|
||||
* Synchronise timestamp counters across all microengines.
|
||||
*/
|
||||
value = ixp2000_reg_read(IXP_MISC_CONTROL);
|
||||
ixp2000_reg_wrb(IXP_MISC_CONTROL, value & ~0x80);
|
||||
for (uengine = 0; uengine < 32; uengine++) {
|
||||
if (ixp2000_uengine_mask & (1 << uengine)) {
|
||||
ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
|
||||
ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);
|
||||
}
|
||||
}
|
||||
ixp2000_reg_wrb(IXP_MISC_CONTROL, value | 0x80);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
subsys_initcall(ixp2000_uengine_init);
|
||||
|
|
@ -0,0 +1,196 @@
|
|||
CONFIG_EXPERIMENTAL=y
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_LBDAF is not set
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SOC_AT91SAM9260=y
|
||||
CONFIG_SOC_AT91SAM9263=y
|
||||
CONFIG_SOC_AT91SAM9G45=y
|
||||
CONFIG_SOC_AT91SAM9X5=y
|
||||
CONFIG_MACH_AT91SAM_DT=y
|
||||
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
|
||||
CONFIG_AT91_TIMER_HZ=128
|
||||
CONFIG_AEABI=y
|
||||
# CONFIG_OABI_COMPAT is not set
|
||||
CONFIG_LEDS=y
|
||||
CONFIG_LEDS_CPU=y
|
||||
CONFIG_UACCESS_WITH_MEMCPY=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_ARM_ATAG_DTB_COMPAT=y
|
||||
CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
|
||||
CONFIG_KEXEC=y
|
||||
CONFIG_AUTO_ZRELADDR=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_PNP=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_IPV6=y
|
||||
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET6_XFRM_MODE_BEET is not set
|
||||
CONFIG_IPV6_SIT_6RD=y
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_ATMEL=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_GLUEBI=y
|
||||
CONFIG_PROC_DEVICETREE=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_COUNT=4
|
||||
CONFIG_BLK_DEV_RAM_SIZE=8192
|
||||
CONFIG_ATMEL_PWM=y
|
||||
CONFIG_ATMEL_TCLIB=y
|
||||
CONFIG_EEPROM_93CX6=m
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_SCSI_MULTI_LUN=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_MACB=y
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_CHELSIO is not set
|
||||
# CONFIG_NET_VENDOR_FARADAY is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
# CONFIG_NET_VENDOR_SMSC is not set
|
||||
# CONFIG_NET_VENDOR_STMICRO is not set
|
||||
CONFIG_DAVICOM_PHY=y
|
||||
CONFIG_MICREL_PHY=y
|
||||
# CONFIG_WLAN is not set
|
||||
CONFIG_INPUT_POLLDEV=y
|
||||
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272
|
||||
CONFIG_INPUT_JOYDEV=y
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_KEYBOARD_ATKBD is not set
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
# CONFIG_SERIO is not set
|
||||
CONFIG_LEGACY_PTY_COUNT=4
|
||||
CONFIG_SERIAL_ATMEL=y
|
||||
CONFIG_SERIAL_ATMEL_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_GPIO=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_ATMEL=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_AT91SAM9X_WATCHDOG=y
|
||||
CONFIG_SSB=m
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_MODE_HELPERS=y
|
||||
CONFIG_FB_ATMEL=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
# CONFIG_LCD_CLASS_DEVICE is not set
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_BACKLIGHT_ATMEL_LCDC=y
|
||||
# CONFIG_BACKLIGHT_GENERIC is not set
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
CONFIG_FONTS=y
|
||||
CONFIG_FONT_8x8=y
|
||||
CONFIG_FONT_ACORN_8x8=y
|
||||
CONFIG_FONT_MINI_4x6=y
|
||||
CONFIG_LOGO=y
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_DEVICEFS=y
|
||||
# CONFIG_USB_DEVICE_CLASS is not set
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_ACM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_SERIAL=y
|
||||
CONFIG_USB_SERIAL_GENERIC=y
|
||||
CONFIG_USB_SERIAL_FTDI_SIO=y
|
||||
CONFIG_USB_SERIAL_PL2303=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_AT91=m
|
||||
CONFIG_USB_ATMEL_USBA=m
|
||||
CONFIG_USB_ETH=m
|
||||
CONFIG_USB_GADGETFS=m
|
||||
CONFIG_USB_CDC_COMPOSITE=m
|
||||
CONFIG_USB_G_ACM_MS=m
|
||||
CONFIG_USB_G_MULTI=m
|
||||
CONFIG_USB_G_MULTI_CDC=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_ATMELMCI=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_TIMER=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_LEDS_TRIGGER_GPIO=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_AT91RM9200=y
|
||||
CONFIG_RTC_DRV_AT91SAM9=y
|
||||
CONFIG_DMADEVICES=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_FANOTIFY=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_CODEPAGE_850=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_STRIP_ASM_SYMS=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_CRYPTO=y
|
||||
CONFIG_CRYPTO_ECB=y
|
||||
CONFIG_CRYPTO_AES=y
|
||||
CONFIG_CRYPTO_ARC4=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
CONFIG_CRYPTO_USER_API_HASH=m
|
||||
CONFIG_CRYPTO_USER_API_SKCIPHER=m
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
CONFIG_CRC_CCITT=m
|
||||
CONFIG_CRC_ITU_T=m
|
||||
CONFIG_CRC7=m
|
||||
CONFIG_AVERAGE=y
|
||||
|
|
@ -14,6 +14,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y
|
|||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_ARCH_AT91RM9200=y
|
||||
CONFIG_MACH_ONEARM=y
|
||||
CONFIG_ARCH_AT91RM9200DK=y
|
||||
CONFIG_MACH_AT91RM9200EK=y
|
||||
|
|
|
|||
|
|
@ -1,99 +0,0 @@
|
|||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EXPERT=y
|
||||
# CONFIG_HOTPLUG is not set
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_ARCH_IXP2000=y
|
||||
CONFIG_ARCH_ENP2611=y
|
||||
CONFIG_ARCH_IXDP2400=y
|
||||
CONFIG_ARCH_IXDP2800=y
|
||||
CONFIG_ARCH_IXDP2401=y
|
||||
CONFIG_ARCH_IXDP2801=y
|
||||
# CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO is not set
|
||||
# CONFIG_ARM_THUMB is not set
|
||||
CONFIG_CPU_BIG_ENDIAN=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="console=ttyS0,57600 root=/dev/nfs ip=bootp mem=64M@0x0"
|
||||
CONFIG_FPE_NWFPE=y
|
||||
CONFIG_FPE_NWFPE_XP=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
CONFIG_IPV6=y
|
||||
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET6_XFRM_MODE_BEET is not set
|
||||
# CONFIG_IPV6_SIT is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_PARTITIONS=y
|
||||
CONFIG_MTD_REDBOOT_PARTS=y
|
||||
CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
|
||||
CONFIG_MTD_REDBOOT_PARTS_READONLY=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_COMPLEX_MAPPINGS=y
|
||||
CONFIG_MTD_IXP2000=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_NBD=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=8192
|
||||
CONFIG_EEPROM_LEGACY=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_NET_PCI=y
|
||||
CONFIG_CS89x0=y
|
||||
CONFIG_E100=y
|
||||
CONFIG_ENP2611_MSF_NET=y
|
||||
CONFIG_WAN=y
|
||||
CONFIG_HDLC=y
|
||||
CONFIG_HDLC_RAW=y
|
||||
CONFIG_HDLC_CISCO=y
|
||||
CONFIG_HDLC_FR=y
|
||||
CONFIG_HDLC_PPP=y
|
||||
CONFIG_DLCI=y
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=3
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_IXP2000=y
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_IXP2000_WATCHDOG=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT3_FS_POSIX_ACL=y
|
||||
CONFIG_INOTIFY=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_DEBUG_ERRORS=y
|
||||
CONFIG_DEBUG_LL=y
|
||||
|
|
@ -1,105 +0,0 @@
|
|||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EXPERT=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_ARCH_IXP23XX=y
|
||||
CONFIG_MACH_ESPRESSO=y
|
||||
CONFIG_MACH_IXDP2351=y
|
||||
CONFIG_MACH_ROADRUNNER=y
|
||||
# CONFIG_ARM_THUMB is not set
|
||||
CONFIG_CPU_BIG_ENDIAN=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp"
|
||||
CONFIG_FPE_NWFPE=y
|
||||
CONFIG_FPE_NWFPE_XP=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
CONFIG_IPV6=y
|
||||
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET6_XFRM_MODE_BEET is not set
|
||||
# CONFIG_IPV6_SIT is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
# CONFIG_FW_LOADER is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_PARTITIONS=y
|
||||
CONFIG_MTD_REDBOOT_PARTS=y
|
||||
CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
|
||||
CONFIG_MTD_REDBOOT_PARTS_READONLY=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_COMPLEX_MAPPINGS=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_NBD=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=8192
|
||||
CONFIG_EEPROM_LEGACY=y
|
||||
CONFIG_IDE=y
|
||||
CONFIG_BLK_DEV_SIIMAGE=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_NET_PCI=y
|
||||
CONFIG_E100=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_WAN=y
|
||||
CONFIG_HDLC=y
|
||||
CONFIG_HDLC_RAW=y
|
||||
CONFIG_HDLC_CISCO=y
|
||||
CONFIG_HDLC_FR=y
|
||||
CONFIG_HDLC_PPP=y
|
||||
CONFIG_DLCI=y
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_WATCHDOG=y
|
||||
# CONFIG_USB_HID is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_MON=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_UHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT3_FS_POSIX_ACL=y
|
||||
CONFIG_INOTIFY=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_DEBUG_ERRORS=y
|
||||
CONFIG_DEBUG_LL=y
|
||||
|
|
@ -1,49 +0,0 @@
|
|||
/*
|
||||
* arch/arm/include/asm/hardware/cs89712.h
|
||||
*
|
||||
* This file contains the hardware definitions of the CS89712
|
||||
* additional internal registers.
|
||||
*
|
||||
* Copyright (C) 2001 Thomas Gleixner autronix automation <gleixner@autronix.de>
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASM_HARDWARE_CS89712_H
|
||||
#define __ASM_HARDWARE_CS89712_H
|
||||
|
||||
/*
|
||||
* CS89712 additional registers
|
||||
*/
|
||||
|
||||
#define PCDR 0x0002 /* Port C Data register ---------------------------- */
|
||||
#define PCDDR 0x0042 /* Port C Data Direction register ------------------ */
|
||||
#define SDCONF 0x2300 /* SDRAM Configuration register ---------------------*/
|
||||
#define SDRFPR 0x2340 /* SDRAM Refresh period register --------------------*/
|
||||
|
||||
#define SDCONF_ACTIVE (1 << 10)
|
||||
#define SDCONF_CLKCTL (1 << 9)
|
||||
#define SDCONF_WIDTH_4 (0 << 7)
|
||||
#define SDCONF_WIDTH_8 (1 << 7)
|
||||
#define SDCONF_WIDTH_16 (2 << 7)
|
||||
#define SDCONF_WIDTH_32 (3 << 7)
|
||||
#define SDCONF_SIZE_16 (0 << 5)
|
||||
#define SDCONF_SIZE_64 (1 << 5)
|
||||
#define SDCONF_SIZE_128 (2 << 5)
|
||||
#define SDCONF_SIZE_256 (3 << 5)
|
||||
#define SDCONF_CASLAT_2 (2)
|
||||
#define SDCONF_CASLAT_3 (3)
|
||||
|
||||
#endif /* __ASM_HARDWARE_CS89712_H */
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/*
|
||||
* arch/arm/include/asm/hardware/ep7211.h
|
||||
*
|
||||
* This file contains the hardware definitions of the EP7211 internal
|
||||
* registers.
|
||||
*
|
||||
* Copyright (C) 2001 Blue Mug, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASM_HARDWARE_EP7211_H
|
||||
#define __ASM_HARDWARE_EP7211_H
|
||||
|
||||
#include <asm/hardware/clps7111.h>
|
||||
|
||||
/*
|
||||
* define EP7211_BASE to be the base address of the region
|
||||
* you want to access.
|
||||
*/
|
||||
|
||||
#define EP7211_PHYS_BASE (0x80000000)
|
||||
|
||||
/*
|
||||
* XXX miket@bluemug.com: need to introduce EP7211 registers (those not
|
||||
* present in 7212) here.
|
||||
*/
|
||||
|
||||
#endif /* __ASM_HARDWARE_EP7211_H */
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
/*
|
||||
* arch/arm/include/asm/hardware/ep7212.h
|
||||
*
|
||||
* This file contains the hardware definitions of the EP7212 internal
|
||||
* registers.
|
||||
*
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASM_HARDWARE_EP7212_H
|
||||
#define __ASM_HARDWARE_EP7212_H
|
||||
|
||||
/*
|
||||
* define EP7212_BASE to be the base address of the region
|
||||
* you want to access.
|
||||
*/
|
||||
|
||||
#define EP7212_PHYS_BASE (0x80000000)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define ep_readl(off) __raw_readl(EP7212_BASE + (off))
|
||||
#define ep_writel(val,off) __raw_writel(val, EP7212_BASE + (off))
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These registers are specific to the EP7212 only
|
||||
*/
|
||||
#define DAIR 0x2000
|
||||
#define DAIR0 0x2040
|
||||
#define DAIDR1 0x2080
|
||||
#define DAIDR2 0x20c0
|
||||
#define DAISR 0x2100
|
||||
#define SYSCON3 0x2200
|
||||
#define INTSR3 0x2240
|
||||
#define INTMR3 0x2280
|
||||
#define LEDFLSH 0x22c0
|
||||
|
||||
#define DAIR_DAIEN (1 << 16)
|
||||
#define DAIR_ECS (1 << 17)
|
||||
#define DAIR_LCTM (1 << 19)
|
||||
#define DAIR_LCRM (1 << 20)
|
||||
#define DAIR_RCTM (1 << 21)
|
||||
#define DAIR_RCRM (1 << 22)
|
||||
#define DAIR_LBM (1 << 23)
|
||||
|
||||
#define DAIDR2_FIFOEN (1 << 15)
|
||||
#define DAIDR2_FIFOLEFT (0x0d << 16)
|
||||
#define DAIDR2_FIFORIGHT (0x11 << 16)
|
||||
|
||||
#define DAISR_RCTS (1 << 0)
|
||||
#define DAISR_RCRS (1 << 1)
|
||||
#define DAISR_LCTS (1 << 2)
|
||||
#define DAISR_LCRS (1 << 3)
|
||||
#define DAISR_RCTU (1 << 4)
|
||||
#define DAISR_RCRO (1 << 5)
|
||||
#define DAISR_LCTU (1 << 6)
|
||||
#define DAISR_LCRO (1 << 7)
|
||||
#define DAISR_RCNF (1 << 8)
|
||||
#define DAISR_RCNE (1 << 9)
|
||||
#define DAISR_LCNF (1 << 10)
|
||||
#define DAISR_LCNE (1 << 11)
|
||||
#define DAISR_FIFO (1 << 12)
|
||||
|
||||
#define SYSCON3_ADCCON (1 << 0)
|
||||
#define SYSCON3_DAISEL (1 << 3)
|
||||
#define SYSCON3_ADCCKNSEN (1 << 4)
|
||||
#define SYSCON3_FASTWAKE (1 << 8)
|
||||
#define SYSCON3_DAIEN (1 << 9)
|
||||
|
||||
#endif /* __ASM_HARDWARE_EP7212_H */
|
||||
|
|
@ -1,62 +0,0 @@
|
|||
/*
|
||||
* Generic library functions for the microengines found on the Intel
|
||||
* IXP2000 series of network processors.
|
||||
*
|
||||
* Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
|
||||
* Dedicated to Marija Kulikova.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as
|
||||
* published by the Free Software Foundation; either version 2.1 of the
|
||||
* License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __IXP2000_UENGINE_H
|
||||
#define __IXP2000_UENGINE_H
|
||||
|
||||
extern u32 ixp2000_uengine_mask;
|
||||
|
||||
struct ixp2000_uengine_code
|
||||
{
|
||||
u32 cpu_model_bitmask;
|
||||
u8 cpu_min_revision;
|
||||
u8 cpu_max_revision;
|
||||
|
||||
u32 uengine_parameters;
|
||||
|
||||
struct ixp2000_reg_value {
|
||||
int reg;
|
||||
u32 value;
|
||||
} *initial_reg_values;
|
||||
|
||||
int num_insns;
|
||||
u8 *insns;
|
||||
};
|
||||
|
||||
u32 ixp2000_uengine_csr_read(int uengine, int offset);
|
||||
void ixp2000_uengine_csr_write(int uengine, int offset, u32 value);
|
||||
void ixp2000_uengine_reset(u32 uengine_mask);
|
||||
void ixp2000_uengine_set_mode(int uengine, u32 mode);
|
||||
void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns);
|
||||
void ixp2000_uengine_init_context(int uengine, int context, int pc);
|
||||
void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask);
|
||||
void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask);
|
||||
int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c);
|
||||
|
||||
#define IXP2000_UENGINE_8_CONTEXTS 0x00000000
|
||||
#define IXP2000_UENGINE_4_CONTEXTS 0x80000000
|
||||
#define IXP2000_UENGINE_PRN_UPDATE_EVERY 0x40000000
|
||||
#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS 0x00000000
|
||||
#define IXP2000_UENGINE_NN_FROM_SELF 0x00100000
|
||||
#define IXP2000_UENGINE_NN_FROM_PREVIOUS 0x00000000
|
||||
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3 0x000c0000
|
||||
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2 0x00080000
|
||||
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1 0x00040000
|
||||
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0 0x00000000
|
||||
#define IXP2000_UENGINE_LM_ADDR1_GLOBAL 0x00020000
|
||||
#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT 0x00000000
|
||||
#define IXP2000_UENGINE_LM_ADDR0_GLOBAL 0x00010000
|
||||
#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT 0x00000000
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -9,15 +9,6 @@ config HAVE_AT91_DBGU0
|
|||
config HAVE_AT91_DBGU1
|
||||
bool
|
||||
|
||||
config HAVE_AT91_USART3
|
||||
bool
|
||||
|
||||
config HAVE_AT91_USART4
|
||||
bool
|
||||
|
||||
config HAVE_AT91_USART5
|
||||
bool
|
||||
|
||||
config AT91_SAM9_ALT_RESET
|
||||
bool
|
||||
default !ARCH_AT91X40
|
||||
|
|
@ -26,87 +17,121 @@ config AT91_SAM9G45_RESET
|
|||
bool
|
||||
default !ARCH_AT91X40
|
||||
|
||||
config SOC_AT91SAM9
|
||||
bool
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select CPU_ARM926T
|
||||
|
||||
menu "Atmel AT91 System-on-Chip"
|
||||
|
||||
choice
|
||||
prompt "Atmel AT91 Processor"
|
||||
comment "Atmel AT91 Processor"
|
||||
|
||||
config ARCH_AT91RM9200
|
||||
config SOC_AT91SAM9
|
||||
bool
|
||||
select CPU_ARM926T
|
||||
select AT91_SAM9_TIME
|
||||
select AT91_SAM9_SMC
|
||||
|
||||
config SOC_AT91RM9200
|
||||
bool "AT91RM9200"
|
||||
select CPU_ARM920T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_AT91_DBGU0
|
||||
select HAVE_AT91_USART3
|
||||
|
||||
config SOC_AT91SAM9260
|
||||
bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20"
|
||||
select SOC_AT91SAM9
|
||||
select HAVE_AT91_DBGU0
|
||||
select HAVE_NET_MACB
|
||||
help
|
||||
Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE
|
||||
or AT91SAM9G20 SoC.
|
||||
|
||||
config SOC_AT91SAM9261
|
||||
bool "AT91SAM9261 or AT91SAM9G10"
|
||||
select SOC_AT91SAM9
|
||||
select HAVE_AT91_DBGU0
|
||||
select HAVE_FB_ATMEL
|
||||
help
|
||||
Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC.
|
||||
|
||||
config SOC_AT91SAM9263
|
||||
bool "AT91SAM9263"
|
||||
select SOC_AT91SAM9
|
||||
select HAVE_AT91_DBGU1
|
||||
select HAVE_FB_ATMEL
|
||||
select HAVE_NET_MACB
|
||||
|
||||
config SOC_AT91SAM9RL
|
||||
bool "AT91SAM9RL"
|
||||
select SOC_AT91SAM9
|
||||
select HAVE_AT91_DBGU0
|
||||
select HAVE_FB_ATMEL
|
||||
|
||||
config SOC_AT91SAM9G45
|
||||
bool "AT91SAM9G45 or AT91SAM9M10 families"
|
||||
select SOC_AT91SAM9
|
||||
select HAVE_AT91_DBGU1
|
||||
select HAVE_FB_ATMEL
|
||||
select HAVE_NET_MACB
|
||||
help
|
||||
Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
|
||||
This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
|
||||
|
||||
config SOC_AT91SAM9X5
|
||||
bool "AT91SAM9x5 family"
|
||||
select SOC_AT91SAM9
|
||||
select HAVE_AT91_DBGU0
|
||||
select HAVE_FB_ATMEL
|
||||
select HAVE_NET_MACB
|
||||
help
|
||||
Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
|
||||
This means that your SAM9 name finishes with a '5' (except if it is
|
||||
AT91SAM9G45!).
|
||||
This support covers AT91SAM9G15, AT91SAM9G25, AT91SAM9X25, AT91SAM9G35
|
||||
and AT91SAM9X35.
|
||||
|
||||
choice
|
||||
prompt "Atmel AT91 Processor Devices for non DT boards"
|
||||
|
||||
config ARCH_AT91_NONE
|
||||
bool "None"
|
||||
|
||||
config ARCH_AT91RM9200
|
||||
bool "AT91RM9200"
|
||||
select SOC_AT91RM9200
|
||||
|
||||
config ARCH_AT91SAM9260
|
||||
bool "AT91SAM9260 or AT91SAM9XE"
|
||||
select CPU_ARM926T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_AT91_DBGU0
|
||||
select HAVE_AT91_USART3
|
||||
select HAVE_AT91_USART4
|
||||
select HAVE_AT91_USART5
|
||||
select HAVE_NET_MACB
|
||||
select SOC_AT91SAM9260
|
||||
|
||||
config ARCH_AT91SAM9261
|
||||
bool "AT91SAM9261"
|
||||
select CPU_ARM926T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_FB_ATMEL
|
||||
select HAVE_AT91_DBGU0
|
||||
select SOC_AT91SAM9261
|
||||
|
||||
config ARCH_AT91SAM9G10
|
||||
bool "AT91SAM9G10"
|
||||
select CPU_ARM926T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_AT91_DBGU0
|
||||
select HAVE_FB_ATMEL
|
||||
select SOC_AT91SAM9261
|
||||
|
||||
config ARCH_AT91SAM9263
|
||||
bool "AT91SAM9263"
|
||||
select CPU_ARM926T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_FB_ATMEL
|
||||
select HAVE_NET_MACB
|
||||
select HAVE_AT91_DBGU1
|
||||
select SOC_AT91SAM9263
|
||||
|
||||
config ARCH_AT91SAM9RL
|
||||
bool "AT91SAM9RL"
|
||||
select CPU_ARM926T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_AT91_USART3
|
||||
select HAVE_FB_ATMEL
|
||||
select HAVE_AT91_DBGU0
|
||||
select SOC_AT91SAM9RL
|
||||
|
||||
config ARCH_AT91SAM9G20
|
||||
bool "AT91SAM9G20"
|
||||
select CPU_ARM926T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_AT91_DBGU0
|
||||
select HAVE_AT91_USART3
|
||||
select HAVE_AT91_USART4
|
||||
select HAVE_AT91_USART5
|
||||
select HAVE_NET_MACB
|
||||
select SOC_AT91SAM9260
|
||||
|
||||
config ARCH_AT91SAM9G45
|
||||
bool "AT91SAM9G45"
|
||||
select CPU_ARM926T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_AT91_USART3
|
||||
select HAVE_FB_ATMEL
|
||||
select HAVE_NET_MACB
|
||||
select HAVE_AT91_DBGU1
|
||||
|
||||
config ARCH_AT91SAM9X5
|
||||
bool "AT91SAM9x5 family"
|
||||
select CPU_ARM926T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_FB_ATMEL
|
||||
select HAVE_NET_MACB
|
||||
select HAVE_AT91_DBGU0
|
||||
select SOC_AT91SAM9G45
|
||||
|
||||
config ARCH_AT91X40
|
||||
bool "AT91x40"
|
||||
depends on !MMU
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
|
||||
endchoice
|
||||
|
|
@ -364,6 +389,7 @@ config MACH_AT91SAM9G20EK_2MMC
|
|||
Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit
|
||||
with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and
|
||||
onwards.
|
||||
<http://www.atmel.com/tools/SAM9G20-EK.aspx>
|
||||
|
||||
config MACH_CPU9G20
|
||||
bool "Eukrea CPU9G20 board"
|
||||
|
|
@ -433,9 +459,10 @@ comment "AT91SAM9G45 Board Type"
|
|||
config MACH_AT91SAM9M10G45EK
|
||||
bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
|
||||
help
|
||||
Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit.
|
||||
"ES" at the end of the name means that this board is an
|
||||
Engineering Sample.
|
||||
Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit.
|
||||
Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10
|
||||
families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
|
||||
<http://www.atmel.com/tools/SAM9M10-G45-EK.aspx>
|
||||
|
||||
endif
|
||||
|
||||
|
|
@ -515,41 +542,6 @@ config AT91_TIMER_HZ
|
|||
system clock (of at least several MHz), rounding is less of a
|
||||
problem so it can be safer to use a decimal values like 100.
|
||||
|
||||
choice
|
||||
prompt "Select a UART for early kernel messages"
|
||||
|
||||
config AT91_EARLY_DBGU0
|
||||
bool "DBGU on rm9200, 9260/9g20, 9261/9g10 and 9rl"
|
||||
depends on HAVE_AT91_DBGU0
|
||||
|
||||
config AT91_EARLY_DBGU1
|
||||
bool "DBGU on 9263 and 9g45"
|
||||
depends on HAVE_AT91_DBGU1
|
||||
|
||||
config AT91_EARLY_USART0
|
||||
bool "USART0"
|
||||
|
||||
config AT91_EARLY_USART1
|
||||
bool "USART1"
|
||||
|
||||
config AT91_EARLY_USART2
|
||||
bool "USART2"
|
||||
depends on ! ARCH_AT91X40
|
||||
|
||||
config AT91_EARLY_USART3
|
||||
bool "USART3"
|
||||
depends on HAVE_AT91_USART3
|
||||
|
||||
config AT91_EARLY_USART4
|
||||
bool "USART4"
|
||||
depends on HAVE_AT91_USART4
|
||||
|
||||
config AT91_EARLY_USART5
|
||||
bool "USART5"
|
||||
depends on HAVE_AT91_USART5
|
||||
|
||||
endchoice
|
||||
|
||||
endmenu
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -10,17 +10,25 @@ obj- :=
|
|||
obj-$(CONFIG_AT91_PMC_UNIT) += clock.o
|
||||
obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
|
||||
obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9) += at91sam926x_time.o sam9_smc.o
|
||||
|
||||
# CPU-specific support
|
||||
obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam926x_time.o sam9_smc.o
|
||||
obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o at91rm9200_time.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9260) += at91sam9260.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9261) += at91sam9261.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9263) += at91sam9263.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9G45) += at91sam9g45.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o
|
||||
|
||||
obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261_devices.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261_devices.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263_devices.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl_devices.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260_devices.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45_devices.o
|
||||
obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
|
||||
|
||||
# AT91RM9200 board-specific support
|
||||
|
|
|
|||
|
|
@ -249,18 +249,6 @@ static void __init at91rm9200_register_clocks(void)
|
|||
clk_register(&pck3);
|
||||
}
|
||||
|
||||
static struct clk_lookup console_clock_lookup;
|
||||
|
||||
void __init at91rm9200_set_console_clock(int id)
|
||||
{
|
||||
if (id >= ARRAY_SIZE(usart_clocks_lookups))
|
||||
return;
|
||||
|
||||
console_clock_lookup.con_id = "usart";
|
||||
console_clock_lookup.clk = usart_clocks_lookups[id].clk;
|
||||
clkdev_add(&console_clock_lookup);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* GPIO
|
||||
* -------------------------------------------------------------------- */
|
||||
|
|
|
|||
|
|
@ -1152,14 +1152,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
|||
at91_uarts[portnr] = pdev;
|
||||
}
|
||||
|
||||
void __init at91_set_serial_console(unsigned portnr)
|
||||
{
|
||||
if (portnr < ATMEL_MAX_UART) {
|
||||
atmel_default_console_device = at91_uarts[portnr];
|
||||
at91rm9200_set_console_clock(at91_uarts[portnr]->id);
|
||||
}
|
||||
}
|
||||
|
||||
void __init at91_add_device_serial(void)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -1168,13 +1160,9 @@ void __init at91_add_device_serial(void)
|
|||
if (at91_uarts[i])
|
||||
platform_device_register(at91_uarts[i]);
|
||||
}
|
||||
|
||||
if (!atmel_default_console_device)
|
||||
printk(KERN_INFO "AT91: No default serial console defined.\n");
|
||||
}
|
||||
#else
|
||||
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
|
||||
void __init at91_set_serial_console(unsigned portnr) {}
|
||||
void __init at91_add_device_serial(void) {}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -268,18 +268,6 @@ static void __init at91sam9260_register_clocks(void)
|
|||
clk_register(&pck1);
|
||||
}
|
||||
|
||||
static struct clk_lookup console_clock_lookup;
|
||||
|
||||
void __init at91sam9260_set_console_clock(int id)
|
||||
{
|
||||
if (id >= ARRAY_SIZE(usart_clocks_lookups))
|
||||
return;
|
||||
|
||||
console_clock_lookup.con_id = "usart";
|
||||
console_clock_lookup.clk = usart_clocks_lookups[id].clk;
|
||||
clkdev_add(&console_clock_lookup);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* GPIO
|
||||
* -------------------------------------------------------------------- */
|
||||
|
|
|
|||
|
|
@ -1229,14 +1229,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
|||
at91_uarts[portnr] = pdev;
|
||||
}
|
||||
|
||||
void __init at91_set_serial_console(unsigned portnr)
|
||||
{
|
||||
if (portnr < ATMEL_MAX_UART) {
|
||||
atmel_default_console_device = at91_uarts[portnr];
|
||||
at91sam9260_set_console_clock(at91_uarts[portnr]->id);
|
||||
}
|
||||
}
|
||||
|
||||
void __init at91_add_device_serial(void)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -1245,13 +1237,9 @@ void __init at91_add_device_serial(void)
|
|||
if (at91_uarts[i])
|
||||
platform_device_register(at91_uarts[i]);
|
||||
}
|
||||
|
||||
if (!atmel_default_console_device)
|
||||
printk(KERN_INFO "AT91: No default serial console defined.\n");
|
||||
}
|
||||
#else
|
||||
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
|
||||
void __init at91_set_serial_console(unsigned portnr) {}
|
||||
void __init at91_add_device_serial(void) {}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -239,18 +239,6 @@ static void __init at91sam9261_register_clocks(void)
|
|||
clk_register(&hck1);
|
||||
}
|
||||
|
||||
static struct clk_lookup console_clock_lookup;
|
||||
|
||||
void __init at91sam9261_set_console_clock(int id)
|
||||
{
|
||||
if (id >= ARRAY_SIZE(usart_clocks_lookups))
|
||||
return;
|
||||
|
||||
console_clock_lookup.con_id = "usart";
|
||||
console_clock_lookup.clk = usart_clocks_lookups[id].clk;
|
||||
clkdev_add(&console_clock_lookup);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* GPIO
|
||||
* -------------------------------------------------------------------- */
|
||||
|
|
|
|||
|
|
@ -1051,14 +1051,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
|||
at91_uarts[portnr] = pdev;
|
||||
}
|
||||
|
||||
void __init at91_set_serial_console(unsigned portnr)
|
||||
{
|
||||
if (portnr < ATMEL_MAX_UART) {
|
||||
atmel_default_console_device = at91_uarts[portnr];
|
||||
at91sam9261_set_console_clock(at91_uarts[portnr]->id);
|
||||
}
|
||||
}
|
||||
|
||||
void __init at91_add_device_serial(void)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -1067,13 +1059,9 @@ void __init at91_add_device_serial(void)
|
|||
if (at91_uarts[i])
|
||||
platform_device_register(at91_uarts[i]);
|
||||
}
|
||||
|
||||
if (!atmel_default_console_device)
|
||||
printk(KERN_INFO "AT91: No default serial console defined.\n");
|
||||
}
|
||||
#else
|
||||
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
|
||||
void __init at91_set_serial_console(unsigned portnr) {}
|
||||
void __init at91_add_device_serial(void) {}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -255,18 +255,6 @@ static void __init at91sam9263_register_clocks(void)
|
|||
clk_register(&pck3);
|
||||
}
|
||||
|
||||
static struct clk_lookup console_clock_lookup;
|
||||
|
||||
void __init at91sam9263_set_console_clock(int id)
|
||||
{
|
||||
if (id >= ARRAY_SIZE(usart_clocks_lookups))
|
||||
return;
|
||||
|
||||
console_clock_lookup.con_id = "usart";
|
||||
console_clock_lookup.clk = usart_clocks_lookups[id].clk;
|
||||
clkdev_add(&console_clock_lookup);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* GPIO
|
||||
* -------------------------------------------------------------------- */
|
||||
|
|
|
|||
|
|
@ -1461,14 +1461,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
|||
at91_uarts[portnr] = pdev;
|
||||
}
|
||||
|
||||
void __init at91_set_serial_console(unsigned portnr)
|
||||
{
|
||||
if (portnr < ATMEL_MAX_UART) {
|
||||
atmel_default_console_device = at91_uarts[portnr];
|
||||
at91sam9263_set_console_clock(at91_uarts[portnr]->id);
|
||||
}
|
||||
}
|
||||
|
||||
void __init at91_add_device_serial(void)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -1477,13 +1469,9 @@ void __init at91_add_device_serial(void)
|
|||
if (at91_uarts[i])
|
||||
platform_device_register(at91_uarts[i]);
|
||||
}
|
||||
|
||||
if (!atmel_default_console_device)
|
||||
printk(KERN_INFO "AT91: No default serial console defined.\n");
|
||||
}
|
||||
#else
|
||||
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
|
||||
void __init at91_set_serial_console(unsigned portnr) {}
|
||||
void __init at91_add_device_serial(void) {}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -288,18 +288,6 @@ static void __init at91sam9g45_register_clocks(void)
|
|||
clk_register(&pck1);
|
||||
}
|
||||
|
||||
static struct clk_lookup console_clock_lookup;
|
||||
|
||||
void __init at91sam9g45_set_console_clock(int id)
|
||||
{
|
||||
if (id >= ARRAY_SIZE(usart_clocks_lookups))
|
||||
return;
|
||||
|
||||
console_clock_lookup.con_id = "usart";
|
||||
console_clock_lookup.clk = usart_clocks_lookups[id].clk;
|
||||
clkdev_add(&console_clock_lookup);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* GPIO
|
||||
* -------------------------------------------------------------------- */
|
||||
|
|
|
|||
|
|
@ -1741,14 +1741,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
|||
at91_uarts[portnr] = pdev;
|
||||
}
|
||||
|
||||
void __init at91_set_serial_console(unsigned portnr)
|
||||
{
|
||||
if (portnr < ATMEL_MAX_UART) {
|
||||
atmel_default_console_device = at91_uarts[portnr];
|
||||
at91sam9g45_set_console_clock(at91_uarts[portnr]->id);
|
||||
}
|
||||
}
|
||||
|
||||
void __init at91_add_device_serial(void)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -1757,13 +1749,9 @@ void __init at91_add_device_serial(void)
|
|||
if (at91_uarts[i])
|
||||
platform_device_register(at91_uarts[i]);
|
||||
}
|
||||
|
||||
if (!atmel_default_console_device)
|
||||
printk(KERN_INFO "AT91: No default serial console defined.\n");
|
||||
}
|
||||
#else
|
||||
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
|
||||
void __init at91_set_serial_console(unsigned portnr) {}
|
||||
void __init at91_add_device_serial(void) {}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -232,18 +232,6 @@ static void __init at91sam9rl_register_clocks(void)
|
|||
clk_register(&pck1);
|
||||
}
|
||||
|
||||
static struct clk_lookup console_clock_lookup;
|
||||
|
||||
void __init at91sam9rl_set_console_clock(int id)
|
||||
{
|
||||
if (id >= ARRAY_SIZE(usart_clocks_lookups))
|
||||
return;
|
||||
|
||||
console_clock_lookup.con_id = "usart";
|
||||
console_clock_lookup.clk = usart_clocks_lookups[id].clk;
|
||||
clkdev_add(&console_clock_lookup);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* GPIO
|
||||
* -------------------------------------------------------------------- */
|
||||
|
|
|
|||
|
|
@ -1192,14 +1192,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
|||
at91_uarts[portnr] = pdev;
|
||||
}
|
||||
|
||||
void __init at91_set_serial_console(unsigned portnr)
|
||||
{
|
||||
if (portnr < ATMEL_MAX_UART) {
|
||||
atmel_default_console_device = at91_uarts[portnr];
|
||||
at91sam9rl_set_console_clock(at91_uarts[portnr]->id);
|
||||
}
|
||||
}
|
||||
|
||||
void __init at91_add_device_serial(void)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -1208,13 +1200,9 @@ void __init at91_add_device_serial(void)
|
|||
if (at91_uarts[i])
|
||||
platform_device_register(at91_uarts[i]);
|
||||
}
|
||||
|
||||
if (!atmel_default_console_device)
|
||||
printk(KERN_INFO "AT91: No default serial console defined.\n");
|
||||
}
|
||||
#else
|
||||
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
|
||||
void __init at91_set_serial_console(unsigned portnr) {}
|
||||
void __init at91_add_device_serial(void) {}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -47,20 +47,6 @@ static void __init onearm_init_early(void)
|
|||
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* USART1 on ttyS2 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
static struct macb_platform_data __initdata onearm_eth_data = {
|
||||
|
|
@ -82,6 +68,16 @@ static struct at91_udc_data __initdata onearm_udc_data = {
|
|||
static void __init onearm_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* USART1 on ttyS2 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
at91_add_device_serial();
|
||||
/* Ethernet */
|
||||
at91_add_device_eth(&onearm_eth_data);
|
||||
|
|
|
|||
|
|
@ -52,22 +52,6 @@ static void __init afeb9260_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1,
|
||||
ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR
|
||||
| ATMEL_UART_DCD | ATMEL_UART_RI);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2,
|
||||
ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -183,6 +167,18 @@ static struct at91_cf_data afeb9260_cf_data = {
|
|||
static void __init afeb9260_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1,
|
||||
ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR
|
||||
| ATMEL_UART_DCD | ATMEL_UART_RI);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2,
|
||||
ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
at91_add_device_serial();
|
||||
/* USB Host */
|
||||
at91_add_device_usbh(&afeb9260_usbh_data);
|
||||
|
|
|
|||
|
|
@ -49,12 +49,6 @@ static void __init cam60_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 10 MHz crystal */
|
||||
at91_initialize(10000000);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -175,6 +169,8 @@ static void __init cam60_add_device_nand(void)
|
|||
static void __init cam60_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
at91_add_device_serial();
|
||||
/* SPI */
|
||||
at91_add_device_spi(cam60_spi_devices, ARRAY_SIZE(cam60_spi_devices));
|
||||
|
|
|
|||
|
|
@ -44,17 +44,6 @@ static void __init carmeva_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 20.000 MHz crystal */
|
||||
at91_initialize(20000000);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
static struct macb_platform_data __initdata carmeva_eth_data = {
|
||||
|
|
@ -139,6 +128,13 @@ static struct gpio_led carmeva_leds[] = {
|
|||
static void __init carmeva_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
at91_add_device_serial();
|
||||
/* Ethernet */
|
||||
at91_add_device_eth(&carmeva_eth_data);
|
||||
|
|
|
|||
|
|
@ -52,34 +52,6 @@ static void __init cpu9krea_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* DGBU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS |
|
||||
ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
|
||||
ATMEL_UART_DCD | ATMEL_UART_RI);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS |
|
||||
ATMEL_UART_RTS);
|
||||
|
||||
/* USART2 on ttyS3. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS |
|
||||
ATMEL_UART_RTS);
|
||||
|
||||
/* USART3 on ttyS4. (Rx, Tx) */
|
||||
at91_register_uart(AT91SAM9260_ID_US3, 4, 0);
|
||||
|
||||
/* USART4 on ttyS5. (Rx, Tx) */
|
||||
at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
|
||||
|
||||
/* USART5 on ttyS6. (Rx, Tx) */
|
||||
at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -352,6 +324,30 @@ static void __init cpu9krea_board_init(void)
|
|||
/* NOR */
|
||||
cpu9krea_add_device_nor();
|
||||
/* Serial */
|
||||
/* DGBU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS |
|
||||
ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
|
||||
ATMEL_UART_DCD | ATMEL_UART_RI);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS |
|
||||
ATMEL_UART_RTS);
|
||||
|
||||
/* USART2 on ttyS3. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS |
|
||||
ATMEL_UART_RTS);
|
||||
|
||||
/* USART3 on ttyS4. (Rx, Tx) */
|
||||
at91_register_uart(AT91SAM9260_ID_US3, 4, 0);
|
||||
|
||||
/* USART4 on ttyS5. (Rx, Tx) */
|
||||
at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
|
||||
|
||||
/* USART5 on ttyS6. (Rx, Tx) */
|
||||
at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
|
||||
at91_add_device_serial();
|
||||
/* USB Host */
|
||||
at91_add_device_usbh(&cpu9krea_usbh_data);
|
||||
|
|
|
|||
|
|
@ -59,28 +59,6 @@ static void __init cpuat91_init_early(void)
|
|||
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS |
|
||||
ATMEL_UART_RTS);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS |
|
||||
ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
|
||||
ATMEL_UART_DCD | ATMEL_UART_RI);
|
||||
|
||||
/* USART2 on ttyS3 (Rx, Tx) */
|
||||
at91_register_uart(AT91RM9200_ID_US2, 3, 0);
|
||||
|
||||
/* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS |
|
||||
ATMEL_UART_RTS);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
static struct macb_platform_data __initdata cpuat91_eth_data = {
|
||||
|
|
@ -161,6 +139,24 @@ static struct platform_device *platform_devices[] __initdata = {
|
|||
static void __init cpuat91_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS |
|
||||
ATMEL_UART_RTS);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS |
|
||||
ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
|
||||
ATMEL_UART_DCD | ATMEL_UART_RI);
|
||||
|
||||
/* USART2 on ttyS3 (Rx, Tx) */
|
||||
at91_register_uart(AT91RM9200_ID_US2, 3, 0);
|
||||
|
||||
/* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS |
|
||||
ATMEL_UART_RTS);
|
||||
at91_add_device_serial();
|
||||
/* LEDs. */
|
||||
at91_gpio_leds(cpuat91_leds, ARRAY_SIZE(cpuat91_leds));
|
||||
|
|
|
|||
|
|
@ -47,15 +47,6 @@ static void __init csb337_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 3.6864 MHz crystal */
|
||||
at91_initialize(3686400);
|
||||
|
||||
/* Setup the LEDs */
|
||||
at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
|
||||
|
||||
/* DBGU on ttyS0 */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* make console=ttyS0 the default */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
static struct macb_platform_data __initdata csb337_eth_data = {
|
||||
|
|
@ -228,7 +219,11 @@ static struct gpio_led csb_leds[] = {
|
|||
|
||||
static void __init csb337_board_init(void)
|
||||
{
|
||||
/* Setup the LEDs */
|
||||
at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0 */
|
||||
at91_register_uart(0, 0, 0);
|
||||
at91_add_device_serial();
|
||||
/* Ethernet */
|
||||
at91_add_device_eth(&csb337_eth_data);
|
||||
|
|
|
|||
|
|
@ -44,12 +44,6 @@ static void __init csb637_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 3.6864 MHz crystal */
|
||||
at91_initialize(3686400);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* make console=ttyS0 (ie, DBGU) the default */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
static struct macb_platform_data __initdata csb637_eth_data = {
|
||||
|
|
@ -118,6 +112,8 @@ static void __init csb637_board_init(void)
|
|||
/* LED(s) */
|
||||
at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds));
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
at91_add_device_serial();
|
||||
/* Ethernet */
|
||||
at91_add_device_eth(&csb637_eth_data);
|
||||
|
|
|
|||
|
|
@ -1,10 +1,6 @@
|
|||
/*
|
||||
* Setup code for AT91SAM Evaluation Kits with Device Tree support
|
||||
*
|
||||
* Covers: * AT91SAM9G45-EKES board
|
||||
* * AT91SAM9M10-EKES board
|
||||
* * AT91SAM9M10G45-EK board
|
||||
*
|
||||
* Copyright (C) 2011 Atmel,
|
||||
* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
|
|
@ -49,9 +45,7 @@ static void __init at91_dt_device_init(void)
|
|||
}
|
||||
|
||||
static const char *at91_dt_board_compat[] __initdata = {
|
||||
"atmel,at91sam9m10g45ek",
|
||||
"atmel,at91sam9x5ek",
|
||||
"calao,usb-a9g20",
|
||||
"atmel,at91sam9",
|
||||
NULL
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -44,20 +44,6 @@ static void __init eb9200_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* USART2 on ttyS2. (Rx, Tx) - IRDA */
|
||||
at91_register_uart(AT91RM9200_ID_US2, 2, 0);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
static struct macb_platform_data __initdata eb9200_eth_data = {
|
||||
|
|
@ -101,6 +87,16 @@ static struct i2c_board_info __initdata eb9200_i2c_devices[] = {
|
|||
static void __init eb9200_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* USART2 on ttyS2. (Rx, Tx) - IRDA */
|
||||
at91_register_uart(AT91RM9200_ID_US2, 2, 0);
|
||||
at91_add_device_serial();
|
||||
/* Ethernet */
|
||||
at91_add_device_eth(&eb9200_eth_data);
|
||||
|
|
|
|||
|
|
@ -50,18 +50,6 @@ static void __init ecb_at91init_early(void)
|
|||
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* Setup the LEDs */
|
||||
at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx & Tx only) */
|
||||
at91_register_uart(AT91RM9200_ID_US0, 1, 0);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
static struct macb_platform_data __initdata ecb_at91eth_data = {
|
||||
|
|
@ -151,7 +139,15 @@ static struct spi_board_info __initdata ecb_at91spi_devices[] = {
|
|||
|
||||
static void __init ecb_at91board_init(void)
|
||||
{
|
||||
/* Setup the LEDs */
|
||||
at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7);
|
||||
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx & Tx only) */
|
||||
at91_register_uart(AT91RM9200_ID_US0, 1, 0);
|
||||
at91_add_device_serial();
|
||||
|
||||
/* Ethernet */
|
||||
|
|
|
|||
|
|
@ -37,15 +37,6 @@ static void __init eco920_init_early(void)
|
|||
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
|
||||
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* Setup the LEDs */
|
||||
at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
static struct macb_platform_data __initdata eco920_eth_data = {
|
||||
|
|
@ -103,6 +94,10 @@ static struct spi_board_info eco920_spi_devices[] = {
|
|||
|
||||
static void __init eco920_board_init(void)
|
||||
{
|
||||
/* Setup the LEDs */
|
||||
at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
|
||||
/* DBGU on ttyS0. (Rx & Tx only */
|
||||
at91_register_uart(0, 0, 0);
|
||||
at91_add_device_serial();
|
||||
at91_add_device_eth(&eco920_eth_data);
|
||||
at91_add_device_usbh(&eco920_usbh_data);
|
||||
|
|
|
|||
|
|
@ -41,12 +41,6 @@ static void __init flexibity_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
/* USB Host port */
|
||||
|
|
@ -143,6 +137,8 @@ static struct gpio_led flexibity_leds[] = {
|
|||
static void __init flexibity_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
at91_add_device_serial();
|
||||
/* USB Host */
|
||||
at91_add_device_usbh(&flexibity_usbh_data);
|
||||
|
|
|
|||
|
|
@ -61,44 +61,6 @@ static void __init foxg20_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1,
|
||||
ATMEL_UART_CTS
|
||||
| ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR
|
||||
| ATMEL_UART_DSR
|
||||
| ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2,
|
||||
ATMEL_UART_CTS
|
||||
| ATMEL_UART_RTS);
|
||||
|
||||
/* USART2 on ttyS3. (Rx & Tx only) */
|
||||
at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
|
||||
|
||||
/* USART3 on ttyS4. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US3, 4,
|
||||
ATMEL_UART_CTS
|
||||
| ATMEL_UART_RTS);
|
||||
|
||||
/* USART4 on ttyS5. (Rx & Tx only) */
|
||||
at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
|
||||
|
||||
/* USART5 on ttyS6. (Rx & Tx only) */
|
||||
at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
|
||||
/* Set the internal pull-up resistor on DRXD */
|
||||
at91_set_A_periph(AT91_PIN_PB14, 1);
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -241,6 +203,39 @@ static struct i2c_board_info __initdata foxg20_i2c_devices[] = {
|
|||
static void __init foxg20_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1,
|
||||
ATMEL_UART_CTS
|
||||
| ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR
|
||||
| ATMEL_UART_DSR
|
||||
| ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2,
|
||||
ATMEL_UART_CTS
|
||||
| ATMEL_UART_RTS);
|
||||
|
||||
/* USART2 on ttyS3. (Rx & Tx only) */
|
||||
at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
|
||||
|
||||
/* USART3 on ttyS4. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US3, 4,
|
||||
ATMEL_UART_CTS
|
||||
| ATMEL_UART_RTS);
|
||||
|
||||
/* USART4 on ttyS5. (Rx & Tx only) */
|
||||
at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
|
||||
|
||||
/* USART5 on ttyS6. (Rx & Tx only) */
|
||||
at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
|
||||
|
||||
/* Set the internal pull-up resistor on DRXD */
|
||||
at91_set_A_periph(AT91_PIN_PB14, 1);
|
||||
at91_add_device_serial();
|
||||
/* USB Host */
|
||||
at91_add_device_usbh(&foxg20_usbh_data);
|
||||
|
|
|
|||
|
|
@ -41,38 +41,6 @@
|
|||
static void __init gsia18s_init_early(void)
|
||||
{
|
||||
stamp9g20_init_early();
|
||||
|
||||
/*
|
||||
* USART0 on ttyS1 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI).
|
||||
* Used for Internal Analog Modem.
|
||||
*/
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1,
|
||||
ATMEL_UART_CTS | ATMEL_UART_RTS |
|
||||
ATMEL_UART_DTR | ATMEL_UART_DSR |
|
||||
ATMEL_UART_DCD | ATMEL_UART_RI);
|
||||
/*
|
||||
* USART1 on ttyS2 (Rx, Tx, CTS, RTS).
|
||||
* Used for GPS or WiFi or Data stream.
|
||||
*/
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2,
|
||||
ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
/*
|
||||
* USART2 on ttyS3 (Rx, Tx, CTS, RTS).
|
||||
* Used for External Modem.
|
||||
*/
|
||||
at91_register_uart(AT91SAM9260_ID_US2, 3,
|
||||
ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
/*
|
||||
* USART3 on ttyS4 (Rx, Tx, RTS).
|
||||
* Used for RS-485.
|
||||
*/
|
||||
at91_register_uart(AT91SAM9260_ID_US3, 4, ATMEL_UART_RTS);
|
||||
|
||||
/*
|
||||
* USART4 on ttyS5 (Rx, Tx).
|
||||
* Used for TRX433 Radio Module.
|
||||
*/
|
||||
at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -558,6 +526,37 @@ static int __init gsia18s_power_off_init(void)
|
|||
|
||||
static void __init gsia18s_board_init(void)
|
||||
{
|
||||
/*
|
||||
* USART0 on ttyS1 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI).
|
||||
* Used for Internal Analog Modem.
|
||||
*/
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1,
|
||||
ATMEL_UART_CTS | ATMEL_UART_RTS |
|
||||
ATMEL_UART_DTR | ATMEL_UART_DSR |
|
||||
ATMEL_UART_DCD | ATMEL_UART_RI);
|
||||
/*
|
||||
* USART1 on ttyS2 (Rx, Tx, CTS, RTS).
|
||||
* Used for GPS or WiFi or Data stream.
|
||||
*/
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2,
|
||||
ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
/*
|
||||
* USART2 on ttyS3 (Rx, Tx, CTS, RTS).
|
||||
* Used for External Modem.
|
||||
*/
|
||||
at91_register_uart(AT91SAM9260_ID_US2, 3,
|
||||
ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
/*
|
||||
* USART3 on ttyS4 (Rx, Tx, RTS).
|
||||
* Used for RS-485.
|
||||
*/
|
||||
at91_register_uart(AT91SAM9260_ID_US3, 4, ATMEL_UART_RTS);
|
||||
|
||||
/*
|
||||
* USART4 on ttyS5 (Rx, Tx).
|
||||
* Used for TRX433 Radio Module.
|
||||
*/
|
||||
at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
|
||||
stamp9g20_board_init();
|
||||
at91_add_device_usbh(&usbh_data);
|
||||
at91_add_device_udc(&udc_data);
|
||||
|
|
|
|||
|
|
@ -47,18 +47,6 @@ static void __init kafa_init_early(void)
|
|||
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* Set up the LEDs */
|
||||
at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
static struct macb_platform_data __initdata kafa_eth_data = {
|
||||
|
|
@ -79,7 +67,15 @@ static struct at91_udc_data __initdata kafa_udc_data = {
|
|||
|
||||
static void __init kafa_board_init(void)
|
||||
{
|
||||
/* Set up the LEDs */
|
||||
at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4);
|
||||
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
at91_add_device_serial();
|
||||
/* Ethernet */
|
||||
at91_add_device_eth(&kafa_eth_data);
|
||||
|
|
|
|||
|
|
@ -50,24 +50,6 @@ static void __init kb9202_init_early(void)
|
|||
|
||||
/* Initialize processor: 10 MHz crystal */
|
||||
at91_initialize(10000000);
|
||||
|
||||
/* Set up the LEDs */
|
||||
at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1 (Rx & Tx only) */
|
||||
at91_register_uart(AT91RM9200_ID_US0, 1, 0);
|
||||
|
||||
/* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 2, 0);
|
||||
|
||||
/* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */
|
||||
at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
static struct macb_platform_data __initdata kb9202_eth_data = {
|
||||
|
|
@ -115,7 +97,21 @@ static struct atmel_nand_data __initdata kb9202_nand_data = {
|
|||
|
||||
static void __init kb9202_board_init(void)
|
||||
{
|
||||
/* Set up the LEDs */
|
||||
at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18);
|
||||
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1 (Rx & Tx only) */
|
||||
at91_register_uart(AT91RM9200_ID_US0, 1, 0);
|
||||
|
||||
/* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 2, 0);
|
||||
|
||||
/* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */
|
||||
at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
at91_add_device_serial();
|
||||
/* Ethernet */
|
||||
at91_add_device_eth(&kb9202_eth_data);
|
||||
|
|
|
|||
|
|
@ -55,15 +55,6 @@ static void __init neocore926_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 20 MHz crystal */
|
||||
at91_initialize(20000000);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -341,6 +332,11 @@ static struct ac97c_platform_data neocore926_ac97_data = {
|
|||
static void __init neocore926_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
at91_add_device_serial();
|
||||
|
||||
/* USB Host */
|
||||
|
|
|
|||
|
|
@ -40,17 +40,6 @@
|
|||
static void __init pcontrol_g20_init_early(void)
|
||||
{
|
||||
stamp9g20_init_early();
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback A2 */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS
|
||||
| ATMEL_UART_RTS);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, CTS, RTS) isolated RS485 X5 */
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS
|
||||
| ATMEL_UART_RTS);
|
||||
|
||||
/* USART2 on ttyS3. (Rx, Tx) 9bit-Bus Multidrop-mode X4 */
|
||||
at91_register_uart(AT91SAM9260_ID_US4, 3, 0);
|
||||
}
|
||||
|
||||
static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
|
||||
|
|
@ -199,6 +188,16 @@ static struct spi_board_info pcontrol_g20_spi_devices[] = {
|
|||
|
||||
static void __init pcontrol_g20_board_init(void)
|
||||
{
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback A2 */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS
|
||||
| ATMEL_UART_RTS);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, CTS, RTS) isolated RS485 X5 */
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS
|
||||
| ATMEL_UART_RTS);
|
||||
|
||||
/* USART2 on ttyS3. (Rx, Tx) 9bit-Bus Multidrop-mode X4 */
|
||||
at91_register_uart(AT91SAM9260_ID_US4, 3, 0);
|
||||
stamp9g20_board_init();
|
||||
at91_add_device_usbh(&usbh_data);
|
||||
at91_add_device_eth(&macb_data);
|
||||
|
|
|
|||
|
|
@ -48,17 +48,6 @@ static void __init picotux200_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
static struct macb_platform_data __initdata picotux200_eth_data = {
|
||||
|
|
@ -106,6 +95,13 @@ static struct platform_device picotux200_flash = {
|
|||
static void __init picotux200_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
at91_add_device_serial();
|
||||
/* Ethernet */
|
||||
at91_add_device_eth(&picotux200_eth_data);
|
||||
|
|
|
|||
|
|
@ -52,24 +52,6 @@ static void __init ek_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 12.000 MHz crystal */
|
||||
at91_initialize(12000000);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* set serial console to ttyS1 (ie, USART0) */
|
||||
at91_set_serial_console(1);
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -235,6 +217,19 @@ static struct gpio_led ek_leds[] = {
|
|||
static void __init ek_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
at91_add_device_serial();
|
||||
/* USB Host */
|
||||
at91_add_device_usbh(&ek_usbh_data);
|
||||
|
|
|
|||
|
|
@ -50,20 +50,6 @@ static void __init dk_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* Setup the LEDs */
|
||||
at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
static struct macb_platform_data __initdata dk_eth_data = {
|
||||
|
|
@ -190,7 +176,17 @@ static struct gpio_led dk_leds[] = {
|
|||
|
||||
static void __init dk_board_init(void)
|
||||
{
|
||||
/* Setup the LEDs */
|
||||
at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
|
||||
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
at91_add_device_serial();
|
||||
/* Ethernet */
|
||||
at91_add_device_eth(&dk_eth_data);
|
||||
|
|
|
|||
|
|
@ -50,20 +50,6 @@ static void __init ek_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* Setup the LEDs */
|
||||
at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
static struct macb_platform_data __initdata ek_eth_data = {
|
||||
|
|
@ -161,7 +147,17 @@ static struct gpio_led ek_leds[] = {
|
|||
|
||||
static void __init ek_board_init(void)
|
||||
{
|
||||
/* Setup the LEDs */
|
||||
at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2);
|
||||
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
at91_add_device_serial();
|
||||
/* Ethernet */
|
||||
at91_add_device_eth(&ek_eth_data);
|
||||
|
|
|
|||
|
|
@ -35,26 +35,6 @@ static void __init rsi_ews_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* Setup the LEDs */
|
||||
at91_init_leds(AT91_PIN_PB6, AT91_PIN_PB9);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
/* This one is for debugging */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
/* Dialin/-out modem interface */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* USART3 on ttyS4. (Rx, Tx, RTS) */
|
||||
/* RS485 communication */
|
||||
at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_RTS);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -204,7 +184,23 @@ static struct platform_device rsiews_nor_flash = {
|
|||
*/
|
||||
static void __init rsi_ews_board_init(void)
|
||||
{
|
||||
/* Setup the LEDs */
|
||||
at91_init_leds(AT91_PIN_PB6, AT91_PIN_PB9);
|
||||
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
/* This one is for debugging */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
/* Dialin/-out modem interface */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* USART3 on ttyS4. (Rx, Tx, RTS) */
|
||||
/* RS485 communication */
|
||||
at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_RTS);
|
||||
at91_add_device_serial();
|
||||
at91_set_gpio_output(AT91_PIN_PA21, 0);
|
||||
/* Ethernet */
|
||||
|
|
|
|||
|
|
@ -48,23 +48,6 @@ static void __init ek_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* Setup the LEDs */
|
||||
at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -184,7 +167,20 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
|
|||
|
||||
static void __init ek_board_init(void)
|
||||
{
|
||||
/* Setup the LEDs */
|
||||
at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6);
|
||||
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
at91_add_device_serial();
|
||||
/* USB Host */
|
||||
at91_add_device_usbh(&ek_usbh_data);
|
||||
|
|
|
|||
|
|
@ -54,20 +54,6 @@ static void __init ek_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -320,6 +306,16 @@ static void __init ek_add_device_buttons(void) {}
|
|||
static void __init ek_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
at91_add_device_serial();
|
||||
/* USB Host */
|
||||
at91_add_device_usbh(&ek_usbh_data);
|
||||
|
|
|
|||
|
|
@ -58,15 +58,6 @@ static void __init ek_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* Setup the LEDs */
|
||||
at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -577,7 +568,12 @@ static struct gpio_led ek_leds[] = {
|
|||
|
||||
static void __init ek_board_init(void)
|
||||
{
|
||||
/* Setup the LEDs */
|
||||
at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14);
|
||||
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
at91_add_device_serial();
|
||||
/* USB Host */
|
||||
at91_add_device_usbh(&ek_usbh_data);
|
||||
|
|
|
|||
|
|
@ -57,15 +57,6 @@ static void __init ek_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 16.367 MHz crystal */
|
||||
at91_initialize(16367660);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -412,6 +403,11 @@ static struct at91_can_data ek_can_data = {
|
|||
static void __init ek_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
at91_add_device_serial();
|
||||
/* USB Host */
|
||||
at91_add_device_usbh(&ek_usbh_data);
|
||||
|
|
|
|||
|
|
@ -65,20 +65,6 @@ static void __init ek_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -372,6 +358,16 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = {
|
|||
static void __init ek_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
at91_add_device_serial();
|
||||
/* USB Host */
|
||||
at91_add_device_usbh(&ek_usbh_data);
|
||||
|
|
|
|||
|
|
@ -53,16 +53,6 @@ static void __init ek_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 12.000 MHz crystal */
|
||||
at91_initialize(12000000);
|
||||
|
||||
/* DGBU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 not connected on the -EK board */
|
||||
/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -457,6 +447,12 @@ static struct platform_device *devices[] __initdata = {
|
|||
static void __init ek_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
/* DGBU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 not connected on the -EK board */
|
||||
/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
|
||||
at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
at91_add_device_serial();
|
||||
/* USB HS Host */
|
||||
at91_add_device_usbh_ohci(&ek_usbh_hs_data);
|
||||
|
|
|
|||
|
|
@ -42,15 +42,6 @@ static void __init ek_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 12.000 MHz crystal */
|
||||
at91_initialize(12000000);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -296,6 +287,11 @@ static void __init ek_add_device_buttons(void) {}
|
|||
static void __init ek_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
at91_add_device_serial();
|
||||
/* USB HS */
|
||||
at91_add_device_usba(&ek_usba_udc_data);
|
||||
|
|
|
|||
|
|
@ -43,16 +43,6 @@
|
|||
static void __init snapper9260_init_early(void)
|
||||
{
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* Debug on ttyS0 */
|
||||
at91_register_uart(0, 0, 0);
|
||||
at91_set_serial_console(0);
|
||||
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1,
|
||||
ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2,
|
||||
ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
|
||||
}
|
||||
|
||||
static struct at91_usbh_data __initdata snapper9260_usbh_data = {
|
||||
|
|
@ -168,6 +158,14 @@ static void __init snapper9260_board_init(void)
|
|||
snapper9260_i2c_isl1208.irq = gpio_to_irq(AT91_PIN_PA31);
|
||||
i2c_register_board_info(0, &snapper9260_i2c_isl1208, 1);
|
||||
|
||||
/* Debug on ttyS0 */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1,
|
||||
ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2,
|
||||
ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
|
||||
at91_add_device_serial();
|
||||
at91_add_device_usbh(&snapper9260_usbh_data);
|
||||
at91_add_device_udc(&snapper9260_udc_data);
|
||||
|
|
|
|||
|
|
@ -36,44 +36,6 @@ void __init stamp9g20_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* DGBU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
static void __init stamp9g20evb_init_early(void)
|
||||
{
|
||||
stamp9g20_init_early();
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR
|
||||
| ATMEL_UART_DCD | ATMEL_UART_RI);
|
||||
}
|
||||
|
||||
static void __init portuxg20_init_early(void)
|
||||
{
|
||||
stamp9g20_init_early();
|
||||
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR
|
||||
| ATMEL_UART_DCD | ATMEL_UART_RI);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* USART4 on ttyS5. (Rx, Tx only) */
|
||||
at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
|
||||
|
||||
/* USART5 on ttyS6. (Rx, Tx only) */
|
||||
at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -254,6 +216,8 @@ void add_w1(void)
|
|||
void __init stamp9g20_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
/* DGBU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
at91_add_device_serial();
|
||||
/* NAND */
|
||||
add_device_nand();
|
||||
|
|
@ -269,6 +233,22 @@ void __init stamp9g20_board_init(void)
|
|||
|
||||
static void __init portuxg20_board_init(void)
|
||||
{
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR
|
||||
| ATMEL_UART_DCD | ATMEL_UART_RI);
|
||||
|
||||
/* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */
|
||||
at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
|
||||
|
||||
/* USART4 on ttyS5. (Rx, Tx only) */
|
||||
at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
|
||||
|
||||
/* USART5 on ttyS6. (Rx, Tx only) */
|
||||
at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
|
||||
stamp9g20_board_init();
|
||||
/* USB Host */
|
||||
at91_add_device_usbh(&usbh_data);
|
||||
|
|
@ -286,6 +266,10 @@ static void __init portuxg20_board_init(void)
|
|||
|
||||
static void __init stamp9g20evb_board_init(void)
|
||||
{
|
||||
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR
|
||||
| ATMEL_UART_DCD | ATMEL_UART_RI);
|
||||
stamp9g20_board_init();
|
||||
/* USB Host */
|
||||
at91_add_device_usbh(&usbh_data);
|
||||
|
|
@ -303,7 +287,7 @@ MACHINE_START(PORTUXG20, "taskit PortuxG20")
|
|||
/* Maintainer: taskit GmbH */
|
||||
.timer = &at91sam926x_timer,
|
||||
.map_io = at91_map_io,
|
||||
.init_early = portuxg20_init_early,
|
||||
.init_early = stamp9g20_init_early,
|
||||
.init_irq = at91_init_irq_default,
|
||||
.init_machine = portuxg20_board_init,
|
||||
MACHINE_END
|
||||
|
|
@ -312,7 +296,7 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20")
|
|||
/* Maintainer: taskit GmbH */
|
||||
.timer = &at91sam926x_timer,
|
||||
.map_io = at91_map_io,
|
||||
.init_early = stamp9g20evb_init_early,
|
||||
.init_early = stamp9g20_init_early,
|
||||
.init_irq = at91_init_irq_default,
|
||||
.init_machine = stamp9g20evb_board_init,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -53,12 +53,6 @@ static void __init ek_init_early(void)
|
|||
{
|
||||
/* Initialize processor: 12.00 MHz crystal */
|
||||
at91_initialize(12000000);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -325,6 +319,8 @@ static void __init ek_add_device_leds(void)
|
|||
static void __init ek_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
at91_add_device_serial();
|
||||
/* USB Host */
|
||||
at91_add_device_usbh(&ek_usbh_data);
|
||||
|
|
|
|||
|
|
@ -58,26 +58,6 @@ static void __init yl9200_init_early(void)
|
|||
|
||||
/* Initialize processor: 18.432 MHz crystal */
|
||||
at91_initialize(18432000);
|
||||
|
||||
/* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
|
||||
at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* USART0 on ttyS2. (Rx & Tx only to JP3) */
|
||||
at91_register_uart(AT91RM9200_ID_US0, 2, 0);
|
||||
|
||||
/* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
|
||||
at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -560,7 +540,23 @@ void __init yl9200_add_device_video(void) {}
|
|||
|
||||
static void __init yl9200_board_init(void)
|
||||
{
|
||||
/* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
|
||||
at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
|
||||
|
||||
/* Serial */
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
||||
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
||||
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
||||
| ATMEL_UART_RI);
|
||||
|
||||
/* USART0 on ttyS2. (Rx & Tx only to JP3) */
|
||||
at91_register_uart(AT91RM9200_ID_US0, 2, 0);
|
||||
|
||||
/* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
|
||||
at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
|
||||
at91_add_device_serial();
|
||||
/* Ethernet */
|
||||
at91_add_device_eth(&yl9200_eth_data);
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#include <linux/export.h>
|
||||
#include <asm/proc-fns.h>
|
||||
#include <asm/cpuidle.h>
|
||||
#include <mach/cpu.h>
|
||||
|
||||
#include "pm.h"
|
||||
|
||||
|
|
@ -33,7 +34,12 @@ static int at91_enter_idle(struct cpuidle_device *dev,
|
|||
struct cpuidle_driver *drv,
|
||||
int index)
|
||||
{
|
||||
at91_standby();
|
||||
if (cpu_is_at91rm9200())
|
||||
at91rm9200_standby();
|
||||
else if (cpu_is_at91sam9g45())
|
||||
at91sam9g45_standby();
|
||||
else
|
||||
at91sam9_standby();
|
||||
|
||||
return index;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -40,17 +40,6 @@ extern struct sys_timer at91sam926x_timer;
|
|||
extern struct sys_timer at91x40_timer;
|
||||
|
||||
/* Clocks */
|
||||
/*
|
||||
* function to specify the clock of the default console. As we do not
|
||||
* use the device/driver bus, the dev_name is not intialize. So we need
|
||||
* to link the clock to a specific con_id only "usart"
|
||||
*/
|
||||
extern void __init at91rm9200_set_console_clock(int id);
|
||||
extern void __init at91sam9260_set_console_clock(int id);
|
||||
extern void __init at91sam9261_set_console_clock(int id);
|
||||
extern void __init at91sam9263_set_console_clock(int id);
|
||||
extern void __init at91sam9rl_set_console_clock(int id);
|
||||
extern void __init at91sam9g45_set_console_clock(int id);
|
||||
#ifdef CONFIG_AT91_PMC_UNIT
|
||||
extern int __init at91_clock_init(unsigned long main_clock);
|
||||
extern int __init at91_dt_clock_init(void);
|
||||
|
|
|
|||
|
|
@ -88,11 +88,6 @@
|
|||
#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
|
||||
#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */
|
||||
|
||||
#define AT91_USART0 AT91RM9200_BASE_US0
|
||||
#define AT91_USART1 AT91RM9200_BASE_US1
|
||||
#define AT91_USART2 AT91RM9200_BASE_US2
|
||||
#define AT91_USART3 AT91RM9200_BASE_US3
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -95,13 +95,6 @@
|
|||
#define AT91SAM9260_BASE_WDT 0xfffffd40
|
||||
#define AT91SAM9260_BASE_GPBR 0xfffffd50
|
||||
|
||||
#define AT91_USART0 AT91SAM9260_BASE_US0
|
||||
#define AT91_USART1 AT91SAM9260_BASE_US1
|
||||
#define AT91_USART2 AT91SAM9260_BASE_US2
|
||||
#define AT91_USART3 AT91SAM9260_BASE_US3
|
||||
#define AT91_USART4 AT91SAM9260_BASE_US4
|
||||
#define AT91_USART5 AT91SAM9260_BASE_US5
|
||||
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
|
|
|
|||
|
|
@ -79,10 +79,6 @@
|
|||
#define AT91SAM9261_BASE_WDT 0xfffffd40
|
||||
#define AT91SAM9261_BASE_GPBR 0xfffffd50
|
||||
|
||||
#define AT91_USART0 AT91SAM9261_BASE_US0
|
||||
#define AT91_USART1 AT91SAM9261_BASE_US1
|
||||
#define AT91_USART2 AT91SAM9261_BASE_US2
|
||||
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
|
|
|
|||
|
|
@ -95,10 +95,6 @@
|
|||
#define AT91SAM9263_BASE_RTT1 0xfffffd50
|
||||
#define AT91SAM9263_BASE_GPBR 0xfffffd60
|
||||
|
||||
#define AT91_USART0 AT91SAM9263_BASE_US0
|
||||
#define AT91_USART1 AT91SAM9263_BASE_US1
|
||||
#define AT91_USART2 AT91SAM9263_BASE_US2
|
||||
|
||||
#define AT91_SMC AT91_SMC0
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -106,11 +106,6 @@
|
|||
#define AT91SAM9G45_BASE_RTC 0xfffffdb0
|
||||
#define AT91SAM9G45_BASE_GPBR 0xfffffd60
|
||||
|
||||
#define AT91_USART0 AT91SAM9G45_BASE_US0
|
||||
#define AT91_USART1 AT91SAM9G45_BASE_US1
|
||||
#define AT91_USART2 AT91SAM9G45_BASE_US2
|
||||
#define AT91_USART3 AT91SAM9G45_BASE_US3
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -89,11 +89,6 @@
|
|||
#define AT91SAM9RL_BASE_GPBR 0xfffffd60
|
||||
#define AT91SAM9RL_BASE_RTC 0xfffffe00
|
||||
|
||||
#define AT91_USART0 AT91SAM9RL_BASE_US0
|
||||
#define AT91_USART1 AT91SAM9RL_BASE_US1
|
||||
#define AT91_USART2 AT91SAM9RL_BASE_US2
|
||||
#define AT91_USART3 AT91SAM9RL_BASE_US3
|
||||
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
|
|
|
|||
|
|
@ -54,14 +54,6 @@
|
|||
#define AT91SAM9X5_BASE_USART1 0xf8020000
|
||||
#define AT91SAM9X5_BASE_USART2 0xf8024000
|
||||
|
||||
/*
|
||||
* Base addresses for early serial code (uncompress.h)
|
||||
*/
|
||||
#define AT91_DBGU AT91_BASE_DBGU0
|
||||
#define AT91_USART0 AT91SAM9X5_BASE_USART0
|
||||
#define AT91_USART1 AT91SAM9X5_BASE_USART1
|
||||
#define AT91_USART2 AT91SAM9X5_BASE_USART2
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -121,7 +121,6 @@ extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_de
|
|||
#define ATMEL_UART_RI 0x20
|
||||
|
||||
extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins);
|
||||
extern void __init at91_set_serial_console(unsigned portnr);
|
||||
|
||||
extern struct platform_device *atmel_default_console_device;
|
||||
|
||||
|
|
|
|||
|
|
@ -54,6 +54,7 @@
|
|||
#define ARCH_REVISON_9200_BGA (0 << 0)
|
||||
#define ARCH_REVISON_9200_PQFP (1 << 0)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
enum at91_soc_type {
|
||||
/* 920T */
|
||||
AT91_SOC_RM9200,
|
||||
|
|
@ -106,7 +107,7 @@ static inline int at91_soc_is_detected(void)
|
|||
return at91_soc_initdata.type != AT91_SOC_NONE;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91RM9200
|
||||
#ifdef CONFIG_SOC_AT91RM9200
|
||||
#define cpu_is_at91rm9200() (at91_soc_initdata.type == AT91_SOC_RM9200)
|
||||
#define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA)
|
||||
#define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP)
|
||||
|
|
@ -116,45 +117,37 @@ static inline int at91_soc_is_detected(void)
|
|||
#define cpu_is_at91rm9200_pqfp() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91SAM9260
|
||||
#ifdef CONFIG_SOC_AT91SAM9260
|
||||
#define cpu_is_at91sam9xe() (at91_soc_initdata.subtype == AT91_SOC_SAM9XE)
|
||||
#define cpu_is_at91sam9260() (at91_soc_initdata.type == AT91_SOC_SAM9260)
|
||||
#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20)
|
||||
#else
|
||||
#define cpu_is_at91sam9xe() (0)
|
||||
#define cpu_is_at91sam9260() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91SAM9G20
|
||||
#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20)
|
||||
#else
|
||||
#define cpu_is_at91sam9g20() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91SAM9261
|
||||
#ifdef CONFIG_SOC_AT91SAM9261
|
||||
#define cpu_is_at91sam9261() (at91_soc_initdata.type == AT91_SOC_SAM9261)
|
||||
#else
|
||||
#define cpu_is_at91sam9261() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91SAM9G10
|
||||
#define cpu_is_at91sam9g10() (at91_soc_initdata.type == AT91_SOC_SAM9G10)
|
||||
#else
|
||||
#define cpu_is_at91sam9261() (0)
|
||||
#define cpu_is_at91sam9g10() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91SAM9263
|
||||
#ifdef CONFIG_SOC_AT91SAM9263
|
||||
#define cpu_is_at91sam9263() (at91_soc_initdata.type == AT91_SOC_SAM9263)
|
||||
#else
|
||||
#define cpu_is_at91sam9263() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91SAM9RL
|
||||
#ifdef CONFIG_SOC_AT91SAM9RL
|
||||
#define cpu_is_at91sam9rl() (at91_soc_initdata.type == AT91_SOC_SAM9RL)
|
||||
#else
|
||||
#define cpu_is_at91sam9rl() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91SAM9G45
|
||||
#ifdef CONFIG_SOC_AT91SAM9G45
|
||||
#define cpu_is_at91sam9g45() (at91_soc_initdata.type == AT91_SOC_SAM9G45)
|
||||
#define cpu_is_at91sam9g45es() (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES)
|
||||
#define cpu_is_at91sam9m10() (at91_soc_initdata.subtype == AT91_SOC_SAM9M10)
|
||||
|
|
@ -168,7 +161,7 @@ static inline int at91_soc_is_detected(void)
|
|||
#define cpu_is_at91sam9m11() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91SAM9X5
|
||||
#ifdef CONFIG_SOC_AT91SAM9X5
|
||||
#define cpu_is_at91sam9x5() (at91_soc_initdata.type == AT91_SOC_SAM9X5)
|
||||
#define cpu_is_at91sam9g15() (at91_soc_initdata.subtype == AT91_SOC_SAM9G15)
|
||||
#define cpu_is_at91sam9g35() (at91_soc_initdata.subtype == AT91_SOC_SAM9G35)
|
||||
|
|
@ -189,5 +182,6 @@ static inline int at91_soc_is_detected(void)
|
|||
* definitions may reduce clutter in common drivers.
|
||||
*/
|
||||
#define cpu_is_at32ap7000() (0)
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __MACH_CPU_H__ */
|
||||
|
|
|
|||
|
|
@ -22,27 +22,17 @@
|
|||
/* 9263, 9g45 */
|
||||
#define AT91_BASE_DBGU1 0xffffee00
|
||||
|
||||
#if defined(CONFIG_ARCH_AT91RM9200)
|
||||
#include <mach/at91rm9200.h>
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
|
||||
#include <mach/at91sam9260.h>
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10)
|
||||
#include <mach/at91sam9261.h>
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9263)
|
||||
#include <mach/at91sam9263.h>
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9RL)
|
||||
#include <mach/at91sam9rl.h>
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
||||
#include <mach/at91sam9g45.h>
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9X5)
|
||||
#include <mach/at91sam9x5.h>
|
||||
#elif defined(CONFIG_ARCH_AT91X40)
|
||||
#if defined(CONFIG_ARCH_AT91X40)
|
||||
#include <mach/at91x40.h>
|
||||
#else
|
||||
#error "Unsupported AT91 processor"
|
||||
#endif
|
||||
#include <mach/at91rm9200.h>
|
||||
#include <mach/at91sam9260.h>
|
||||
#include <mach/at91sam9261.h>
|
||||
#include <mach/at91sam9263.h>
|
||||
#include <mach/at91sam9rl.h>
|
||||
#include <mach/at91sam9g45.h>
|
||||
#include <mach/at91sam9x5.h>
|
||||
|
||||
#if !defined(CONFIG_ARCH_AT91X40)
|
||||
/*
|
||||
* On all at91 except rm9200 and x40 have the System Controller starts
|
||||
* at address 0xffffc000 and has a size of 16KiB.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,8 @@
|
|||
/*
|
||||
* arch/arm/mach-at91/include/mach/uncompress.h
|
||||
*
|
||||
* Copyright (C) 2003 SAN People
|
||||
* Copyright (C) 2003 SAN People
|
||||
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -25,22 +26,147 @@
|
|||
#include <linux/atmel_serial.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#if defined(CONFIG_AT91_EARLY_DBGU0)
|
||||
#define UART_OFFSET AT91_BASE_DBGU0
|
||||
#elif defined(CONFIG_AT91_EARLY_DBGU1)
|
||||
#define UART_OFFSET AT91_BASE_DBGU1
|
||||
#elif defined(CONFIG_AT91_EARLY_USART0)
|
||||
#define UART_OFFSET AT91_USART0
|
||||
#elif defined(CONFIG_AT91_EARLY_USART1)
|
||||
#define UART_OFFSET AT91_USART1
|
||||
#elif defined(CONFIG_AT91_EARLY_USART2)
|
||||
#define UART_OFFSET AT91_USART2
|
||||
#elif defined(CONFIG_AT91_EARLY_USART3)
|
||||
#define UART_OFFSET AT91_USART3
|
||||
#elif defined(CONFIG_AT91_EARLY_USART4)
|
||||
#define UART_OFFSET AT91_USART4
|
||||
#elif defined(CONFIG_AT91_EARLY_USART5)
|
||||
#define UART_OFFSET AT91_USART5
|
||||
#include <mach/at91_dbgu.h>
|
||||
#include <mach/cpu.h>
|
||||
|
||||
void __iomem *at91_uart;
|
||||
|
||||
#if !defined(CONFIG_ARCH_AT91X40)
|
||||
static const u32 uarts_rm9200[] = {
|
||||
AT91_BASE_DBGU0,
|
||||
AT91RM9200_BASE_US0,
|
||||
AT91RM9200_BASE_US1,
|
||||
AT91RM9200_BASE_US2,
|
||||
AT91RM9200_BASE_US3,
|
||||
0,
|
||||
};
|
||||
|
||||
static const u32 uarts_sam9260[] = {
|
||||
AT91_BASE_DBGU0,
|
||||
AT91SAM9260_BASE_US0,
|
||||
AT91SAM9260_BASE_US1,
|
||||
AT91SAM9260_BASE_US2,
|
||||
AT91SAM9260_BASE_US3,
|
||||
AT91SAM9260_BASE_US4,
|
||||
AT91SAM9260_BASE_US5,
|
||||
0,
|
||||
};
|
||||
|
||||
static const u32 uarts_sam9261[] = {
|
||||
AT91_BASE_DBGU0,
|
||||
AT91SAM9261_BASE_US0,
|
||||
AT91SAM9261_BASE_US1,
|
||||
AT91SAM9261_BASE_US2,
|
||||
0,
|
||||
};
|
||||
|
||||
static const u32 uarts_sam9263[] = {
|
||||
AT91_BASE_DBGU1,
|
||||
AT91SAM9263_BASE_US0,
|
||||
AT91SAM9263_BASE_US1,
|
||||
AT91SAM9263_BASE_US2,
|
||||
0,
|
||||
};
|
||||
|
||||
static const u32 uarts_sam9g45[] = {
|
||||
AT91_BASE_DBGU1,
|
||||
AT91SAM9G45_BASE_US0,
|
||||
AT91SAM9G45_BASE_US1,
|
||||
AT91SAM9G45_BASE_US2,
|
||||
AT91SAM9G45_BASE_US3,
|
||||
0,
|
||||
};
|
||||
|
||||
static const u32 uarts_sam9rl[] = {
|
||||
AT91_BASE_DBGU0,
|
||||
AT91SAM9RL_BASE_US0,
|
||||
AT91SAM9RL_BASE_US1,
|
||||
AT91SAM9RL_BASE_US2,
|
||||
AT91SAM9RL_BASE_US3,
|
||||
0,
|
||||
};
|
||||
|
||||
static const u32 uarts_sam9x5[] = {
|
||||
AT91_BASE_DBGU0,
|
||||
AT91SAM9X5_BASE_USART0,
|
||||
AT91SAM9X5_BASE_USART1,
|
||||
AT91SAM9X5_BASE_USART2,
|
||||
0,
|
||||
};
|
||||
|
||||
static inline const u32* decomp_soc_detect(u32 dbgu_base)
|
||||
{
|
||||
u32 cidr, socid;
|
||||
|
||||
cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR);
|
||||
socid = cidr & ~AT91_CIDR_VERSION;
|
||||
|
||||
switch (socid) {
|
||||
case ARCH_ID_AT91RM9200:
|
||||
return uarts_rm9200;
|
||||
|
||||
case ARCH_ID_AT91SAM9G20:
|
||||
case ARCH_ID_AT91SAM9260:
|
||||
return uarts_sam9260;
|
||||
|
||||
case ARCH_ID_AT91SAM9261:
|
||||
return uarts_sam9261;
|
||||
|
||||
case ARCH_ID_AT91SAM9263:
|
||||
return uarts_sam9263;
|
||||
|
||||
case ARCH_ID_AT91SAM9G45:
|
||||
return uarts_sam9g45;
|
||||
|
||||
case ARCH_ID_AT91SAM9RL64:
|
||||
return uarts_sam9rl;
|
||||
|
||||
case ARCH_ID_AT91SAM9X5:
|
||||
return uarts_sam9x5;
|
||||
}
|
||||
|
||||
/* at91sam9g10 */
|
||||
if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
|
||||
return uarts_sam9261;
|
||||
}
|
||||
/* at91sam9xe */
|
||||
else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
|
||||
return uarts_sam9260;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline void arch_decomp_setup(void)
|
||||
{
|
||||
int i = 0;
|
||||
const u32* usarts;
|
||||
|
||||
usarts = decomp_soc_detect(AT91_BASE_DBGU0);
|
||||
|
||||
if (!usarts)
|
||||
usarts = decomp_soc_detect(AT91_BASE_DBGU1);
|
||||
if (!usarts) {
|
||||
at91_uart = NULL;
|
||||
return;
|
||||
}
|
||||
|
||||
do {
|
||||
/* physical address */
|
||||
at91_uart = (void __iomem *)usarts[i];
|
||||
|
||||
if (__raw_readl(at91_uart + ATMEL_US_BRGR))
|
||||
return;
|
||||
i++;
|
||||
} while (usarts[i]);
|
||||
|
||||
at91_uart = NULL;
|
||||
}
|
||||
#else
|
||||
static inline void arch_decomp_setup(void)
|
||||
{
|
||||
at91_uart = NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -52,28 +178,24 @@
|
|||
*/
|
||||
static void putc(int c)
|
||||
{
|
||||
#ifdef UART_OFFSET
|
||||
void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */
|
||||
if (!at91_uart)
|
||||
return;
|
||||
|
||||
while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXRDY))
|
||||
while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY))
|
||||
barrier();
|
||||
__raw_writel(c, sys + ATMEL_US_THR);
|
||||
#endif
|
||||
__raw_writel(c, at91_uart + ATMEL_US_THR);
|
||||
}
|
||||
|
||||
static inline void flush(void)
|
||||
{
|
||||
#ifdef UART_OFFSET
|
||||
void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */
|
||||
if (!at91_uart)
|
||||
return;
|
||||
|
||||
/* wait for transmission to complete */
|
||||
while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
|
||||
while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
|
||||
barrier();
|
||||
#endif
|
||||
}
|
||||
|
||||
#define arch_decomp_setup()
|
||||
|
||||
#define arch_decomp_wdog()
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -261,7 +261,12 @@ static int at91_pm_enter(suspend_state_t state)
|
|||
* For ARM 926 based chips, this requirement is weaker
|
||||
* as at91sam9 can access a RAM in self-refresh mode.
|
||||
*/
|
||||
at91_standby();
|
||||
if (cpu_is_at91rm9200())
|
||||
at91rm9200_standby();
|
||||
else if (cpu_is_at91sam9g45())
|
||||
at91sam9g45_standby();
|
||||
else
|
||||
at91sam9_standby();
|
||||
break;
|
||||
|
||||
case PM_SUSPEND_ON:
|
||||
|
|
@ -307,10 +312,9 @@ static int __init at91_pm_init(void)
|
|||
|
||||
pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91RM9200
|
||||
/* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
|
||||
at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
|
||||
#endif
|
||||
if (cpu_is_at91rm9200())
|
||||
at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
|
||||
|
||||
suspend_set_ops(&at91_pm_ops);
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@
|
|||
#define __ARCH_ARM_MACH_AT91_PM
|
||||
|
||||
#include <mach/at91_ramc.h>
|
||||
#ifdef CONFIG_ARCH_AT91RM9200
|
||||
#include <mach/at91rm9200_sdramc.h>
|
||||
|
||||
/*
|
||||
|
|
@ -43,10 +42,6 @@ static inline void at91rm9200_standby(void)
|
|||
"r" (lpr));
|
||||
}
|
||||
|
||||
#define at91_standby at91rm9200_standby
|
||||
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
||||
|
||||
/* We manage both DDRAM/SDRAM controllers, we need more than one value to
|
||||
* remember.
|
||||
*/
|
||||
|
|
@ -75,11 +70,7 @@ static inline void at91sam9g45_standby(void)
|
|||
at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
|
||||
}
|
||||
|
||||
#define at91_standby at91sam9g45_standby
|
||||
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91SAM9263
|
||||
#ifdef CONFIG_SOC_AT91SAM9263
|
||||
/*
|
||||
* FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
|
||||
* handle those cases both here and in the Suspend-To-RAM support.
|
||||
|
|
@ -102,8 +93,4 @@ static inline void at91sam9_standby(void)
|
|||
at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr);
|
||||
}
|
||||
|
||||
#define at91_standby at91sam9_standby
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@
|
|||
#include <mach/at91_ramc.h>
|
||||
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91SAM9263
|
||||
#ifdef CONFIG_SOC_AT91SAM9263
|
||||
/*
|
||||
* FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
|
||||
* handle those cases both here and in the Suspend-To-RAM support.
|
||||
|
|
|
|||
|
|
@ -26,30 +26,30 @@ static inline int at91_soc_is_enabled(void)
|
|||
return at91_boot_soc.init != NULL;
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_ARCH_AT91RM9200)
|
||||
#if !defined(CONFIG_SOC_AT91RM9200)
|
||||
#define at91rm9200_soc at91_boot_soc
|
||||
#endif
|
||||
|
||||
#if !(defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20))
|
||||
#if !defined(CONFIG_SOC_AT91SAM9260)
|
||||
#define at91sam9260_soc at91_boot_soc
|
||||
#endif
|
||||
|
||||
#if !(defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10))
|
||||
#if !defined(CONFIG_SOC_AT91SAM9261)
|
||||
#define at91sam9261_soc at91_boot_soc
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_ARCH_AT91SAM9263)
|
||||
#if !defined(CONFIG_SOC_AT91SAM9263)
|
||||
#define at91sam9263_soc at91_boot_soc
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_ARCH_AT91SAM9G45)
|
||||
#if !defined(CONFIG_SOC_AT91SAM9G45)
|
||||
#define at91sam9g45_soc at91_boot_soc
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_ARCH_AT91SAM9RL)
|
||||
#if !defined(CONFIG_SOC_AT91SAM9RL)
|
||||
#define at91sam9rl_soc at91_boot_soc
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_ARCH_AT91SAM9X5)
|
||||
#if !defined(CONFIG_SOC_AT91SAM9X5)
|
||||
#define at91sam9x5_soc at91_boot_soc
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
if ARCH_CLPS711X
|
||||
|
||||
menu "CLPS711X/EP721X Implementations"
|
||||
menu "CLPS711X/EP721X/EP731X Implementations"
|
||||
|
||||
config ARCH_AUTCPU12
|
||||
bool "AUTCPU12"
|
||||
|
|
@ -45,26 +45,13 @@ config ARCH_P720T
|
|||
config ARCH_FORTUNET
|
||||
bool "FORTUNET"
|
||||
|
||||
# XXX Maybe these should indicate register compatibility
|
||||
# instead of being mutually exclusive.
|
||||
config ARCH_EP7211
|
||||
bool
|
||||
depends on ARCH_EDB7211
|
||||
default y
|
||||
|
||||
config ARCH_EP7212
|
||||
bool
|
||||
depends on ARCH_P720T || ARCH_CEIVA
|
||||
default y
|
||||
|
||||
config EP72XX_ROM_BOOT
|
||||
bool "EP72xx ROM boot"
|
||||
depends on ARCH_EP7211 || ARCH_EP7212
|
||||
---help---
|
||||
bool "EP721x/EP731x ROM boot"
|
||||
help
|
||||
If you say Y here, your CLPS711x-based kernel will use the bootstrap
|
||||
mode memory map instead of the normal memory map.
|
||||
|
||||
Processors derived from the Cirrus CLPS-711X core support two boot
|
||||
Processors derived from the Cirrus CLPS711X core support two boot
|
||||
modes. Normal mode boots from the external memory device at CS0.
|
||||
Bootstrap mode rearranges parts of the memory map, placing an
|
||||
internal 128 byte bootstrap ROM at CS0. This option performs the
|
||||
|
|
|
|||
|
|
@ -36,7 +36,6 @@
|
|||
#include <asm/page.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/hardware/clps7111.h>
|
||||
#include <asm/system_misc.h>
|
||||
|
||||
/*
|
||||
|
|
@ -44,8 +43,8 @@
|
|||
*/
|
||||
static struct map_desc clps711x_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = CLPS7111_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(CLPS7111_PHYS_BASE),
|
||||
.virtual = (unsigned long)CLPS711X_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(CLPS711X_PHYS_BASE),
|
||||
.length = SZ_1M,
|
||||
.type = MT_DEVICE
|
||||
}
|
||||
|
|
@ -67,12 +66,6 @@ static void int1_mask(struct irq_data *d)
|
|||
|
||||
static void int1_ack(struct irq_data *d)
|
||||
{
|
||||
u32 intmr1;
|
||||
|
||||
intmr1 = clps_readl(INTMR1);
|
||||
intmr1 &= ~(1 << d->irq);
|
||||
clps_writel(intmr1, INTMR1);
|
||||
|
||||
switch (d->irq) {
|
||||
case IRQ_CSINT: clps_writel(0, COEOI); break;
|
||||
case IRQ_TC1OI: clps_writel(0, TC1EOI); break;
|
||||
|
|
@ -109,12 +102,6 @@ static void int2_mask(struct irq_data *d)
|
|||
|
||||
static void int2_ack(struct irq_data *d)
|
||||
{
|
||||
u32 intmr2;
|
||||
|
||||
intmr2 = clps_readl(INTMR2);
|
||||
intmr2 &= ~(1 << (d->irq - 16));
|
||||
clps_writel(intmr2, INTMR2);
|
||||
|
||||
switch (d->irq) {
|
||||
case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
/*
|
||||
* arch/arm/include/asm/hardware/clps7111.h
|
||||
*
|
||||
* This file contains the hardware definitions of the CLPS7111 internal
|
||||
* registers.
|
||||
* This file contains the hardware definitions of the Cirrus Logic
|
||||
* ARM7 CLPS711X internal registers.
|
||||
*
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd.
|
||||
*
|
||||
|
|
@ -20,25 +18,18 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASM_HARDWARE_CLPS7111_H
|
||||
#define __ASM_HARDWARE_CLPS7111_H
|
||||
#ifndef __MACH_CLPS711X_H
|
||||
#define __MACH_CLPS711X_H
|
||||
|
||||
#define CLPS7111_PHYS_BASE (0x80000000)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define clps_readb(off) __raw_readb(CLPS7111_BASE + (off))
|
||||
#define clps_readw(off) __raw_readw(CLPS7111_BASE + (off))
|
||||
#define clps_readl(off) __raw_readl(CLPS7111_BASE + (off))
|
||||
#define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off))
|
||||
#define clps_writew(val,off) __raw_writew(val, CLPS7111_BASE + (off))
|
||||
#define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off))
|
||||
#endif
|
||||
#define CLPS711X_PHYS_BASE (0x80000000)
|
||||
|
||||
#define PADR (0x0000)
|
||||
#define PBDR (0x0001)
|
||||
#define PCDR (0x0002)
|
||||
#define PDDR (0x0003)
|
||||
#define PADDR (0x0040)
|
||||
#define PBDDR (0x0041)
|
||||
#define PCDDR (0x0042)
|
||||
#define PDDDR (0x0043)
|
||||
#define PEDR (0x0080)
|
||||
#define PEDDR (0x00c0)
|
||||
|
|
@ -50,7 +41,7 @@
|
|||
#define INTSR1 (0x0240)
|
||||
#define INTMR1 (0x0280)
|
||||
#define LCDCON (0x02c0)
|
||||
#define TC1D (0x0300)
|
||||
#define TC1D (0x0300)
|
||||
#define TC2D (0x0340)
|
||||
#define RTCDR (0x0380)
|
||||
#define RTCMR (0x03c0)
|
||||
|
|
@ -85,6 +76,26 @@
|
|||
#define SS2POP (0x16c0)
|
||||
#define KBDEOI (0x1700)
|
||||
|
||||
#define DAIR (0x2000)
|
||||
#define DAIR0 (0x2040)
|
||||
#define DAIDR1 (0x2080)
|
||||
#define DAIDR2 (0x20c0)
|
||||
#define DAISR (0x2100)
|
||||
#define SYSCON3 (0x2200)
|
||||
#define INTSR3 (0x2240)
|
||||
#define INTMR3 (0x2280)
|
||||
#define LEDFLSH (0x22c0)
|
||||
#define SDCONF (0x2300)
|
||||
#define SDRFPR (0x2340)
|
||||
#define UNIQID (0x2440)
|
||||
#define DAI64FS (0x2600)
|
||||
#define PLLW (0x2610)
|
||||
#define PLLR (0xa5a8)
|
||||
#define RANDID0 (0x2700)
|
||||
#define RANDID1 (0x2704)
|
||||
#define RANDID2 (0x2708)
|
||||
#define RANDID3 (0x270c)
|
||||
|
||||
/* common bits: SYSCON1 / SYSCON2 */
|
||||
#define SYSCON_UARTEN (1 << 8)
|
||||
|
||||
|
|
@ -131,6 +142,8 @@
|
|||
#define SYSFLG1_CTXFF (1 << 25)
|
||||
#define SYSFLG1_SSIBUSY (1 << 26)
|
||||
#define SYSFLG1_ID (1 << 29)
|
||||
#define SYSFLG1_VERID(x) (((x) >> 30) & 3)
|
||||
#define SYSFLG1_VERID_MASK (3 << 30)
|
||||
|
||||
#define SYSFLG2_SSRXOF (1 << 0)
|
||||
#define SYSFLG2_RESVAL (1 << 1)
|
||||
|
|
@ -178,7 +191,88 @@
|
|||
#define UBRLCR_WRDLEN8 (3 << 17)
|
||||
#define UBRLCR_WRDLEN_MASK (3 << 17)
|
||||
|
||||
#define SYNCIO_FRMLEN(x) (((x) & 0x3f) << 7)
|
||||
#define SYNCIO_CFGLEN(x) ((x) & 0x7f)
|
||||
#define SYNCIO_SMCKEN (1 << 13)
|
||||
#define SYNCIO_TXFRMEN (1 << 14)
|
||||
|
||||
#endif /* __ASM_HARDWARE_CLPS7111_H */
|
||||
#define DAIR_RESERVED (0x0404)
|
||||
#define DAIR_DAIEN (1 << 16)
|
||||
#define DAIR_ECS (1 << 17)
|
||||
#define DAIR_LCTM (1 << 19)
|
||||
#define DAIR_LCRM (1 << 20)
|
||||
#define DAIR_RCTM (1 << 21)
|
||||
#define DAIR_RCRM (1 << 22)
|
||||
#define DAIR_LBM (1 << 23)
|
||||
|
||||
#define DAIDR2_FIFOEN (1 << 15)
|
||||
#define DAIDR2_FIFOLEFT (0x0d << 16)
|
||||
#define DAIDR2_FIFORIGHT (0x11 << 16)
|
||||
|
||||
#define DAISR_RCTS (1 << 0)
|
||||
#define DAISR_RCRS (1 << 1)
|
||||
#define DAISR_LCTS (1 << 2)
|
||||
#define DAISR_LCRS (1 << 3)
|
||||
#define DAISR_RCTU (1 << 4)
|
||||
#define DAISR_RCRO (1 << 5)
|
||||
#define DAISR_LCTU (1 << 6)
|
||||
#define DAISR_LCRO (1 << 7)
|
||||
#define DAISR_RCNF (1 << 8)
|
||||
#define DAISR_RCNE (1 << 9)
|
||||
#define DAISR_LCNF (1 << 10)
|
||||
#define DAISR_LCNE (1 << 11)
|
||||
#define DAISR_FIFO (1 << 12)
|
||||
|
||||
#define DAI64FS_I2SF64 (1 << 0)
|
||||
#define DAI64FS_AUDIOCLKEN (1 << 1)
|
||||
#define DAI64FS_AUDIOCLKSRC (1 << 2)
|
||||
#define DAI64FS_MCLK256EN (1 << 3)
|
||||
#define DAI64FS_LOOPBACK (1 << 5)
|
||||
|
||||
#define SYSCON3_ADCCON (1 << 0)
|
||||
#define SYSCON3_CLKCTL0 (1 << 1)
|
||||
#define SYSCON3_CLKCTL1 (1 << 2)
|
||||
#define SYSCON3_DAISEL (1 << 3)
|
||||
#define SYSCON3_ADCCKNSEN (1 << 4)
|
||||
#define SYSCON3_VERSN(x) (((x) >> 5) & 7)
|
||||
#define SYSCON3_VERSN_MASK (7 << 5)
|
||||
#define SYSCON3_FASTWAKE (1 << 8)
|
||||
#define SYSCON3_DAIEN (1 << 9)
|
||||
#define SYSCON3_128FS SYSCON3_DAIEN
|
||||
#define SYSCON3_ENPD67 (1 << 10)
|
||||
|
||||
#define SDCONF_ACTIVE (1 << 10)
|
||||
#define SDCONF_CLKCTL (1 << 9)
|
||||
#define SDCONF_WIDTH_4 (0 << 7)
|
||||
#define SDCONF_WIDTH_8 (1 << 7)
|
||||
#define SDCONF_WIDTH_16 (2 << 7)
|
||||
#define SDCONF_WIDTH_32 (3 << 7)
|
||||
#define SDCONF_SIZE_16 (0 << 5)
|
||||
#define SDCONF_SIZE_64 (1 << 5)
|
||||
#define SDCONF_SIZE_128 (2 << 5)
|
||||
#define SDCONF_SIZE_256 (3 << 5)
|
||||
#define SDCONF_CASLAT_2 (2)
|
||||
#define SDCONF_CASLAT_3 (3)
|
||||
|
||||
#define MEMCFG_BUS_WIDTH_32 (1)
|
||||
#define MEMCFG_BUS_WIDTH_16 (0)
|
||||
#define MEMCFG_BUS_WIDTH_8 (3)
|
||||
|
||||
#define MEMCFG_WAITSTATE_8_3 (0 << 2)
|
||||
#define MEMCFG_WAITSTATE_7_3 (1 << 2)
|
||||
#define MEMCFG_WAITSTATE_6_3 (2 << 2)
|
||||
#define MEMCFG_WAITSTATE_5_3 (3 << 2)
|
||||
#define MEMCFG_WAITSTATE_4_2 (4 << 2)
|
||||
#define MEMCFG_WAITSTATE_3_2 (5 << 2)
|
||||
#define MEMCFG_WAITSTATE_2_2 (6 << 2)
|
||||
#define MEMCFG_WAITSTATE_1_2 (7 << 2)
|
||||
#define MEMCFG_WAITSTATE_8_1 (8 << 2)
|
||||
#define MEMCFG_WAITSTATE_7_1 (9 << 2)
|
||||
#define MEMCFG_WAITSTATE_6_1 (10 << 2)
|
||||
#define MEMCFG_WAITSTATE_5_1 (11 << 2)
|
||||
#define MEMCFG_WAITSTATE_4_0 (12 << 2)
|
||||
#define MEMCFG_WAITSTATE_3_0 (13 << 2)
|
||||
#define MEMCFG_WAITSTATE_2_0 (14 << 2)
|
||||
#define MEMCFG_WAITSTATE_1_0 (15 << 2)
|
||||
|
||||
#endif /* __MACH_CLPS711X_H */
|
||||
|
|
@ -12,7 +12,6 @@
|
|||
*/
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/hardware/clps7111.h>
|
||||
|
||||
.macro addruart, rp, rv, tmp
|
||||
#ifndef CONFIG_DEBUG_CLPS711X_UART2
|
||||
|
|
@ -20,8 +19,8 @@
|
|||
#else
|
||||
mov \rp, #0x1000 @ UART2
|
||||
#endif
|
||||
orr \rv, \rp, #CLPS7111_VIRT_BASE
|
||||
orr \rp, \rp, #CLPS7111_PHYS_BASE
|
||||
orr \rv, \rp, #CLPS711X_VIRT_BASE
|
||||
orr \rp, \rp, #CLPS711X_PHYS_BASE
|
||||
.endm
|
||||
|
||||
.macro senduart,rd,rx
|
||||
|
|
|
|||
|
|
@ -8,7 +8,6 @@
|
|||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/hardware/clps7111.h>
|
||||
|
||||
.macro get_irqnr_preamble, base, tmp
|
||||
.endm
|
||||
|
|
@ -18,7 +17,7 @@
|
|||
#endif
|
||||
|
||||
.macro get_irqnr_and_base, irqnr, stat, base, mask
|
||||
mov \base, #CLPS7111_BASE
|
||||
mov \base, #CLPS711X_VIRT_BASE
|
||||
ldr \stat, [\base, #INTSR1]
|
||||
ldr \mask, [\base, #INTMR1]
|
||||
mov \irqnr, #4
|
||||
|
|
|
|||
|
|
@ -19,12 +19,21 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASM_ARCH_HARDWARE_H
|
||||
#define __ASM_ARCH_HARDWARE_H
|
||||
#ifndef __MACH_HARDWARE_H
|
||||
#define __MACH_HARDWARE_H
|
||||
|
||||
#include <mach/clps711x.h>
|
||||
|
||||
#define CLPS7111_VIRT_BASE 0xff000000
|
||||
#define CLPS7111_BASE CLPS7111_VIRT_BASE
|
||||
#define CLPS711X_VIRT_BASE IOMEM(0xff000000)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define clps_readb(off) readb(CLPS711X_VIRT_BASE + (off))
|
||||
#define clps_readw(off) readw(CLPS711X_VIRT_BASE + (off))
|
||||
#define clps_readl(off) readl(CLPS711X_VIRT_BASE + (off))
|
||||
#define clps_writeb(val,off) writeb(val, CLPS711X_VIRT_BASE + (off))
|
||||
#define clps_writew(val,off) writew(val, CLPS711X_VIRT_BASE + (off))
|
||||
#define clps_writel(val,off) writel(val, CLPS711X_VIRT_BASE + (off))
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The physical addresses that the external chip select signals map to is
|
||||
|
|
@ -52,46 +61,11 @@
|
|||
#define CS7_PHYS_BASE (0x00000000)
|
||||
#endif
|
||||
|
||||
#if defined (CONFIG_ARCH_EP7211)
|
||||
|
||||
#define EP7211_VIRT_BASE CLPS7111_VIRT_BASE
|
||||
#define EP7211_BASE CLPS7111_VIRT_BASE
|
||||
#include <asm/hardware/ep7211.h>
|
||||
|
||||
#elif defined (CONFIG_ARCH_EP7212)
|
||||
|
||||
#define EP7212_VIRT_BASE CLPS7111_VIRT_BASE
|
||||
#define EP7212_BASE CLPS7111_VIRT_BASE
|
||||
#include <asm/hardware/ep7212.h>
|
||||
|
||||
#endif
|
||||
|
||||
#define SYSPLD_VIRT_BASE 0xfe000000
|
||||
#define SYSPLD_BASE SYSPLD_VIRT_BASE
|
||||
|
||||
#if defined (CONFIG_ARCH_AUTCPU12)
|
||||
|
||||
#define CS89712_VIRT_BASE CLPS7111_VIRT_BASE
|
||||
#define CS89712_BASE CLPS7111_VIRT_BASE
|
||||
|
||||
#include <asm/hardware/clps7111.h>
|
||||
#include <asm/hardware/ep7212.h>
|
||||
#include <asm/hardware/cs89712.h>
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (CONFIG_ARCH_CDB89712)
|
||||
|
||||
#include <asm/hardware/clps7111.h>
|
||||
#include <asm/hardware/ep7212.h>
|
||||
#include <asm/hardware/cs89712.h>
|
||||
|
||||
/* static cdb89712_map_io() areas */
|
||||
#define REGISTER_START 0x80000000
|
||||
#define REGISTER_SIZE 0x4000
|
||||
#define REGISTER_BASE 0xff000000
|
||||
|
||||
#define ETHER_START 0x20000000
|
||||
#define ETHER_SIZE 0x1000
|
||||
#define ETHER_BASE 0xfe000000
|
||||
|
|
@ -154,13 +128,6 @@
|
|||
|
||||
#if defined (CONFIG_ARCH_CEIVA)
|
||||
|
||||
#define CEIVA_VIRT_BASE CLPS7111_VIRT_BASE
|
||||
#define CEIVA_BASE CLPS7111_VIRT_BASE
|
||||
|
||||
#include <asm/hardware/clps7111.h>
|
||||
#include <asm/hardware/ep7212.h>
|
||||
|
||||
|
||||
/*
|
||||
* The two flash banks are wired to chip selects 0 and 1. This is the mapping
|
||||
* for them.
|
||||
|
|
|
|||
|
|
@ -35,7 +35,6 @@
|
|||
#define IRQ_SSEOTI 15
|
||||
|
||||
#define INT1_IRQS (0x0000fff0)
|
||||
#define INT1_ACK_IRQS (0x00004f10)
|
||||
|
||||
/*
|
||||
* Interrupts from INTSR2
|
||||
|
|
@ -47,7 +46,5 @@
|
|||
#define IRQ_URXINT2 (16+13) /* bit 13 */
|
||||
|
||||
#define INT2_IRQS (0x30070000)
|
||||
#define INT2_ACK_IRQS (0x00010000)
|
||||
|
||||
#define NR_IRQS 30
|
||||
|
||||
#define NR_IRQS 30
|
||||
|
|
|
|||
|
|
@ -1,49 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-clps711x/include/mach/time.h
|
||||
*
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <asm/leds.h>
|
||||
#include <asm/hardware/clps7111.h>
|
||||
|
||||
extern void clps711x_setup_timer(void);
|
||||
|
||||
/*
|
||||
* IRQ handler for the timer
|
||||
*/
|
||||
static irqreturn_t
|
||||
p720t_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct pt_regs *regs = get_irq_regs();
|
||||
do_leds();
|
||||
xtime_update(1);
|
||||
#ifndef CONFIG_SMP
|
||||
update_process_times(user_mode(regs));
|
||||
#endif
|
||||
do_profile(regs);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set up timer interrupt, and return the current time in seconds.
|
||||
*/
|
||||
void __init time_init(void)
|
||||
{
|
||||
clps711x_setup_timer();
|
||||
timer_irq.handler = p720t_timer_interrupt;
|
||||
setup_irq(IRQ_TC2OI, &timer_irq);
|
||||
}
|
||||
|
|
@ -17,14 +17,7 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/hardware/clps7111.h>
|
||||
|
||||
#undef CLPS7111_BASE
|
||||
#define CLPS7111_BASE CLPS7111_PHYS_BASE
|
||||
|
||||
#define __raw_readl(p) (*(unsigned long *)(p))
|
||||
#define __raw_writel(v,p) (*(unsigned long *)(p) = (v))
|
||||
#include <mach/clps711x.h>
|
||||
|
||||
#ifdef CONFIG_DEBUG_CLPS711X_UART2
|
||||
#define SYSFLGx SYSFLG2
|
||||
|
|
@ -34,19 +27,25 @@
|
|||
#define UARTDRx UARTDR1
|
||||
#endif
|
||||
|
||||
#define phys_reg(x) (*(volatile u32 *)(CLPS711X_PHYS_BASE + (x)))
|
||||
|
||||
/*
|
||||
* The following code assumes the serial port has already been
|
||||
* initialized by the bootloader. If you didn't setup a port in
|
||||
* your bootloader then nothing will appear (which might be desired).
|
||||
*
|
||||
* This does not append a newline
|
||||
*/
|
||||
static inline void putc(int c)
|
||||
{
|
||||
while (clps_readl(SYSFLGx) & SYSFLG_UTXFF)
|
||||
while (phys_reg(SYSFLGx) & SYSFLG_UTXFF)
|
||||
barrier();
|
||||
clps_writel(c, UARTDRx);
|
||||
phys_reg(UARTDRx) = c;
|
||||
}
|
||||
|
||||
static inline void flush(void)
|
||||
{
|
||||
while (clps_readl(SYSFLGx) & SYSFLG_UBUSY)
|
||||
while (phys_reg(SYSFLGx) & SYSFLG_UBUSY)
|
||||
barrier();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -27,9 +27,6 @@
|
|||
#include <asm/leds.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <asm/hardware/clps7111.h>
|
||||
#include <asm/hardware/ep7212.h>
|
||||
|
||||
static void p720t_leds_event(led_event_t ledevt)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
|
|
|||
|
|
@ -181,7 +181,7 @@ static int get_tclk(void)
|
|||
return 166666667;
|
||||
}
|
||||
|
||||
static void dove_timer_init(void)
|
||||
static void __init dove_timer_init(void)
|
||||
{
|
||||
orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
|
||||
IRQ_DOVE_BRIDGE, get_tclk());
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
|
|||
|
||||
/* Dump all the extra MPP registers. The platform code will dump the
|
||||
registers for pins 0-23. */
|
||||
static void dove_mpp_dump_regs(void)
|
||||
static void __init dove_mpp_dump_regs(void)
|
||||
{
|
||||
pr_debug("PMU_CTRL4_CTRL: %08x\n",
|
||||
readl(DOVE_MPP_CTRL4_VIRT_BASE));
|
||||
|
|
@ -67,7 +67,7 @@ static void dove_mpp_dump_regs(void)
|
|||
pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
|
||||
}
|
||||
|
||||
static void dove_mpp_cfg_nfc(int sel)
|
||||
static void __init dove_mpp_cfg_nfc(int sel)
|
||||
{
|
||||
u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE);
|
||||
|
||||
|
|
@ -78,7 +78,7 @@ static void dove_mpp_cfg_nfc(int sel)
|
|||
dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK);
|
||||
}
|
||||
|
||||
static void dove_mpp_cfg_au1(int sel)
|
||||
static void __init dove_mpp_cfg_au1(int sel)
|
||||
{
|
||||
u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
|
||||
u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
|
||||
|
|
@ -118,7 +118,7 @@ static void dove_mpp_cfg_au1(int sel)
|
|||
|
||||
/* Configure the group registers, enabling GPIO if sel indicates the
|
||||
pin is to be used for GPIO */
|
||||
static void dove_mpp_conf_grp(unsigned int *mpp_grp_list)
|
||||
static void __init dove_mpp_conf_grp(unsigned int *mpp_grp_list)
|
||||
{
|
||||
u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
|
||||
int gpio_mode;
|
||||
|
|
|
|||
|
|
@ -2,6 +2,11 @@ if ARCH_EP93XX
|
|||
|
||||
menu "Cirrus EP93xx Implementation Options"
|
||||
|
||||
config EP93XX_SOC_COMMON
|
||||
bool
|
||||
default y
|
||||
select LEDS_GPIO_REGISTER
|
||||
|
||||
config CRUNCH
|
||||
bool "Support for MaverickCrunch"
|
||||
help
|
||||
|
|
|
|||
|
|
@ -241,11 +241,7 @@ unsigned int ep93xx_chip_revision(void)
|
|||
* EP93xx GPIO
|
||||
*************************************************************************/
|
||||
static struct resource ep93xx_gpio_resource[] = {
|
||||
{
|
||||
.start = EP93XX_GPIO_PHYS_BASE,
|
||||
.end = EP93XX_GPIO_PHYS_BASE + 0xcc - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc),
|
||||
};
|
||||
|
||||
static struct platform_device ep93xx_gpio_device = {
|
||||
|
|
@ -288,11 +284,7 @@ static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE,
|
|||
{ IRQ_EP93XX_UART3 }, &ep93xx_uart_data);
|
||||
|
||||
static struct resource ep93xx_rtc_resource[] = {
|
||||
{
|
||||
.start = EP93XX_RTC_PHYS_BASE,
|
||||
.end = EP93XX_RTC_PHYS_BASE + 0x10c - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
DEFINE_RES_MEM(EP93XX_RTC_PHYS_BASE, 0x10c),
|
||||
};
|
||||
|
||||
static struct platform_device ep93xx_rtc_device = {
|
||||
|
|
@ -304,16 +296,8 @@ static struct platform_device ep93xx_rtc_device = {
|
|||
|
||||
|
||||
static struct resource ep93xx_ohci_resources[] = {
|
||||
[0] = {
|
||||
.start = EP93XX_USB_PHYS_BASE,
|
||||
.end = EP93XX_USB_PHYS_BASE + 0x0fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_EP93XX_USB,
|
||||
.end = IRQ_EP93XX_USB,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE, 0x1000),
|
||||
DEFINE_RES_IRQ(IRQ_EP93XX_USB),
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -372,15 +356,8 @@ void __init ep93xx_register_flash(unsigned int width,
|
|||
static struct ep93xx_eth_data ep93xx_eth_data;
|
||||
|
||||
static struct resource ep93xx_eth_resource[] = {
|
||||
{
|
||||
.start = EP93XX_ETHERNET_PHYS_BASE,
|
||||
.end = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_EP93XX_ETHERNET,
|
||||
.end = IRQ_EP93XX_ETHERNET,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
DEFINE_RES_MEM(EP93XX_ETHERNET_PHYS_BASE, 0x10000),
|
||||
DEFINE_RES_IRQ(IRQ_EP93XX_ETHERNET),
|
||||
};
|
||||
|
||||
static u64 ep93xx_eth_dma_mask = DMA_BIT_MASK(32);
|
||||
|
|
@ -461,16 +438,8 @@ void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
|
|||
static struct ep93xx_spi_info ep93xx_spi_master_data;
|
||||
|
||||
static struct resource ep93xx_spi_resources[] = {
|
||||
{
|
||||
.start = EP93XX_SPI_PHYS_BASE,
|
||||
.end = EP93XX_SPI_PHYS_BASE + 0x18 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_EP93XX_SSP,
|
||||
.end = IRQ_EP93XX_SSP,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
DEFINE_RES_MEM(EP93XX_SPI_PHYS_BASE, 0x18),
|
||||
DEFINE_RES_IRQ(IRQ_EP93XX_SSP),
|
||||
};
|
||||
|
||||
static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32);
|
||||
|
|
@ -513,7 +482,7 @@ void __init ep93xx_register_spi(struct ep93xx_spi_info *info,
|
|||
/*************************************************************************
|
||||
* EP93xx LEDs
|
||||
*************************************************************************/
|
||||
static struct gpio_led ep93xx_led_pins[] = {
|
||||
static const struct gpio_led ep93xx_led_pins[] __initconst = {
|
||||
{
|
||||
.name = "platform:grled",
|
||||
.gpio = EP93XX_GPIO_LINE_GRLED,
|
||||
|
|
@ -523,29 +492,16 @@ static struct gpio_led ep93xx_led_pins[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct gpio_led_platform_data ep93xx_led_data = {
|
||||
static const struct gpio_led_platform_data ep93xx_led_data __initconst = {
|
||||
.num_leds = ARRAY_SIZE(ep93xx_led_pins),
|
||||
.leds = ep93xx_led_pins,
|
||||
};
|
||||
|
||||
static struct platform_device ep93xx_leds = {
|
||||
.name = "leds-gpio",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &ep93xx_led_data,
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* EP93xx pwm peripheral handling
|
||||
*************************************************************************/
|
||||
static struct resource ep93xx_pwm0_resource[] = {
|
||||
{
|
||||
.start = EP93XX_PWM_PHYS_BASE,
|
||||
.end = EP93XX_PWM_PHYS_BASE + 0x10 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE, 0x10),
|
||||
};
|
||||
|
||||
static struct platform_device ep93xx_pwm0_device = {
|
||||
|
|
@ -556,11 +512,7 @@ static struct platform_device ep93xx_pwm0_device = {
|
|||
};
|
||||
|
||||
static struct resource ep93xx_pwm1_resource[] = {
|
||||
{
|
||||
.start = EP93XX_PWM_PHYS_BASE + 0x20,
|
||||
.end = EP93XX_PWM_PHYS_BASE + 0x30 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE + 0x20, 0x10),
|
||||
};
|
||||
|
||||
static struct platform_device ep93xx_pwm1_device = {
|
||||
|
|
@ -628,11 +580,7 @@ EXPORT_SYMBOL(ep93xx_pwm_release_gpio);
|
|||
static struct ep93xxfb_mach_info ep93xxfb_data;
|
||||
|
||||
static struct resource ep93xx_fb_resource[] = {
|
||||
{
|
||||
.start = EP93XX_RASTER_PHYS_BASE,
|
||||
.end = EP93XX_RASTER_PHYS_BASE + 0x800 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE, 0x800),
|
||||
};
|
||||
|
||||
static struct platform_device ep93xx_fb_device = {
|
||||
|
|
@ -680,15 +628,8 @@ void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
|
|||
static struct ep93xx_keypad_platform_data ep93xx_keypad_data;
|
||||
|
||||
static struct resource ep93xx_keypad_resource[] = {
|
||||
{
|
||||
.start = EP93XX_KEY_MATRIX_PHYS_BASE,
|
||||
.end = EP93XX_KEY_MATRIX_PHYS_BASE + 0x0c - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_EP93XX_KEY,
|
||||
.end = IRQ_EP93XX_KEY,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
DEFINE_RES_MEM(EP93XX_KEY_MATRIX_PHYS_BASE, 0x0c),
|
||||
DEFINE_RES_IRQ(IRQ_EP93XX_KEY),
|
||||
};
|
||||
|
||||
static struct platform_device ep93xx_keypad_device = {
|
||||
|
|
@ -761,11 +702,7 @@ EXPORT_SYMBOL(ep93xx_keypad_release_gpio);
|
|||
* EP93xx I2S audio peripheral handling
|
||||
*************************************************************************/
|
||||
static struct resource ep93xx_i2s_resource[] = {
|
||||
{
|
||||
.start = EP93XX_I2S_PHYS_BASE,
|
||||
.end = EP93XX_I2S_PHYS_BASE + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100),
|
||||
};
|
||||
|
||||
static struct platform_device ep93xx_i2s_device = {
|
||||
|
|
@ -824,16 +761,8 @@ EXPORT_SYMBOL(ep93xx_i2s_release);
|
|||
* EP93xx AC97 audio peripheral handling
|
||||
*************************************************************************/
|
||||
static struct resource ep93xx_ac97_resources[] = {
|
||||
{
|
||||
.start = EP93XX_AAC_PHYS_BASE,
|
||||
.end = EP93XX_AAC_PHYS_BASE + 0xac - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_EP93XX_AACINTR,
|
||||
.end = IRQ_EP93XX_AACINTR,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
DEFINE_RES_MEM(EP93XX_AAC_PHYS_BASE, 0xac),
|
||||
DEFINE_RES_IRQ(IRQ_EP93XX_AACINTR),
|
||||
};
|
||||
|
||||
static struct platform_device ep93xx_ac97_device = {
|
||||
|
|
@ -889,8 +818,9 @@ void __init ep93xx_init_devices(void)
|
|||
|
||||
platform_device_register(&ep93xx_rtc_device);
|
||||
platform_device_register(&ep93xx_ohci_device);
|
||||
platform_device_register(&ep93xx_leds);
|
||||
platform_device_register(&ep93xx_wdt_device);
|
||||
|
||||
gpio_led_register_device(-1, &ep93xx_led_data);
|
||||
}
|
||||
|
||||
void ep93xx_restart(char mode, const char *cmd)
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#include <asm/smp_scu.h>
|
||||
#include <asm/suspend.h>
|
||||
#include <asm/unified.h>
|
||||
#include <asm/cpuidle.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
#include <mach/pmu.h>
|
||||
|
||||
|
|
@ -34,22 +35,12 @@
|
|||
|
||||
#define S5P_CHECK_AFTR 0xFCBA0D10
|
||||
|
||||
static int exynos4_enter_idle(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv,
|
||||
int index);
|
||||
static int exynos4_enter_lowpower(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv,
|
||||
int index);
|
||||
|
||||
static struct cpuidle_state exynos4_cpuidle_set[] __initdata = {
|
||||
[0] = {
|
||||
.enter = exynos4_enter_idle,
|
||||
.exit_latency = 1,
|
||||
.target_residency = 100000,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||
.name = "C0",
|
||||
.desc = "ARM clock gating(WFI)",
|
||||
},
|
||||
[0] = ARM_CPUIDLE_WFI_STATE,
|
||||
[1] = {
|
||||
.enter = exynos4_enter_lowpower,
|
||||
.exit_latency = 300,
|
||||
|
|
@ -63,8 +54,9 @@ static struct cpuidle_state exynos4_cpuidle_set[] __initdata = {
|
|||
static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
|
||||
|
||||
static struct cpuidle_driver exynos4_idle_driver = {
|
||||
.name = "exynos4_idle",
|
||||
.owner = THIS_MODULE,
|
||||
.name = "exynos4_idle",
|
||||
.owner = THIS_MODULE,
|
||||
.en_core_tk_irqen = 1,
|
||||
};
|
||||
|
||||
/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
|
||||
|
|
@ -103,13 +95,8 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
|
|||
struct cpuidle_driver *drv,
|
||||
int index)
|
||||
{
|
||||
struct timeval before, after;
|
||||
int idle_time;
|
||||
unsigned long tmp;
|
||||
|
||||
local_irq_disable();
|
||||
do_gettimeofday(&before);
|
||||
|
||||
exynos4_set_wakeupmask();
|
||||
|
||||
/* Set value of power down register for aftr mode */
|
||||
|
|
@ -150,34 +137,6 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
|
|||
/* Clear wakeup state register */
|
||||
__raw_writel(0x0, S5P_WAKEUP_STAT);
|
||||
|
||||
do_gettimeofday(&after);
|
||||
|
||||
local_irq_enable();
|
||||
idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
|
||||
(after.tv_usec - before.tv_usec);
|
||||
|
||||
dev->last_residency = idle_time;
|
||||
return index;
|
||||
}
|
||||
|
||||
static int exynos4_enter_idle(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv,
|
||||
int index)
|
||||
{
|
||||
struct timeval before, after;
|
||||
int idle_time;
|
||||
|
||||
local_irq_disable();
|
||||
do_gettimeofday(&before);
|
||||
|
||||
cpu_do_idle();
|
||||
|
||||
do_gettimeofday(&after);
|
||||
local_irq_enable();
|
||||
idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
|
||||
(after.tv_usec - before.tv_usec);
|
||||
|
||||
dev->last_residency = idle_time;
|
||||
return index;
|
||||
}
|
||||
|
||||
|
|
@ -192,7 +151,7 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev,
|
|||
new_index = drv->safe_state_index;
|
||||
|
||||
if (new_index == 0)
|
||||
return exynos4_enter_idle(dev, drv, new_index);
|
||||
return arm_cpuidle_simple_enter(dev, drv, new_index);
|
||||
else
|
||||
return exynos4_enter_core0_aftr(dev, drv, new_index);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -236,16 +236,8 @@ static struct ahci_platform_data exynos4_ahci_pdata = {
|
|||
};
|
||||
|
||||
static struct resource exynos4_ahci_resource[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_SATA,
|
||||
.end = EXYNOS4_PA_SATA + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = EXYNOS4_IRQ_SATA,
|
||||
.end = EXYNOS4_IRQ_SATA,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_SATA, SZ_64K),
|
||||
[1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_SATA),
|
||||
};
|
||||
|
||||
static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);
|
||||
|
|
|
|||
|
|
@ -62,26 +62,10 @@ static struct s3c_audio_pdata i2sv5_pdata = {
|
|||
};
|
||||
|
||||
static struct resource exynos4_i2s0_resource[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_I2S0,
|
||||
.end = EXYNOS4_PA_I2S0 + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = DMACH_I2S0_TX,
|
||||
.end = DMACH_I2S0_TX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[2] = {
|
||||
.start = DMACH_I2S0_RX,
|
||||
.end = DMACH_I2S0_RX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[3] = {
|
||||
.start = DMACH_I2S0S_TX,
|
||||
.end = DMACH_I2S0S_TX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S0, SZ_256),
|
||||
[1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
|
||||
[2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
|
||||
[3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
|
||||
};
|
||||
|
||||
struct platform_device exynos4_device_i2s0 = {
|
||||
|
|
@ -110,21 +94,9 @@ static struct s3c_audio_pdata i2sv3_pdata = {
|
|||
};
|
||||
|
||||
static struct resource exynos4_i2s1_resource[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_I2S1,
|
||||
.end = EXYNOS4_PA_I2S1 + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = DMACH_I2S1_TX,
|
||||
.end = DMACH_I2S1_TX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[2] = {
|
||||
.start = DMACH_I2S1_RX,
|
||||
.end = DMACH_I2S1_RX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S1, SZ_256),
|
||||
[1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
|
||||
[2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
|
||||
};
|
||||
|
||||
struct platform_device exynos4_device_i2s1 = {
|
||||
|
|
@ -138,21 +110,9 @@ struct platform_device exynos4_device_i2s1 = {
|
|||
};
|
||||
|
||||
static struct resource exynos4_i2s2_resource[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_I2S2,
|
||||
.end = EXYNOS4_PA_I2S2 + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = DMACH_I2S2_TX,
|
||||
.end = DMACH_I2S2_TX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[2] = {
|
||||
.start = DMACH_I2S2_RX,
|
||||
.end = DMACH_I2S2_RX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S2, SZ_256),
|
||||
[1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
|
||||
[2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
|
||||
};
|
||||
|
||||
struct platform_device exynos4_device_i2s2 = {
|
||||
|
|
@ -192,21 +152,9 @@ static struct s3c_audio_pdata s3c_pcm_pdata = {
|
|||
};
|
||||
|
||||
static struct resource exynos4_pcm0_resource[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_PCM0,
|
||||
.end = EXYNOS4_PA_PCM0 + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = DMACH_PCM0_TX,
|
||||
.end = DMACH_PCM0_TX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[2] = {
|
||||
.start = DMACH_PCM0_RX,
|
||||
.end = DMACH_PCM0_RX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM0, SZ_256),
|
||||
[1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
|
||||
[2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
|
||||
};
|
||||
|
||||
struct platform_device exynos4_device_pcm0 = {
|
||||
|
|
@ -220,21 +168,9 @@ struct platform_device exynos4_device_pcm0 = {
|
|||
};
|
||||
|
||||
static struct resource exynos4_pcm1_resource[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_PCM1,
|
||||
.end = EXYNOS4_PA_PCM1 + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = DMACH_PCM1_TX,
|
||||
.end = DMACH_PCM1_TX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[2] = {
|
||||
.start = DMACH_PCM1_RX,
|
||||
.end = DMACH_PCM1_RX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM1, SZ_256),
|
||||
[1] = DEFINE_RES_DMA(DMACH_PCM1_TX),
|
||||
[2] = DEFINE_RES_DMA(DMACH_PCM1_RX),
|
||||
};
|
||||
|
||||
struct platform_device exynos4_device_pcm1 = {
|
||||
|
|
@ -248,21 +184,9 @@ struct platform_device exynos4_device_pcm1 = {
|
|||
};
|
||||
|
||||
static struct resource exynos4_pcm2_resource[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_PCM2,
|
||||
.end = EXYNOS4_PA_PCM2 + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = DMACH_PCM2_TX,
|
||||
.end = DMACH_PCM2_TX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[2] = {
|
||||
.start = DMACH_PCM2_RX,
|
||||
.end = DMACH_PCM2_RX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM2, SZ_256),
|
||||
[1] = DEFINE_RES_DMA(DMACH_PCM2_TX),
|
||||
[2] = DEFINE_RES_DMA(DMACH_PCM2_RX),
|
||||
};
|
||||
|
||||
struct platform_device exynos4_device_pcm2 = {
|
||||
|
|
@ -283,31 +207,11 @@ static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
static struct resource exynos4_ac97_resource[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_AC97,
|
||||
.end = EXYNOS4_PA_AC97 + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = DMACH_AC97_PCMOUT,
|
||||
.end = DMACH_AC97_PCMOUT,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[2] = {
|
||||
.start = DMACH_AC97_PCMIN,
|
||||
.end = DMACH_AC97_PCMIN,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[3] = {
|
||||
.start = DMACH_AC97_MICIN,
|
||||
.end = DMACH_AC97_MICIN,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[4] = {
|
||||
.start = EXYNOS4_IRQ_AC97,
|
||||
.end = EXYNOS4_IRQ_AC97,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_AC97, SZ_256),
|
||||
[1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT),
|
||||
[2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN),
|
||||
[3] = DEFINE_RES_DMA(DMACH_AC97_MICIN),
|
||||
[4] = DEFINE_RES_IRQ(EXYNOS4_IRQ_AC97),
|
||||
};
|
||||
|
||||
static struct s3c_audio_pdata s3c_ac97_pdata = {
|
||||
|
|
@ -338,16 +242,8 @@ static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
static struct resource exynos4_spdif_resource[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_SPDIF,
|
||||
.end = EXYNOS4_PA_SPDIF + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = DMACH_SPDIF,
|
||||
.end = DMACH_SPDIF,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_SPDIF, SZ_256),
|
||||
[1] = DEFINE_RES_DMA(DMACH_SPDIF),
|
||||
};
|
||||
|
||||
static struct s3c_audio_pdata samsung_spdif_pdata = {
|
||||
|
|
|
|||
|
|
@ -77,7 +77,6 @@ static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
|
|||
|
||||
static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_PERMANENT,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
|
||||
.max_width = 8,
|
||||
.host_caps = MMC_CAP_8_BIT_DATA,
|
||||
|
|
@ -88,13 +87,11 @@ static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
|
|||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.ext_cd_gpio = EXYNOS4_GPX2(5),
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
.max_width = 4,
|
||||
};
|
||||
|
||||
static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_PERMANENT,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
.max_width = 4,
|
||||
};
|
||||
|
||||
|
|
@ -121,16 +118,9 @@ static void __init armlex4210_wlan_init(void)
|
|||
}
|
||||
|
||||
static struct resource armlex4210_smsc911x_resources[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_SROM_BANK(3),
|
||||
.end = EXYNOS4_PA_SROM_BANK(3) + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_EINT(27),
|
||||
.end = IRQ_EINT(27),
|
||||
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
|
||||
},
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(3), SZ_64K),
|
||||
[1] = DEFINE_RES_NAMED(IRQ_EINT(27), 1, NULL, IORESOURCE_IRQ \
|
||||
| IRQF_TRIGGER_HIGH),
|
||||
};
|
||||
|
||||
static struct smsc911x_platform_config smsc9215_config = {
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue