ixgbe: use EIAM to automask MSI-X
when disabling interrupts, driver was writing with IO, this is no necessary because on ixgbe parts the hardware can "oneshot" disable and clear the interrupt. So on 82598/82599 use of EIAM should avoid one posted write per interrupt when in MSI-X mode. This should improve performance and seems to in my limited testing, reduce CPU utilization VERY slightly. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Acked-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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1 changed files with 19 additions and 6 deletions
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@ -1329,8 +1329,7 @@ static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
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r_idx + 1);
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r_idx + 1);
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}
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}
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/* disable interrupts on this vector only */
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/* EIAM disabled interrupts (on this vector) for us */
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ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
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napi_schedule(&q_vector->napi);
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napi_schedule(&q_vector->napi);
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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@ -1362,7 +1361,7 @@ static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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/* disable interrupts on this vector only */
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/* disable interrupts on this vector only */
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ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
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/* EIAM disabled interrupts (on this vector) for us */
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napi_schedule(&q_vector->napi);
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napi_schedule(&q_vector->napi);
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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@ -1397,8 +1396,7 @@ static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
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r_idx + 1);
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r_idx + 1);
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}
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}
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/* disable interrupts on this vector only */
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/* EIAM disabled interrupts (on this vector) for us */
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ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
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napi_schedule(&q_vector->napi);
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napi_schedule(&q_vector->napi);
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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@ -2716,7 +2714,22 @@ static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
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IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
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IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
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}
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}
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if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
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if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
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/*
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* use EIAM to auto-mask when MSI-X interrupt is asserted
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* this saves a register write for every interrupt
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*/
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switch (hw->mac.type) {
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case ixgbe_mac_82598EB:
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IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
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break;
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default:
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case ixgbe_mac_82599EB:
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IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
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IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
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break;
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}
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} else {
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/* legacy interrupts, use EIAM to auto-mask when reading EICR,
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/* legacy interrupts, use EIAM to auto-mask when reading EICR,
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* specifically only auto mask tx and rx interrupts */
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* specifically only auto mask tx and rx interrupts */
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IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
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IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
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