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V4L/DVB: tm6000: Replace all magic values by a register alias

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Instead of using magic pairs of req/reg, replace them by the defined
values.

This patch were generated by the following script:

cat tm6000-regs.h |perl -ne 'if (m/(TM6010_REQ[^\s]+)\s+0x([a-f0-9]+)\,
0x([a-f0-9]+)/) { $name="$1"; $req=$2; $val=$3; printf
"s/REQ_${req}_SET_GET_AVREG[_BIT]*, 0x[0]*$3,/$1,/\n" }'  >a; for i in
tm*.c; do sed -f a $i >b && mv b $i; done

Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Mauro Carvalho Chehab 2010-03-11 10:26:46 -03:00
parent 77012fb995
commit 9afec493e2
4 changed files with 768 additions and 768 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
drivers/staging/tm6000/tm6000-alsa.c
View file

@ -100,11 +100,11 @@ static int _tm6000_start_audio_dma(struct snd_tm6000_card *chip)
int val;
/* Enables audio */
val = tm6000_get_reg(core, REQ_07_SET_GET_AVREG, 0xcc, 0x0);
val = tm6000_get_reg(core, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0x0);
val |= 0x20;
tm6000_set_reg(core, REQ_07_SET_GET_AVREG, 0xcc, val);
tm6000_set_reg(core, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
tm6000_set_reg(core, REQ_08_SET_GET_AVREG_BIT, 0x01, 0x80);
tm6000_set_reg(core, TM6010_REQ08_R01_A_INIT, 0x80);
return 0;
}
@ -119,11 +119,11 @@ static int _tm6000_stop_audio_dma(struct snd_tm6000_card *chip)
dprintk(1, "Stopping audio DMA\n");
/* Enables audio */
val = tm6000_get_reg(core, REQ_07_SET_GET_AVREG, 0xcc, 0x0);
val = tm6000_get_reg(core, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0x0);
val &= ~0x20;
tm6000_set_reg(core, REQ_07_SET_GET_AVREG, 0xcc, val);
tm6000_set_reg(core, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
tm6000_set_reg(core, REQ_08_SET_GET_AVREG_BIT, 0x01, 0);
tm6000_set_reg(core, TM6010_REQ08_R01_A_INIT, 0);
return 0;
}

352
drivers/staging/tm6000/tm6000-core.c
View file

@ -143,14 +143,14 @@ void tm6000_set_fourcc_format(struct tm6000_core *dev)
{
if (dev->dev_type == TM6010) {
if (dev->fourcc == V4L2_PIX_FMT_UYVY)
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0xfc);
tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xfc);
else
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0xfd);
tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xfd);
} else {
if (dev->fourcc == V4L2_PIX_FMT_UYVY)
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0xd0);
tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
else
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0x90);
tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0x90);
}
}
@ -160,40 +160,40 @@ int tm6000_init_analog_mode (struct tm6000_core *dev)
int val;
/* Enable video */
val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, 0);
val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
val |= 0x60;
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, val);
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xfe, 0xcf);
tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0xcf);
} else {
/* Enables soft reset */
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x3f, 0x01);
tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
if (dev->scaler) {
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0x20);
tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x20);
} else {
/* Enable Hfilter and disable TS Drop err */
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0x80);
tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x80);
}
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc3, 0x88);
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xda, 0x23);
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd1, 0xc0);
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd2, 0xd8);
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd6, 0x06);
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xdf, 0x1f);
tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x88);
tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23);
tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xc0);
tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xd8);
tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x06);
tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f);
/* AP Software reset */
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xff, 0x08);
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xff, 0x00);
tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
tm6000_set_fourcc_format(dev);
/* Disables soft reset */
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x3f, 0x00);
tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
/* E3: Select input 0 - TV tuner */
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xe3, 0x00);
tm6000_set_reg(dev, TM6010_REQ07_RE3_OUT_SEL1, 0x00);
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60);
/* This controls input */
@ -225,38 +225,38 @@ int tm6000_init_digital_mode (struct tm6000_core *dev)
u8 buf[2];
/* digital init */
val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, 0);
val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
val &= ~0x60;
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, val);
val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0);
tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
val = tm6000_get_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0);
val |= 0x40;
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, val);
tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xfe, 0x28);
tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xfc);
tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0xe6, 0xff);
tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe);
tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, val);
tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0x28);
tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xfc);
tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0xff);
tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe);
tm6000_read_write_usb (dev, 0xc0, 0x0e, 0x00c2, 0x0008, buf, 2);
printk (KERN_INFO "buf %#x %#x \n", buf[0], buf[1]);
} else {
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00ff, 0x08);
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00ff, 0x00);
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x003f, 0x01);
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00df, 0x08);
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e2, 0x0c);
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e8, 0xff);
tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x08);
tm6000_set_reg(dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c);
tm6000_set_reg(dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff);
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0xd8);
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c0, 0x40);
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c1, 0xd0);
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c3, 0x09);
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00da, 0x37);
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d1, 0xd8);
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d2, 0xc0);
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d6, 0x60);
tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x40);
tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x09);
tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x37);
tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xd8);
tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xc0);
tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x60);
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e2, 0x0c);
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e8, 0xff);
tm6000_set_reg(dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c);
tm6000_set_reg(dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff);
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0x08);
msleep(50);
@ -279,153 +279,153 @@ struct reg_init {
/* The meaning of those initializations are unknown */
struct reg_init tm6000_init_tab[] = {
/* REG VALUE */
{ REQ_07_SET_GET_AVREG, 0xdf, 0x1f },
{ REQ_07_SET_GET_AVREG, 0xff, 0x08 },
{ REQ_07_SET_GET_AVREG, 0xff, 0x00 },
{ REQ_07_SET_GET_AVREG, 0xd5, 0x4f },
{ REQ_07_SET_GET_AVREG, 0xda, 0x23 },
{ REQ_07_SET_GET_AVREG, 0xdb, 0x08 },
{ REQ_07_SET_GET_AVREG, 0xe2, 0x00 },
{ REQ_07_SET_GET_AVREG, 0xe3, 0x10 },
{ REQ_07_SET_GET_AVREG, 0xe5, 0x00 },
{ REQ_07_SET_GET_AVREG, 0xe8, 0x00 },
{ TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f },
{ TM6010_REQ07_RFF_SOFT_RESET, 0x08 },
{ TM6010_REQ07_RFF_SOFT_RESET, 0x00 },
{ TM6010_REQ07_RD5_POWERSAVE, 0x4f },
{ TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23 },
{ TM6010_REQ07_RD8_IR_WAKEUP_ADD, 0x08 },
{ TM6010_REQ07_RE2_OUT_SEL2, 0x00 },
{ TM6010_REQ07_RE3_OUT_SEL1, 0x10 },
{ TM6010_REQ07_RE5_REMOTE_WAKEUP, 0x00 },
{ TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0x00 },
{ REQ_07_SET_GET_AVREG, 0xeb, 0x64 }, /* 48000 bits/sample, external input */
{ REQ_07_SET_GET_AVREG, 0xee, 0xc2 },
{ REQ_07_SET_GET_AVREG, 0x3f, 0x01 }, /* Start of soft reset */
{ REQ_07_SET_GET_AVREG, 0x00, 0x00 },
{ REQ_07_SET_GET_AVREG, 0x01, 0x07 },
{ REQ_07_SET_GET_AVREG, 0x02, 0x5f },
{ REQ_07_SET_GET_AVREG, 0x03, 0x00 },
{ REQ_07_SET_GET_AVREG, 0x05, 0x64 },
{ REQ_07_SET_GET_AVREG, 0x07, 0x01 },
{ REQ_07_SET_GET_AVREG, 0x08, 0x82 },
{ REQ_07_SET_GET_AVREG, 0x09, 0x36 },
{ REQ_07_SET_GET_AVREG, 0x0a, 0x50 },
{ REQ_07_SET_GET_AVREG, 0x0c, 0x6a },
{ REQ_07_SET_GET_AVREG, 0x11, 0xc9 },
{ REQ_07_SET_GET_AVREG, 0x12, 0x07 },
{ REQ_07_SET_GET_AVREG, 0x13, 0x3b },
{ REQ_07_SET_GET_AVREG, 0x14, 0x47 },
{ REQ_07_SET_GET_AVREG, 0x15, 0x6f },
{ REQ_07_SET_GET_AVREG, 0x17, 0xcd },
{ REQ_07_SET_GET_AVREG, 0x18, 0x1e },
{ REQ_07_SET_GET_AVREG, 0x19, 0x8b },
{ REQ_07_SET_GET_AVREG, 0x1a, 0xa2 },
{ REQ_07_SET_GET_AVREG, 0x1b, 0xe9 },
{ REQ_07_SET_GET_AVREG, 0x1c, 0x1c },
{ REQ_07_SET_GET_AVREG, 0x1d, 0xcc },
{ REQ_07_SET_GET_AVREG, 0x1e, 0xcc },
{ REQ_07_SET_GET_AVREG, 0x1f, 0xcd },
{ REQ_07_SET_GET_AVREG, 0x20, 0x3c },
{ REQ_07_SET_GET_AVREG, 0x21, 0x3c },
{ REQ_07_SET_GET_AVREG, 0x2d, 0x48 },
{ REQ_07_SET_GET_AVREG, 0x2e, 0x88 },
{ REQ_07_SET_GET_AVREG, 0x30, 0x22 },
{ REQ_07_SET_GET_AVREG, 0x31, 0x61 },
{ REQ_07_SET_GET_AVREG, 0x32, 0x74 },
{ REQ_07_SET_GET_AVREG, 0x33, 0x1c },
{ REQ_07_SET_GET_AVREG, 0x34, 0x74 },
{ REQ_07_SET_GET_AVREG, 0x35, 0x1c },
{ REQ_07_SET_GET_AVREG, 0x36, 0x7a },
{ REQ_07_SET_GET_AVREG, 0x37, 0x26 },
{ REQ_07_SET_GET_AVREG, 0x38, 0x40 },
{ REQ_07_SET_GET_AVREG, 0x39, 0x0a },
{ REQ_07_SET_GET_AVREG, 0x42, 0x55 },
{ REQ_07_SET_GET_AVREG, 0x51, 0x11 },
{ REQ_07_SET_GET_AVREG, 0x55, 0x01 },
{ REQ_07_SET_GET_AVREG, 0x57, 0x02 },
{ REQ_07_SET_GET_AVREG, 0x58, 0x35 },
{ REQ_07_SET_GET_AVREG, 0x59, 0xa0 },
{ REQ_07_SET_GET_AVREG, 0x80, 0x15 },
{ REQ_07_SET_GET_AVREG, 0x82, 0x42 },
{ REQ_07_SET_GET_AVREG, 0xc1, 0xd0 },
{ REQ_07_SET_GET_AVREG, 0xc3, 0x88 },
{ REQ_07_SET_GET_AVREG, 0x3f, 0x00 }, /* End of the soft reset */
{ TM6010_REQ07_R3F_RESET, 0x01 }, /* Start of soft reset */
{ TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
{ TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
{ TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
{ TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
{ TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
{ TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
{ TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
{ TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
{ TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
{ TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
{ TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
{ TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
{ TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
{ TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
{ TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
{ TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
{ TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
{ TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
{ TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
{ TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
{ TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
{ TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
{ TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
{ TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
{ TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
{ TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
{ TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
{ TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
{ TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
{ TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
{ TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
{ TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
{ TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
{ TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
{ TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
{ TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
{ TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
{ TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
{ TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
{ TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
{ TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
{ TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
{ TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
{ TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
{ TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
{ TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
{ TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
{ TM6010_REQ07_RC3_HSTART1, 0x88 },
{ TM6010_REQ07_R3F_RESET, 0x00 }, /* End of the soft reset */
{ REQ_05_SET_GET_USBREG, 0x18, 0x00 },
};
struct reg_init tm6010_init_tab[] = {
{ REQ_07_SET_GET_AVREG, 0xc0, 0x00 },
{ REQ_07_SET_GET_AVREG, 0xc4, 0xa0 },
{ REQ_07_SET_GET_AVREG, 0xc6, 0x40 },
{ REQ_07_SET_GET_AVREG, 0xca, 0x31 },
{ REQ_07_SET_GET_AVREG, 0xcc, 0xe1 },
{ REQ_07_SET_GET_AVREG, 0xe0, 0x03 },
{ REQ_07_SET_GET_AVREG, 0xfe, 0x7f },
{ TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x00 },
{ TM6010_REQ07_RC4_HSTART0, 0xa0 },
{ TM6010_REQ07_RC6_HEND0, 0x40 },
{ TM6010_REQ07_RCA_VEND0, 0x31 },
{ TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0xe1 },
{ TM6010_REQ07_RE0_DVIDEO_SOURCE, 0x03 },
{ TM6010_REQ07_RFE_POWER_DOWN, 0x7f },
{ REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0 },
{ REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4 },
{ REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8 },
{ REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00 },
{ REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2 },
{ REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0 },
{ REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2 },
{ REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60 },
{ REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc },
{ TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0 },
{ TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4 },
{ TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8 },
{ TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00 },
{ TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2 },
{ TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0 },
{ TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2 },
{ TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60 },
{ TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc },
{ REQ_07_SET_GET_AVREG, 0x3f, 0x01 },
{ REQ_07_SET_GET_AVREG, 0x00, 0x00 },
{ REQ_07_SET_GET_AVREG, 0x01, 0x07 },
{ REQ_07_SET_GET_AVREG, 0x02, 0x5f },
{ REQ_07_SET_GET_AVREG, 0x03, 0x00 },
{ REQ_07_SET_GET_AVREG, 0x05, 0x64 },
{ REQ_07_SET_GET_AVREG, 0x07, 0x01 },
{ REQ_07_SET_GET_AVREG, 0x08, 0x82 },
{ REQ_07_SET_GET_AVREG, 0x09, 0x36 },
{ REQ_07_SET_GET_AVREG, 0x0a, 0x50 },
{ REQ_07_SET_GET_AVREG, 0x0c, 0x6a },
{ REQ_07_SET_GET_AVREG, 0x11, 0xc9 },
{ REQ_07_SET_GET_AVREG, 0x12, 0x07 },
{ REQ_07_SET_GET_AVREG, 0x13, 0x3b },
{ REQ_07_SET_GET_AVREG, 0x14, 0x47 },
{ REQ_07_SET_GET_AVREG, 0x15, 0x6f },
{ REQ_07_SET_GET_AVREG, 0x17, 0xcd },
{ REQ_07_SET_GET_AVREG, 0x18, 0x1e },
{ REQ_07_SET_GET_AVREG, 0x19, 0x8b },
{ REQ_07_SET_GET_AVREG, 0x1a, 0xa2 },
{ REQ_07_SET_GET_AVREG, 0x1b, 0xe9 },
{ REQ_07_SET_GET_AVREG, 0x1c, 0x1c },
{ REQ_07_SET_GET_AVREG, 0x1d, 0xcc },
{ REQ_07_SET_GET_AVREG, 0x1e, 0xcc },
{ REQ_07_SET_GET_AVREG, 0x1f, 0xcd },
{ REQ_07_SET_GET_AVREG, 0x20, 0x3c },
{ REQ_07_SET_GET_AVREG, 0x21, 0x3c },
{ REQ_07_SET_GET_AVREG, 0x2d, 0x48 },
{ REQ_07_SET_GET_AVREG, 0x2e, 0x88 },
{ REQ_07_SET_GET_AVREG, 0x30, 0x22 },
{ REQ_07_SET_GET_AVREG, 0x31, 0x61 },
{ REQ_07_SET_GET_AVREG, 0x32, 0x74 },
{ REQ_07_SET_GET_AVREG, 0x33, 0x1c },
{ REQ_07_SET_GET_AVREG, 0x34, 0x74 },
{ REQ_07_SET_GET_AVREG, 0x35, 0x1c },
{ REQ_07_SET_GET_AVREG, 0x36, 0x7a },
{ REQ_07_SET_GET_AVREG, 0x37, 0x26 },
{ REQ_07_SET_GET_AVREG, 0x38, 0x40 },
{ REQ_07_SET_GET_AVREG, 0x39, 0x0a },
{ REQ_07_SET_GET_AVREG, 0x42, 0x55 },
{ REQ_07_SET_GET_AVREG, 0x51, 0x11 },
{ REQ_07_SET_GET_AVREG, 0x55, 0x01 },
{ REQ_07_SET_GET_AVREG, 0x57, 0x02 },
{ REQ_07_SET_GET_AVREG, 0x58, 0x35 },
{ REQ_07_SET_GET_AVREG, 0x59, 0xa0 },
{ REQ_07_SET_GET_AVREG, 0x80, 0x15 },
{ REQ_07_SET_GET_AVREG, 0x82, 0x42 },
{ REQ_07_SET_GET_AVREG, 0xc1, 0xd0 },
{ REQ_07_SET_GET_AVREG, 0xc3, 0x88 },
{ REQ_07_SET_GET_AVREG, 0x3f, 0x00 },
{ TM6010_REQ07_R3F_RESET, 0x01 },
{ TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
{ TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
{ TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
{ TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
{ TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
{ TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
{ TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
{ TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
{ TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
{ TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
{ TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
{ TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
{ TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
{ TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
{ TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
{ TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
{ TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
{ TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
{ TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
{ TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
{ TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
{ TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
{ TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
{ TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
{ TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
{ TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
{ TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
{ TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
{ TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
{ TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
{ TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
{ TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
{ TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
{ TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
{ TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
{ TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
{ TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
{ TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
{ TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
{ TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
{ TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
{ TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
{ TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
{ TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
{ TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
{ TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
{ TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
{ TM6010_REQ07_RC3_HSTART1, 0x88 },
{ TM6010_REQ07_R3F_RESET, 0x00 },
{ REQ_05_SET_GET_USBREG, 0x18, 0x00 },
{ REQ_07_SET_GET_AVREG, 0xdc, 0xaa },
{ REQ_07_SET_GET_AVREG, 0xdd, 0x30 },
{ REQ_07_SET_GET_AVREG, 0xde, 0x20 },
{ REQ_07_SET_GET_AVREG, 0xdf, 0xd0 },
{ TM6010_REQ07_RD8_IR_LEADER1, 0xaa },
{ TM6010_REQ07_RD8_IR_LEADER0, 0x30 },
{ TM6010_REQ07_RD8_IR_PULSE_CNT1, 0x20 },
{ TM6010_REQ07_RD8_IR_PULSE_CNT0, 0xd0 },
{ REQ_04_EN_DISABLE_MCU_INT, 0x02, 0x00 },
{ REQ_07_SET_GET_AVREG, 0xd8, 0x2f },
{ TM6010_REQ07_RD8_IR, 0x2f },
/* set remote wakeup key:any key wakeup */
{ REQ_07_SET_GET_AVREG, 0xe5, 0xfe },
{ REQ_07_SET_GET_AVREG, 0xda, 0xff },
{ TM6010_REQ07_RE5_REMOTE_WAKEUP, 0xfe },
{ TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0xff },
};
int tm6000_init (struct tm6000_core *dev)

1156
drivers/staging/tm6000/tm6000-stds.c
View file

File diff suppressed because it is too large Load diff

16
drivers/staging/tm6000/tm6000-video.c
View file

@ -1186,16 +1186,16 @@ static int vidioc_g_ctrl (struct file *file, void *priv,
/* FIXME: Probably, those won't work! Maybe we need shadow regs */
switch (ctrl->id) {
case V4L2_CID_CONTRAST:
val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0x08, 0);
val = tm6000_get_reg(dev, TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0);
break;
case V4L2_CID_BRIGHTNESS:
val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0x09, 0);
val = tm6000_get_reg(dev, TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0);
return 0;
case V4L2_CID_SATURATION:
val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0x0a, 0);
val = tm6000_get_reg(dev, TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0);
return 0;
case V4L2_CID_HUE:
val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0x0b, 0);
val = tm6000_get_reg(dev, TM6010_REQ07_R0B_CHROMA_HUE_PHASE_ADJ, 0);
return 0;
default:
return -EINVAL;
@ -1217,16 +1217,16 @@ static int vidioc_s_ctrl (struct file *file, void *priv,
switch (ctrl->id) {
case V4L2_CID_CONTRAST:
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x08, val);
tm6000_set_reg(dev, TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, val);
return 0;
case V4L2_CID_BRIGHTNESS:
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x09, val);
tm6000_set_reg(dev, TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, val);
return 0;
case V4L2_CID_SATURATION:
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x0a, val);
tm6000_set_reg(dev, TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, val);
return 0;
case V4L2_CID_HUE:
tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x0b, val);
tm6000_set_reg(dev, TM6010_REQ07_R0B_CHROMA_HUE_PHASE_ADJ, val);
return 0;
}
return -EINVAL;