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powerpc/85xx: mpc8548cds - Add FPGA node to dts 

Remove FPGA(CADMUS) macros in code. Move it to dts.

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
chenhui zhao 2012-03-06 17:06:42 +08:00 committed by Kumar Gala
parent 96939e79b0
commit 992608ff56
2 changed files with 41 additions and 17 deletions
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8
arch/powerpc/boot/dts/mpc8548cds.dts
View File

@ -35,7 +35,8 @@
lbc: localbus@e0005000 {
reg = <0 0xe0005000 0 0x1000>;
ranges = <0x0 0x0 0x0 0xff000000 0x01000000>;
ranges = <0x0 0x0 0x0 0xff000000 0x01000000
0x1 0x0 0x0 0xf8004000 0x00001000>;
nor@0,0 {
#address-cells = <1>;
@ -72,6 +73,11 @@
read-only;
};
};
board-control@1,0 {
compatible = "fsl,mpc8548cds-fpga";
reg = <0x1 0x0 0x1000>;
};
};
soc: soc8548@e0000000 {

50
arch/powerpc/platforms/85xx/mpc85xx_cds.c
View File

@ -48,17 +48,24 @@
#include "mpc85xx.h"
/* CADMUS info */
/* xxx - galak, move into device tree */
#define CADMUS_BASE (0xf8004000)
#define CADMUS_SIZE (256)
#define CM_VER (0)
#define CM_CSR (1)
#define CM_RST (2)
/*
* The CDS board contains an FPGA/CPLD called "Cadmus", which collects
* various logic and performs system control functions.
* Here is the FPGA/CPLD register map.
*/
struct cadmus_reg {
u8 cm_ver; /* Board version */
u8 cm_csr; /* General control/status */
u8 cm_rst; /* Reset control */
u8 cm_hsclk; /* High speed clock */
u8 cm_hsxclk; /* High speed clock extended */
u8 cm_led; /* LED data */
u8 cm_pci; /* PCI control/status */
u8 cm_dma; /* DMA control */
u8 res[248]; /* Total 256 bytes */
};
static int cds_pci_slot = 2;
static volatile u8 *cadmus;
static struct cadmus_reg *cadmus;
#ifdef CONFIG_PCI
@ -275,20 +282,30 @@ machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);
*/
static void __init mpc85xx_cds_setup_arch(void)
{
#ifdef CONFIG_PCI
struct device_node *np;
#endif
int cds_pci_slot;
if (ppc_md.progress)
ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
np = of_find_compatible_node(NULL, NULL, "fsl,mpc8548cds-fpga");
if (!np) {
pr_err("Could not find FPGA node.\n");
return;
}
cadmus = of_iomap(np, 0);
of_node_put(np);
if (!cadmus) {
pr_err("Fail to map FPGA area.\n");
return;
}
if (ppc_md.progress) {
char buf[40];
cds_pci_slot = ((in_8(&cadmus->cm_csr) >> 6) & 0x3) + 1;
snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
cadmus[CM_VER], cds_pci_slot);
in_8(&cadmus->cm_ver), cds_pci_slot);
ppc_md.progress(buf, 0);
}
@ -318,7 +335,8 @@ static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
svid = mfspr(SPRN_SVR);
seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n",
in_8(&cadmus->cm_ver));
seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
seq_printf(m, "SVR\t\t: 0x%x\n", svid);