ARM: arm-soc fixes for 3.8-rc
People are back from the holiday breaks, and it shows. Here are a bunch of
fixes for a number of platforms:
- A couple of small fixes for Nomadik
- A larger set of changes for kirkwood/mvebu
- uart driver selection, dt clocks, gpio-poweroff fixups,
a few __init annotation fixes and some error handling improvement
in their xor dma driver.
- i.MX had a couple of minor fixes (and a critical one for flexcan2
clock setup)
- MXS has a small board fix and a framebuffer bugfix
- A set of fixes for Samsung Exynos, fixing default bootargs and some
Exynos5440 clock issues
- A set of OMAP changes including PM fixes and a few sparse warning
fixups
All in all a bit more positive code delta than we'd ideally want to see
here, mostly from the OMAP PM changes, but nothing overly crazy.
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Merge tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"People are back from the holiday breaks, and it shows. Here are a
bunch of fixes for a number of platforms:
- A couple of small fixes for Nomadik
- A larger set of changes for kirkwood/mvebu
- uart driver selection, dt clocks, gpio-poweroff fixups, a few
__init annotation fixes and some error handling improvement in
their xor dma driver.
- i.MX had a couple of minor fixes (and a critical one for flexcan2
clock setup)
- MXS has a small board fix and a framebuffer bugfix
- A set of fixes for Samsung Exynos, fixing default bootargs and some
Exynos5440 clock issues
- A set of OMAP changes including PM fixes and a few sparse warning
fixups
All in all a bit more positive code delta than we'd ideally want to
see here, mostly from the OMAP PM changes, but nothing overly crazy."
* tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (44 commits)
ARM: clps711x: Fix bad merge of clockevents setup
ARM: highbank: save and restore L2 cache and GIC on suspend
ARM: highbank: add a power request clear
ARM: highbank: fix secondary boot and hotplug
ARM: highbank: fix typos with hignbank in power request functions
ARM: dts: fix highbank cpu mpidr values
ARM: dts: add device_type prop to cpu nodes on Calxeda platforms
ARM: mx5: Fix MX53 flexcan2 clock
ARM: OMAP2+: am33xx-hwmod: Fix wrongly terminated am33xx_usbss_mpu_irqs array
pinctrl: mvebu: make pdma clock on dove mandatory
ARM: Dove: Add pinctrl clock to DT
dma: mv_xor: fix error handling for clocks
dma: mv_xor: fix error handling of mv_xor_channel_add()
arm: mvebu: Add missing ; for cpu node.
arm: mvebu: Armada XP MV78230 has only three Ethernet interfaces
arm: mvebu: Armada XP MV78230 has two cores, not one
clk: mvebu: Remove inappropriate __init tagging
ARM: Kirkwood: Use fixed-regulator instead of board gpio call
ARM: Kirkwood: Fix missing sdio clock
ARM: Kirkwood: Switch TWSI1 of 88f6282 to DT clock providers
...
This commit is contained in:
Linus Torvalds
commit
974b33586b
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|
@ -60,11 +60,6 @@ clks: clkctrl@80040000 {
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compatible = "fsl,imx23-clkctrl";
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reg = <0x80040000 0x2000>;
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#clock-cells = <1>;
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clock-output-names =
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...
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"uart", /* 32 */
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...
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"end_of_list";
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};
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auart0: serial@8006c000 {
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@ -146,10 +146,6 @@ clks: ccm@53f80000 {
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compatible = "fsl,imx25-ccm";
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reg = <0x53f80000 0x4000>;
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interrupts = <31>;
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clock-output-names = ...
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"uart_ipg",
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"uart_serial",
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...;
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};
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uart1: serial@43f90000 {
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@ -83,11 +83,6 @@ clks: clkctrl@80040000 {
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compatible = "fsl,imx28-clkctrl";
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reg = <0x80040000 0x2000>;
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#clock-cells = <1>;
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clock-output-names =
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...
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"uart", /* 45 */
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...
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"end_of_list";
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};
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auart0: serial@8006a000 {
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@ -211,10 +211,6 @@ clks: ccm@020c4000 {
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reg = <0x020c4000 0x4000>;
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interrupts = <0 87 0x04 0 88 0x04>;
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#clock-cells = <1>;
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clock-output-names = ...
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"uart_ipg",
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"uart_serial",
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...;
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};
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uart1: serial@02020000 {
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@ -1,4 +1,19 @@
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GPIO line that should be set high/low to power off a device
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Driver a GPIO line that can be used to turn the power off.
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The driver supports both level triggered and edge triggered power off.
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At driver load time, the driver will request the given gpio line and
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install a pm_power_off handler. If the optional properties 'input' is
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not found, the GPIO line will be driven in the inactive
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state. Otherwise its configured as an input.
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When the pm_power_off is called, the gpio is configured as an output,
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and drive active, so triggering a level triggered power off
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condition. This will also cause an inactive->active edge condition, so
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triggering positive edge triggered power off. After a delay of 100ms,
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the GPIO is set to inactive, thus causing an active->inactive edge,
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triggering negative edge triggered power off. After another 100ms
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delay the GPIO is driver active again. If the power is still on and
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the CPU still running after a 3000ms delay, a WARN_ON(1) is emitted.
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Required properties:
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- compatible : should be "gpio-poweroff".
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@ -13,10 +28,9 @@ Optional properties:
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property is not specified, the GPIO is initialized as an output in its
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inactive state.
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Examples:
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gpio-poweroff {
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compatible = "gpio-poweroff";
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gpios = <&gpio 4 0>; /* GPIO 4 Active Low */
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gpios = <&gpio 4 0>;
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};
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@ -371,7 +371,6 @@ config ARCH_CNS3XXX
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config ARCH_CLPS711X
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bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
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select ARCH_REQUIRE_GPIOLIB
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select ARCH_USES_GETTIMEOFFSET
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select AUTO_ZRELADDR
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select CLKDEV_LOOKUP
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select COMMON_CLK
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@ -50,17 +50,19 @@
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ranges;
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serial@d0012000 {
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compatible = "ns16550";
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compatible = "snps,dw-apb-uart";
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reg = <0xd0012000 0x100>;
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reg-shift = <2>;
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interrupts = <41>;
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reg-io-width = <4>;
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status = "disabled";
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};
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serial@d0012100 {
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compatible = "ns16550";
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compatible = "snps,dw-apb-uart";
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reg = <0xd0012100 0x100>;
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reg-shift = <2>;
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interrupts = <42>;
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reg-io-width = <4>;
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status = "disabled";
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};
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@ -34,7 +34,14 @@
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reg = <0>;
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clocks = <&cpuclk 0>;
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};
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}
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cpu@1 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <1>;
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clocks = <&cpuclk 1>;
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};
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};
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soc {
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pinctrl {
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@ -85,5 +85,13 @@
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#interrupts-cells = <2>;
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interrupts = <24>;
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};
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ethernet@d0034000 {
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compatible = "marvell,armada-370-neta";
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reg = <0xd0034000 0x2500>;
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interrupts = <14>;
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clocks = <&gateclk 1>;
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status = "disabled";
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};
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};
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};
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@ -100,5 +100,13 @@
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#interrupts-cells = <2>;
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interrupts = <24>;
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};
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ethernet@d0034000 {
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compatible = "marvell,armada-370-neta";
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reg = <0xd0034000 0x2500>;
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interrupts = <14>;
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clocks = <&gateclk 1>;
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status = "disabled";
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};
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};
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};
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@ -42,17 +42,19 @@
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soc {
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serial@d0012200 {
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compatible = "ns16550";
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compatible = "snps,dw-apb-uart";
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reg = <0xd0012200 0x100>;
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reg-shift = <2>;
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interrupts = <43>;
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reg-io-width = <4>;
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status = "disabled";
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};
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serial@d0012300 {
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compatible = "ns16550";
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compatible = "snps,dw-apb-uart";
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reg = <0xd0012300 0x100>;
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reg-shift = <2>;
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interrupts = <44>;
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reg-io-width = <4>;
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status = "disabled";
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};
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@ -93,14 +95,6 @@
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status = "disabled";
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};
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ethernet@d0034000 {
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compatible = "marvell,armada-370-neta";
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reg = <0xd0034000 0x2500>;
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interrupts = <14>;
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clocks = <&gateclk 1>;
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status = "disabled";
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};
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xor@d0060900 {
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compatible = "marvell,orion-xor";
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reg = <0xd0060900 0x100
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@ -117,6 +117,7 @@
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pinctrl: pinctrl@d0200 {
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compatible = "marvell,dove-pinctrl";
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reg = <0xd0200 0x10>;
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clocks = <&gate_clk 22>;
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};
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spi0: spi@10600 {
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@ -32,6 +32,7 @@
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cpu@0 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <0>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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@ -39,6 +40,7 @@
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cpu@1 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <1>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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@ -46,6 +48,7 @@
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cpu@2 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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@ -53,6 +56,7 @@
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cpu@3 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <3>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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|
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@ -26,7 +26,7 @@
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};
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chosen {
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bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
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bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
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};
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sdhci@12530000 {
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|
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@ -574,7 +574,7 @@
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hdmi {
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compatible = "samsung,exynos5-hdmi";
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reg = <0x14530000 0x100000>;
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reg = <0x14530000 0x70000>;
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interrupts = <0 95 0>;
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};
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|
|
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@ -21,7 +21,7 @@
|
|||
};
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chosen {
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bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC2,115200 init=/linuxrc";
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bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC0,115200 init=/linuxrc";
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};
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spi {
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|
|
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@ -30,33 +30,37 @@
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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cpu@900 {
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compatible = "arm,cortex-a9";
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reg = <0>;
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device_type = "cpu";
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reg = <0x900>;
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next-level-cache = <&L2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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};
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|
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cpu@1 {
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cpu@901 {
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compatible = "arm,cortex-a9";
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reg = <1>;
|
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device_type = "cpu";
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reg = <0x901>;
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next-level-cache = <&L2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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};
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|
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cpu@2 {
|
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cpu@902 {
|
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compatible = "arm,cortex-a9";
|
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reg = <2>;
|
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device_type = "cpu";
|
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reg = <0x902>;
|
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next-level-cache = <&L2>;
|
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clocks = <&a9pll>;
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clock-names = "cpu";
|
||||
};
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|
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cpu@3 {
|
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cpu@903 {
|
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compatible = "arm,cortex-a9";
|
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reg = <3>;
|
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device_type = "cpu";
|
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reg = <0x903>;
|
||||
next-level-cache = <&L2>;
|
||||
clocks = <&a9pll>;
|
||||
clock-names = "cpu";
|
||||
|
|
|
|||
|
|
@ -39,17 +39,17 @@
|
|||
hog_pins_a: hog@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
|
||||
0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
led_pin_gpio0_17: led_gpio0_17@0 {
|
||||
led_pin_gpio2_1: led_gpio2_1@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
|
||||
0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
|
|
@ -110,7 +110,7 @@
|
|||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_pin_gpio0_17>;
|
||||
pinctrl-0 = <&led_pin_gpio2_1>;
|
||||
|
||||
user {
|
||||
label = "green";
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
|
||||
/ {
|
||||
model = "Buglabs i.MX31 Bug 1.x";
|
||||
compatible = "fsl,imx31-bug", "fsl,imx31";
|
||||
compatible = "buglabs,imx31-bug", "fsl,imx31";
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x8000000>; /* 128M */
|
||||
|
|
|
|||
|
|
@ -492,7 +492,7 @@
|
|||
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x53fcc000 0x4000>;
|
||||
interrupts = <83>;
|
||||
clocks = <&clks 158>, <&clks 157>;
|
||||
clocks = <&clks 87>, <&clks 86>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -39,6 +39,7 @@
|
|||
#size-cells = <0>;
|
||||
interrupts = <32>;
|
||||
clock-frequency = <100000>;
|
||||
clocks = <&gate_clk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -82,4 +82,21 @@
|
|||
gpios = <&gpio1 16 1>;
|
||||
};
|
||||
};
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sata0_power: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "SATA0 Power";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
gpio = <&gpio1 4 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -144,6 +144,7 @@
|
|||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x50000 0x1000>;
|
||||
interrupts = <19>;
|
||||
clocks = <&gate_clk 3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -33,9 +33,7 @@ CONFIG_MVNETA=y
|
|||
CONFIG_MARVELL_PHY=y
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_MV64XXX=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
|
|
|
|||
|
|
@ -74,6 +74,8 @@ config SOC_EXYNOS5440
|
|||
depends on ARCH_EXYNOS5
|
||||
select ARM_ARCH_TIMER
|
||||
select AUTO_ZRELADDR
|
||||
select PINCTRL
|
||||
select PINCTRL_EXYNOS5440
|
||||
help
|
||||
Enable EXYNOS5440 SoC support
|
||||
|
||||
|
|
|
|||
|
|
@ -424,11 +424,18 @@ static void __init exynos5_init_clocks(int xtal)
|
|||
{
|
||||
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
|
||||
|
||||
/* EXYNOS5440 can support only common clock framework */
|
||||
|
||||
if (soc_is_exynos5440())
|
||||
return;
|
||||
|
||||
#ifdef CONFIG_SOC_EXYNOS5250
|
||||
s3c24xx_register_baseclocks(xtal);
|
||||
s5p_register_clocks(xtal);
|
||||
|
||||
exynos5_register_clocks();
|
||||
exynos5_setup_clocks();
|
||||
#endif
|
||||
}
|
||||
|
||||
#define COMBINER_ENABLE_SET 0x0
|
||||
|
|
|
|||
|
|
@ -135,7 +135,7 @@ static struct sys_timer highbank_timer = {
|
|||
|
||||
static void highbank_power_off(void)
|
||||
{
|
||||
hignbank_set_pwr_shutdown();
|
||||
highbank_set_pwr_shutdown();
|
||||
|
||||
while (1)
|
||||
cpu_do_idle();
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ void __ref highbank_cpu_die(unsigned int cpu)
|
|||
{
|
||||
flush_cache_all();
|
||||
|
||||
highbank_set_cpu_jump(cpu, secondary_startup);
|
||||
highbank_set_cpu_jump(cpu, phys_to_virt(0));
|
||||
highbank_set_core_pwr();
|
||||
|
||||
cpu_do_idle();
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ static void __cpuinit highbank_secondary_init(unsigned int cpu)
|
|||
|
||||
static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
highbank_set_cpu_jump(cpu, secondary_startup);
|
||||
gic_raise_softirq(cpumask_of(cpu), 0);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -61,19 +62,8 @@ static void __init highbank_smp_init_cpus(void)
|
|||
|
||||
static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (scu_base_addr)
|
||||
scu_enable(scu_base_addr);
|
||||
|
||||
/*
|
||||
* Write the address of secondary startup into the jump table
|
||||
* The cores are in wfi and wait until they receive a soft interrupt
|
||||
* and a non-zero value to jump to. Then the secondary CPU branches
|
||||
* to this address.
|
||||
*/
|
||||
for (i = 1; i < max_cpus; i++)
|
||||
highbank_set_cpu_jump(i, secondary_startup);
|
||||
}
|
||||
|
||||
struct smp_operations highbank_smp_ops __initdata = {
|
||||
|
|
|
|||
|
|
@ -14,10 +14,12 @@
|
|||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <linux/cpu_pm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/suspend.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/proc-fns.h>
|
||||
#include <asm/suspend.h>
|
||||
|
||||
|
|
@ -26,16 +28,31 @@
|
|||
|
||||
static int highbank_suspend_finish(unsigned long val)
|
||||
{
|
||||
outer_flush_all();
|
||||
outer_disable();
|
||||
|
||||
highbank_set_pwr_suspend();
|
||||
|
||||
cpu_do_idle();
|
||||
|
||||
highbank_clear_pwr_request();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int highbank_pm_enter(suspend_state_t state)
|
||||
{
|
||||
hignbank_set_pwr_suspend();
|
||||
cpu_pm_enter();
|
||||
cpu_cluster_pm_enter();
|
||||
|
||||
highbank_set_cpu_jump(0, cpu_resume);
|
||||
cpu_suspend(0, highbank_suspend_finish);
|
||||
|
||||
cpu_cluster_pm_exit();
|
||||
cpu_pm_exit();
|
||||
|
||||
highbank_smc1(0x102, 0x1);
|
||||
if (scu_base_addr)
|
||||
scu_enable(scu_base_addr);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -44,28 +44,43 @@ static inline void highbank_set_core_pwr(void)
|
|||
writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
|
||||
}
|
||||
|
||||
static inline void hignbank_set_pwr_suspend(void)
|
||||
static inline void highbank_clear_core_pwr(void)
|
||||
{
|
||||
int cpu = cpu_logical_map(smp_processor_id());
|
||||
if (scu_base_addr)
|
||||
scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
|
||||
else
|
||||
writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu));
|
||||
}
|
||||
|
||||
static inline void highbank_set_pwr_suspend(void)
|
||||
{
|
||||
writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
|
||||
highbank_set_core_pwr();
|
||||
}
|
||||
|
||||
static inline void hignbank_set_pwr_shutdown(void)
|
||||
static inline void highbank_set_pwr_shutdown(void)
|
||||
{
|
||||
writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
|
||||
highbank_set_core_pwr();
|
||||
}
|
||||
|
||||
static inline void hignbank_set_pwr_soft_reset(void)
|
||||
static inline void highbank_set_pwr_soft_reset(void)
|
||||
{
|
||||
writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
|
||||
highbank_set_core_pwr();
|
||||
}
|
||||
|
||||
static inline void hignbank_set_pwr_hard_reset(void)
|
||||
static inline void highbank_set_pwr_hard_reset(void)
|
||||
{
|
||||
writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
|
||||
highbank_set_core_pwr();
|
||||
}
|
||||
|
||||
static inline void highbank_clear_pwr_request(void)
|
||||
{
|
||||
writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ);
|
||||
highbank_clear_core_pwr();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -22,9 +22,9 @@
|
|||
void highbank_restart(char mode, const char *cmd)
|
||||
{
|
||||
if (mode == 'h')
|
||||
hignbank_set_pwr_hard_reset();
|
||||
highbank_set_pwr_hard_reset();
|
||||
else
|
||||
hignbank_set_pwr_soft_reset();
|
||||
highbank_set_pwr_soft_reset();
|
||||
|
||||
while (1)
|
||||
cpu_do_idle();
|
||||
|
|
|
|||
|
|
@ -67,6 +67,10 @@ static void __init kirkwood_legacy_clk_init(void)
|
|||
orion_clkdev_add(NULL, "mv643xx_eth_port.1",
|
||||
of_clk_get_from_provider(&clkspec));
|
||||
|
||||
clkspec.args[0] = CGC_BIT_SDIO;
|
||||
orion_clkdev_add(NULL, "mvsdio",
|
||||
of_clk_get_from_provider(&clkspec));
|
||||
|
||||
}
|
||||
|
||||
static void __init kirkwood_of_clk_init(void)
|
||||
|
|
|
|||
|
|
@ -64,8 +64,6 @@ static unsigned int topkick_mpp_config[] __initdata = {
|
|||
0
|
||||
};
|
||||
|
||||
#define TOPKICK_SATA0_PWR_ENABLE 36
|
||||
|
||||
void __init usi_topkick_init(void)
|
||||
{
|
||||
/*
|
||||
|
|
@ -73,8 +71,6 @@ void __init usi_topkick_init(void)
|
|||
*/
|
||||
kirkwood_mpp_conf(topkick_mpp_config);
|
||||
|
||||
/* SATA0 power enable */
|
||||
gpio_set_value(TOPKICK_SATA0_PWR_ENABLE, 1);
|
||||
|
||||
kirkwood_ge00_init(&topkick_ge00_data);
|
||||
kirkwood_sdio_init(&topkick_mvsdio_data);
|
||||
|
|
|
|||
|
|
@ -27,7 +27,6 @@
|
|||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/platform_data/pinctrl-nomadik.h>
|
||||
#include <linux/platform_data/clocksource-nomadik-mtu.h>
|
||||
#include <linux/platform_data/mtd-nomadik-nand.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
|
|
|||
|
|
@ -22,49 +22,49 @@
|
|||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#define IRQ_VIC_START 1 /* first VIC interrupt is 1 */
|
||||
#define IRQ_VIC_START 32 /* first VIC interrupt is 1 */
|
||||
|
||||
/*
|
||||
* Interrupt numbers generic for all Nomadik Chip cuts
|
||||
*/
|
||||
#define IRQ_WATCHDOG 1
|
||||
#define IRQ_SOFTINT 2
|
||||
#define IRQ_CRYPTO 3
|
||||
#define IRQ_OWM 4
|
||||
#define IRQ_MTU0 5
|
||||
#define IRQ_MTU1 6
|
||||
#define IRQ_GPIO0 7
|
||||
#define IRQ_GPIO1 8
|
||||
#define IRQ_GPIO2 9
|
||||
#define IRQ_GPIO3 10
|
||||
#define IRQ_RTC_RTT 11
|
||||
#define IRQ_SSP 12
|
||||
#define IRQ_UART0 13
|
||||
#define IRQ_DMA1 14
|
||||
#define IRQ_CLCD_MDIF 15
|
||||
#define IRQ_DMA0 16
|
||||
#define IRQ_PWRFAIL 17
|
||||
#define IRQ_UART1 18
|
||||
#define IRQ_FIRDA 19
|
||||
#define IRQ_MSP0 20
|
||||
#define IRQ_I2C0 21
|
||||
#define IRQ_I2C1 22
|
||||
#define IRQ_SDMMC 23
|
||||
#define IRQ_USBOTG 24
|
||||
#define IRQ_SVA_IT0 25
|
||||
#define IRQ_SVA_IT1 26
|
||||
#define IRQ_SAA_IT0 27
|
||||
#define IRQ_SAA_IT1 28
|
||||
#define IRQ_UART2 29
|
||||
#define IRQ_MSP2 30
|
||||
#define IRQ_L2CC 49
|
||||
#define IRQ_HPI 50
|
||||
#define IRQ_SKE 51
|
||||
#define IRQ_KP 52
|
||||
#define IRQ_MEMST 55
|
||||
#define IRQ_SGA_IT 59
|
||||
#define IRQ_USBM 61
|
||||
#define IRQ_MSP1 63
|
||||
#define IRQ_WATCHDOG (IRQ_VIC_START+0)
|
||||
#define IRQ_SOFTINT (IRQ_VIC_START+1)
|
||||
#define IRQ_CRYPTO (IRQ_VIC_START+2)
|
||||
#define IRQ_OWM (IRQ_VIC_START+3)
|
||||
#define IRQ_MTU0 (IRQ_VIC_START+4)
|
||||
#define IRQ_MTU1 (IRQ_VIC_START+5)
|
||||
#define IRQ_GPIO0 (IRQ_VIC_START+6)
|
||||
#define IRQ_GPIO1 (IRQ_VIC_START+7)
|
||||
#define IRQ_GPIO2 (IRQ_VIC_START+8)
|
||||
#define IRQ_GPIO3 (IRQ_VIC_START+9)
|
||||
#define IRQ_RTC_RTT (IRQ_VIC_START+10)
|
||||
#define IRQ_SSP (IRQ_VIC_START+11)
|
||||
#define IRQ_UART0 (IRQ_VIC_START+12)
|
||||
#define IRQ_DMA1 (IRQ_VIC_START+13)
|
||||
#define IRQ_CLCD_MDIF (IRQ_VIC_START+14)
|
||||
#define IRQ_DMA0 (IRQ_VIC_START+15)
|
||||
#define IRQ_PWRFAIL (IRQ_VIC_START+16)
|
||||
#define IRQ_UART1 (IRQ_VIC_START+17)
|
||||
#define IRQ_FIRDA (IRQ_VIC_START+18)
|
||||
#define IRQ_MSP0 (IRQ_VIC_START+19)
|
||||
#define IRQ_I2C0 (IRQ_VIC_START+20)
|
||||
#define IRQ_I2C1 (IRQ_VIC_START+21)
|
||||
#define IRQ_SDMMC (IRQ_VIC_START+22)
|
||||
#define IRQ_USBOTG (IRQ_VIC_START+23)
|
||||
#define IRQ_SVA_IT0 (IRQ_VIC_START+24)
|
||||
#define IRQ_SVA_IT1 (IRQ_VIC_START+25)
|
||||
#define IRQ_SAA_IT0 (IRQ_VIC_START+26)
|
||||
#define IRQ_SAA_IT1 (IRQ_VIC_START+27)
|
||||
#define IRQ_UART2 (IRQ_VIC_START+28)
|
||||
#define IRQ_MSP2 (IRQ_VIC_START+29)
|
||||
#define IRQ_L2CC (IRQ_VIC_START+30)
|
||||
#define IRQ_HPI (IRQ_VIC_START+31)
|
||||
#define IRQ_SKE (IRQ_VIC_START+32)
|
||||
#define IRQ_KP (IRQ_VIC_START+33)
|
||||
#define IRQ_MEMST (IRQ_VIC_START+34)
|
||||
#define IRQ_SGA_IT (IRQ_VIC_START+35)
|
||||
#define IRQ_USBM (IRQ_VIC_START+36)
|
||||
#define IRQ_MSP1 (IRQ_VIC_START+37)
|
||||
|
||||
#define NOMADIK_GPIO_OFFSET (IRQ_VIC_START+64)
|
||||
|
||||
|
|
|
|||
|
|
@ -160,7 +160,7 @@ static struct omap_lcd_config ams_delta_lcd_config __initdata = {
|
|||
.ctrl_name = "internal",
|
||||
};
|
||||
|
||||
static struct omap_usb_config ams_delta_usb_config = {
|
||||
static struct omap_usb_config ams_delta_usb_config __initdata = {
|
||||
.register_host = 1,
|
||||
.hmc_mode = 16,
|
||||
.pins[0] = 2,
|
||||
|
|
|
|||
|
|
@ -629,8 +629,14 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config)
|
|||
static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
|
||||
#endif
|
||||
|
||||
void __init omap1_usb_init(struct omap_usb_config *pdata)
|
||||
void __init omap1_usb_init(struct omap_usb_config *_pdata)
|
||||
{
|
||||
struct omap_usb_config *pdata;
|
||||
|
||||
pdata = kmemdup(_pdata, sizeof(*pdata), GFP_KERNEL);
|
||||
if (!pdata)
|
||||
return;
|
||||
|
||||
pdata->usb0_init = omap1_usb0_init;
|
||||
pdata->usb1_init = omap1_usb1_init;
|
||||
pdata->usb2_init = omap1_usb2_init;
|
||||
|
|
|
|||
|
|
@ -1167,6 +1167,8 @@ static const struct clk_ops emu_src_ck_ops = {
|
|||
.recalc_rate = &omap2_clksel_recalc,
|
||||
.get_parent = &omap2_clksel_find_parent_index,
|
||||
.set_parent = &omap2_clksel_set_parent,
|
||||
.enable = &omap2_clkops_enable_clkdm,
|
||||
.disable = &omap2_clkops_disable_clkdm,
|
||||
};
|
||||
|
||||
static struct clk emu_src_ck;
|
||||
|
|
|
|||
|
|
@ -2070,7 +2070,7 @@ static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
|
|||
{ .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
|
||||
{ .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
|
||||
{ .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
|
||||
{ .irq = -1 + OMAP_INTC_START, },
|
||||
{ .irq = -1, },
|
||||
};
|
||||
|
||||
static struct omap_hwmod am33xx_usbss_hwmod = {
|
||||
|
|
@ -2515,7 +2515,7 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
|
|||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
|
||||
static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x4A101000,
|
||||
.pa_end = 0x4A101000 + SZ_256 - 1,
|
||||
|
|
@ -2523,7 +2523,7 @@ struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
|
|||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
|
||||
static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
|
||||
.master = &am33xx_cpgmac0_hwmod,
|
||||
.slave = &am33xx_mdio_hwmod,
|
||||
.addr = am33xx_mdio_addr_space,
|
||||
|
|
|
|||
|
|
@ -27,6 +27,14 @@
|
|||
#include "cm2xxx_3xxx.h"
|
||||
#include "prm-regbits-24xx.h"
|
||||
|
||||
/*
|
||||
* OMAP24xx PM_PWSTCTRL_*.POWERSTATE and PM_PWSTST_*.LASTSTATEENTERED bits -
|
||||
* these are reversed from the bits used on OMAP3+
|
||||
*/
|
||||
#define OMAP24XX_PWRDM_POWER_ON 0x0
|
||||
#define OMAP24XX_PWRDM_POWER_RET 0x1
|
||||
#define OMAP24XX_PWRDM_POWER_OFF 0x3
|
||||
|
||||
/*
|
||||
* omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP
|
||||
* hardware register (which are specific to the OMAP2xxx SoCs) to
|
||||
|
|
@ -67,6 +75,34 @@ static u32 omap2xxx_prm_read_reset_sources(void)
|
|||
return r;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap2xxx_pwrst_to_common_pwrst - convert OMAP2xxx pwrst to common pwrst
|
||||
* @omap2xxx_pwrst: OMAP2xxx hardware power state to convert
|
||||
*
|
||||
* Return the common power state bits corresponding to the OMAP2xxx
|
||||
* hardware power state bits @omap2xxx_pwrst, or -EINVAL upon error.
|
||||
*/
|
||||
static int omap2xxx_pwrst_to_common_pwrst(u8 omap2xxx_pwrst)
|
||||
{
|
||||
u8 pwrst;
|
||||
|
||||
switch (omap2xxx_pwrst) {
|
||||
case OMAP24XX_PWRDM_POWER_OFF:
|
||||
pwrst = PWRDM_POWER_OFF;
|
||||
break;
|
||||
case OMAP24XX_PWRDM_POWER_RET:
|
||||
pwrst = PWRDM_POWER_RET;
|
||||
break;
|
||||
case OMAP24XX_PWRDM_POWER_ON:
|
||||
pwrst = PWRDM_POWER_ON;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return pwrst;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC
|
||||
*
|
||||
|
|
@ -97,10 +133,56 @@ int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int omap2xxx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
|
||||
{
|
||||
u8 omap24xx_pwrst;
|
||||
|
||||
switch (pwrst) {
|
||||
case PWRDM_POWER_OFF:
|
||||
omap24xx_pwrst = OMAP24XX_PWRDM_POWER_OFF;
|
||||
break;
|
||||
case PWRDM_POWER_RET:
|
||||
omap24xx_pwrst = OMAP24XX_PWRDM_POWER_RET;
|
||||
break;
|
||||
case PWRDM_POWER_ON:
|
||||
omap24xx_pwrst = OMAP24XX_PWRDM_POWER_ON;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
|
||||
(omap24xx_pwrst << OMAP_POWERSTATE_SHIFT),
|
||||
pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int omap2xxx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
|
||||
{
|
||||
u8 omap2xxx_pwrst;
|
||||
|
||||
omap2xxx_pwrst = omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
|
||||
OMAP2_PM_PWSTCTRL,
|
||||
OMAP_POWERSTATE_MASK);
|
||||
|
||||
return omap2xxx_pwrst_to_common_pwrst(omap2xxx_pwrst);
|
||||
}
|
||||
|
||||
static int omap2xxx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
|
||||
{
|
||||
u8 omap2xxx_pwrst;
|
||||
|
||||
omap2xxx_pwrst = omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
|
||||
OMAP2_PM_PWSTST,
|
||||
OMAP_POWERSTATEST_MASK);
|
||||
|
||||
return omap2xxx_pwrst_to_common_pwrst(omap2xxx_pwrst);
|
||||
}
|
||||
|
||||
struct pwrdm_ops omap2_pwrdm_operations = {
|
||||
.pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst,
|
||||
.pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst,
|
||||
.pwrdm_read_pwrst = omap2_pwrdm_read_pwrst,
|
||||
.pwrdm_set_next_pwrst = omap2xxx_pwrdm_set_next_pwrst,
|
||||
.pwrdm_read_next_pwrst = omap2xxx_pwrdm_read_next_pwrst,
|
||||
.pwrdm_read_pwrst = omap2xxx_pwrdm_read_pwrst,
|
||||
.pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
|
||||
.pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
|
||||
.pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,
|
||||
|
|
|
|||
|
|
@ -103,28 +103,6 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
|
|||
/* Powerdomain low-level functions */
|
||||
|
||||
/* Common functions across OMAP2 and OMAP3 */
|
||||
int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
|
||||
{
|
||||
omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
|
||||
(pwrst << OMAP_POWERSTATE_SHIFT),
|
||||
pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
|
||||
{
|
||||
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
|
||||
OMAP2_PM_PWSTCTRL,
|
||||
OMAP_POWERSTATE_MASK);
|
||||
}
|
||||
|
||||
int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm)
|
||||
{
|
||||
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
|
||||
OMAP2_PM_PWSTST,
|
||||
OMAP_POWERSTATEST_MASK);
|
||||
}
|
||||
|
||||
int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
|
||||
u8 pwrst)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -277,6 +277,28 @@ static u32 omap3xxx_prm_read_reset_sources(void)
|
|||
|
||||
/* Powerdomain low-level functions */
|
||||
|
||||
static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
|
||||
{
|
||||
omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
|
||||
(pwrst << OMAP_POWERSTATE_SHIFT),
|
||||
pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int omap3_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
|
||||
{
|
||||
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
|
||||
OMAP2_PM_PWSTCTRL,
|
||||
OMAP_POWERSTATE_MASK);
|
||||
}
|
||||
|
||||
static int omap3_pwrdm_read_pwrst(struct powerdomain *pwrdm)
|
||||
{
|
||||
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
|
||||
OMAP2_PM_PWSTST,
|
||||
OMAP_POWERSTATEST_MASK);
|
||||
}
|
||||
|
||||
/* Applicable only for OMAP3. Not supported on OMAP2 */
|
||||
static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
|
||||
{
|
||||
|
|
@ -355,9 +377,9 @@ static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
|
|||
}
|
||||
|
||||
struct pwrdm_ops omap3_pwrdm_operations = {
|
||||
.pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst,
|
||||
.pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst,
|
||||
.pwrdm_read_pwrst = omap2_pwrdm_read_pwrst,
|
||||
.pwrdm_set_next_pwrst = omap3_pwrdm_set_next_pwrst,
|
||||
.pwrdm_read_next_pwrst = omap3_pwrdm_read_next_pwrst,
|
||||
.pwrdm_read_pwrst = omap3_pwrdm_read_pwrst,
|
||||
.pwrdm_read_prev_pwrst = omap3_pwrdm_read_prev_pwrst,
|
||||
.pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
|
||||
.pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst,
|
||||
|
|
|
|||
|
|
@ -56,9 +56,9 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
|
|||
* enumeration)
|
||||
*/
|
||||
static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
|
||||
{ OMAP4430_RST_GLOBAL_WARM_SW_SHIFT,
|
||||
{ OMAP4430_GLOBAL_WARM_SW_RST_SHIFT,
|
||||
OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
|
||||
{ OMAP4430_RST_GLOBAL_COLD_SW_SHIFT,
|
||||
{ OMAP4430_GLOBAL_COLD_RST_SHIFT,
|
||||
OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
|
||||
{ OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT,
|
||||
OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
|
||||
|
|
@ -333,7 +333,7 @@ static u32 omap44xx_prm_read_reset_sources(void)
|
|||
u32 r = 0;
|
||||
u32 v;
|
||||
|
||||
v = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
|
||||
v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
|
||||
OMAP4_RM_RSTST);
|
||||
|
||||
p = omap44xx_prm_reset_src_map;
|
||||
|
|
|
|||
|
|
@ -62,8 +62,8 @@
|
|||
|
||||
/* OMAP4 specific register offsets */
|
||||
#define OMAP4_RM_RSTCTRL 0x0000
|
||||
#define OMAP4_RM_RSTTIME 0x0004
|
||||
#define OMAP4_RM_RSTST 0x0008
|
||||
#define OMAP4_RM_RSTST 0x0004
|
||||
#define OMAP4_RM_RSTTIME 0x0008
|
||||
#define OMAP4_PM_PWSTCTRL 0x0000
|
||||
#define OMAP4_PM_PWSTST 0x0004
|
||||
|
||||
|
|
|
|||
|
|
@ -22,6 +22,8 @@
|
|||
#include <asm/mach/time.h>
|
||||
#include <asm/sched_clock.h>
|
||||
|
||||
#include <plat/counter-32k.h>
|
||||
|
||||
/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
|
||||
#define OMAP2_32KSYNCNT_REV_OFF 0x0
|
||||
#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
|
||||
|
|
|
|||
|
|
@ -26,6 +26,8 @@
|
|||
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <plat/sram.h>
|
||||
|
||||
#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
|
||||
|
||||
static void __iomem *omap_sram_base;
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ extern unsigned long samsung_cpu_id;
|
|||
#define EXYNOS4_CPU_MASK 0xFFFE0000
|
||||
|
||||
#define EXYNOS5250_SOC_ID 0x43520000
|
||||
#define EXYNOS5440_SOC_ID 0x54400000
|
||||
#define EXYNOS5440_SOC_ID 0xE5440000
|
||||
#define EXYNOS5_SOC_MASK 0xFFFFF000
|
||||
|
||||
#define IS_SAMSUNG_CPU(name, id, mask) \
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ struct mvebu_soc_descr {
|
|||
|
||||
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
|
||||
|
||||
static struct clk __init *mvebu_clk_gating_get_src(
|
||||
static struct clk *mvebu_clk_gating_get_src(
|
||||
struct of_phandle_args *clkspec, void *data)
|
||||
{
|
||||
struct mvebu_gating_ctrl *ctrl = (struct mvebu_gating_ctrl *)data;
|
||||
|
|
|
|||
|
|
@ -1361,13 +1361,16 @@ static int mv_xor_probe(struct platform_device *pdev)
|
|||
err_channel_add:
|
||||
for (i = 0; i < MV_XOR_MAX_CHANNELS; i++)
|
||||
if (xordev->channels[i]) {
|
||||
mv_xor_channel_remove(xordev->channels[i]);
|
||||
if (pdev->dev.of_node)
|
||||
irq_dispose_mapping(xordev->channels[i]->irq);
|
||||
mv_xor_channel_remove(xordev->channels[i]);
|
||||
}
|
||||
|
||||
clk_disable_unprepare(xordev->clk);
|
||||
clk_put(xordev->clk);
|
||||
if (!IS_ERR(xordev->clk)) {
|
||||
clk_disable_unprepare(xordev->clk);
|
||||
clk_put(xordev->clk);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -595,8 +595,11 @@ static int dove_pinctrl_probe(struct platform_device *pdev)
|
|||
* grab clk to make sure it is ticking.
|
||||
*/
|
||||
clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (!IS_ERR(clk))
|
||||
clk_prepare_enable(clk);
|
||||
if (IS_ERR(clk)) {
|
||||
dev_err(&pdev->dev, "Unable to get pdma clock");
|
||||
return PTR_RET(clk);
|
||||
}
|
||||
clk_prepare_enable(clk);
|
||||
|
||||
return mvebu_pinctrl_probe(pdev);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -29,15 +29,16 @@ static int gpio_active_low;
|
|||
|
||||
static void gpio_poweroff_do_poweroff(void)
|
||||
{
|
||||
BUG_ON(gpio_num == -1);
|
||||
BUG_ON(!gpio_is_valid(gpio_num));
|
||||
|
||||
/* drive it active */
|
||||
/* drive it active, also inactive->active edge */
|
||||
gpio_direction_output(gpio_num, !gpio_active_low);
|
||||
mdelay(100);
|
||||
/* rising edge or drive inactive */
|
||||
/* drive inactive, also active->inactive edge */
|
||||
gpio_set_value(gpio_num, gpio_active_low);
|
||||
mdelay(100);
|
||||
/* falling edge */
|
||||
|
||||
/* drive it active, also inactive->active edge */
|
||||
gpio_set_value(gpio_num, !gpio_active_low);
|
||||
|
||||
/* give it some time */
|
||||
|
|
@ -60,15 +61,12 @@ static int gpio_poweroff_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
gpio_num = of_get_gpio_flags(pdev->dev.of_node, 0, &flags);
|
||||
if (gpio_num < 0) {
|
||||
pr_err("%s: Could not get GPIO configuration: %d",
|
||||
__func__, gpio_num);
|
||||
return -ENODEV;
|
||||
}
|
||||
if (!gpio_is_valid(gpio_num))
|
||||
return gpio_num;
|
||||
|
||||
gpio_active_low = flags & OF_GPIO_ACTIVE_LOW;
|
||||
|
||||
if (of_get_property(pdev->dev.of_node, "input", NULL))
|
||||
input = true;
|
||||
input = of_property_read_bool(pdev->dev.of_node, "input");
|
||||
|
||||
ret = gpio_request(gpio_num, "poweroff-gpio");
|
||||
if (ret) {
|
||||
|
|
@ -98,8 +96,7 @@ err:
|
|||
|
||||
static int gpio_poweroff_remove(struct platform_device *pdev)
|
||||
{
|
||||
if (gpio_num != -1)
|
||||
gpio_free(gpio_num);
|
||||
gpio_free(gpio_num);
|
||||
if (pm_power_off == &gpio_poweroff_do_poweroff)
|
||||
pm_power_off = NULL;
|
||||
|
||||
|
|
@ -115,15 +112,15 @@ static struct platform_driver gpio_poweroff_driver = {
|
|||
.probe = gpio_poweroff_probe,
|
||||
.remove = gpio_poweroff_remove,
|
||||
.driver = {
|
||||
.name = "poweroff-gpio",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_gpio_poweroff_match,
|
||||
},
|
||||
.name = "poweroff-gpio",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_gpio_poweroff_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(gpio_poweroff_driver);
|
||||
|
||||
MODULE_AUTHOR("Jamie Lentin <jm@lentin.co.uk>");
|
||||
MODULE_DESCRIPTION("GPIO poweroff driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:poweroff-gpio");
|
||||
|
|
|
|||
|
|
@ -369,7 +369,8 @@ static void mxsfb_disable_controller(struct fb_info *fb_info)
|
|||
loop--;
|
||||
}
|
||||
|
||||
writel(VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4 + REG_CLR);
|
||||
reg = readl(host->base + LCDC_VDCTRL4);
|
||||
writel(reg & ~VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4);
|
||||
|
||||
clk_disable_unprepare(host->clk);
|
||||
|
||||
|
|
|
|||
Reference in New Issue