s3fb: fix Virge/GX2
Fix Virge/GX2 support in s3fb: - fix IDs: 86C357 is GX2, 86C359 is GX2+, 86C356 probably does not exist - add memory size detection - drive it the same way as Trio3D/2X The original IDs most likely came from S3 website which claims that: - 356 is Virge/GX2 with ID=8A10, driver included in Windows 2K, XP - 357 is Virge/GX2+ with ID=8A11, driver included in Windows ME - 359 is Virge/GX2+ with ID=8A12, driver included in Windows ME but: - google search for 86C356 only reveals references to Trio3D (probably because of a typo - Trio3D is 86C365) - my card is clearly marked as 86C357, Virge/GX2 and has ID=8A10 - there is no driver for IDs 8A11 and 8A12 in Windows ME - there is a driver for ID 8A10 in Windows ME that says it's GX2 (357) Tested with #9 Reality 334 (86C357 Virge/GX2, ID=0x8A10). Signed-off-by: Ondrej Zary <linux@rainbow-software.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Ondrej Zary
Paul Mundt
parent
62e0ff1ef2
commit
94e948e6e4
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@ -71,9 +71,9 @@ static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
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static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+",
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"S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX",
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"S3 Plato/PX", "S3 Aurora64VP", "S3 Virge",
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"S3 Plato/PX", "S3 Aurora64V+", "S3 Virge",
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"S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
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"S3 Virge/GX2", "S3 Virge/GX2P", "S3 Virge/GX2P",
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"S3 Virge/GX2", "S3 Virge/GX2+", "",
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"S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X",
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"S3 Trio3D"};
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@ -90,9 +90,8 @@ static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64",
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#define CHIP_988_VIRGE_VX 0x0A
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#define CHIP_375_VIRGE_DX 0x0B
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#define CHIP_385_VIRGE_GX 0x0C
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#define CHIP_356_VIRGE_GX2 0x0D
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#define CHIP_357_VIRGE_GX2P 0x0E
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#define CHIP_359_VIRGE_GX2P 0x0F
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#define CHIP_357_VIRGE_GX2 0x0D
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#define CHIP_359_VIRGE_GX2P 0x0E
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#define CHIP_360_TRIO3D_1X 0x10
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#define CHIP_362_TRIO3D_2X 0x11
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#define CHIP_368_TRIO3D_2X 0x12
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@ -359,7 +358,9 @@ static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
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vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
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/* Set S3 clock registers */
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if (par->chip == CHIP_360_TRIO3D_1X ||
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if (par->chip == CHIP_357_VIRGE_GX2 ||
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par->chip == CHIP_359_VIRGE_GX2P ||
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par->chip == CHIP_360_TRIO3D_1X ||
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par->chip == CHIP_362_TRIO3D_2X ||
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par->chip == CHIP_368_TRIO3D_2X) {
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vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */
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@ -560,7 +561,9 @@ static int s3fb_set_par(struct fb_info *info)
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pr_debug("fb%d: offset register : %d\n", info->node, offset_value);
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svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value);
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if (par->chip != CHIP_360_TRIO3D_1X &&
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if (par->chip != CHIP_357_VIRGE_GX2 &&
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par->chip != CHIP_359_VIRGE_GX2P &&
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par->chip != CHIP_360_TRIO3D_1X &&
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par->chip != CHIP_362_TRIO3D_2X &&
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par->chip != CHIP_368_TRIO3D_2X) {
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vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */
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@ -604,7 +607,9 @@ static int s3fb_set_par(struct fb_info *info)
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vga_wcrt(par->state.vgabase, 0x66, 0x90);
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}
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if (par->chip == CHIP_360_TRIO3D_1X ||
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if (par->chip == CHIP_357_VIRGE_GX2 ||
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par->chip == CHIP_359_VIRGE_GX2P ||
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par->chip == CHIP_360_TRIO3D_1X ||
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par->chip == CHIP_362_TRIO3D_2X ||
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par->chip == CHIP_368_TRIO3D_2X ||
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par->chip == CHIP_365_TRIO3D ||
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@ -617,8 +622,7 @@ static int s3fb_set_par(struct fb_info *info)
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vga_wcrt(par->state.vgabase, 0x66, 0x81);
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}
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if (par->chip == CHIP_356_VIRGE_GX2 ||
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par->chip == CHIP_357_VIRGE_GX2P ||
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if (par->chip == CHIP_357_VIRGE_GX2 ||
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par->chip == CHIP_359_VIRGE_GX2P ||
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par->chip == CHIP_360_TRIO3D_1X ||
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par->chip == CHIP_362_TRIO3D_2X ||
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@ -674,6 +678,8 @@ static int s3fb_set_par(struct fb_info *info)
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pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
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svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
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if (info->var.pixclock > 20000 ||
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par->chip == CHIP_357_VIRGE_GX2 ||
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par->chip == CHIP_359_VIRGE_GX2P ||
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par->chip == CHIP_360_TRIO3D_1X ||
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par->chip == CHIP_362_TRIO3D_2X ||
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par->chip == CHIP_368_TRIO3D_2X)
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@ -702,7 +708,9 @@ static int s3fb_set_par(struct fb_info *info)
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} else {
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svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
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svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
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if (par->chip != CHIP_360_TRIO3D_1X &&
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if (par->chip != CHIP_357_VIRGE_GX2 &&
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par->chip != CHIP_359_VIRGE_GX2P &&
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par->chip != CHIP_360_TRIO3D_1X &&
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par->chip != CHIP_362_TRIO3D_2X &&
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par->chip != CHIP_368_TRIO3D_2X)
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hmul = 2;
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@ -727,7 +735,9 @@ static int s3fb_set_par(struct fb_info *info)
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} else {
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svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
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svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
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if (par->chip != CHIP_360_TRIO3D_1X &&
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if (par->chip != CHIP_357_VIRGE_GX2 &&
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par->chip != CHIP_359_VIRGE_GX2P &&
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par->chip != CHIP_360_TRIO3D_1X &&
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par->chip != CHIP_362_TRIO3D_2X &&
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par->chip != CHIP_368_TRIO3D_2X)
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hmul = 2;
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@ -1069,6 +1079,16 @@ static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_i
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info->screen_size = 2 << 20;
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break;
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}
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} else if (par->chip == CHIP_357_VIRGE_GX2 ||
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par->chip == CHIP_359_VIRGE_GX2P) {
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switch ((regval & 0xC0) >> 6) {
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case 1: /* 4MB */
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info->screen_size = 4 << 20;
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break;
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case 3: /* 2MB */
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info->screen_size = 2 << 20;
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break;
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}
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} else
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info->screen_size = s3_memsizes[regval >> 5] << 10;
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info->fix.smem_len = info->screen_size;
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@ -1268,8 +1288,8 @@ static struct pci_device_id s3_devices[] __devinitdata = {
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{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE},
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{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX},
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{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX},
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{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_356_VIRGE_GX2},
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{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_357_VIRGE_GX2P},
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{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_357_VIRGE_GX2},
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{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_359_VIRGE_GX2P},
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{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
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{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X},
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{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8904), .driver_data = CHIP_365_TRIO3D},
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