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[MIPS] Malta: Fix build errors for 64-bit kernels 

Fix 64-bit Malta by using CKSEG0ADDR and correct casts.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Thomas Bogendoerfer 2008-05-29 22:05:07 +02:00 committed by Ralf Baechle
parent 1f34f2e426
commit 938b2b1417
2 changed files with 4 additions and 4 deletions
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4
arch/mips/mips-boards/generic/amon.c
View File

@ -28,7 +28,7 @@
int amon_cpu_avail(int cpu)
{
struct cpulaunch *launch = (struct cpulaunch *)KSEG0ADDR(CPULAUNCH);
struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
if (cpu < 0 || cpu >= NCPULAUNCH) {
pr_debug("avail: cpu%d is out of range\n", cpu);
@ -53,7 +53,7 @@ void amon_cpu_start(int cpu,
unsigned long gp, unsigned long a0)
{
volatile struct cpulaunch *launch =
(struct cpulaunch *)KSEG0ADDR(CPULAUNCH);
(struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
if (!amon_cpu_avail(cpu))
return;

4
include/asm-mips/gic.h
View File

@ -24,8 +24,8 @@
#define MSK(n) ((1 << (n)) - 1)
#define REG32(addr) (*(volatile unsigned int *) (addr))
#define REG(base, offs) REG32((unsigned int)(base) + offs##_##OFS)
#define REGP(base, phys) REG32((unsigned int)(base) + (phys))
#define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS)
#define REGP(base, phys) REG32((unsigned long)(base) + (phys))
/* Accessors */
#define GIC_REG(segment, offset) \