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x86: provide readq()/writeq() on 32-bit too, complete

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if HAVE_READQ/HAVE_WRITEQ are defined, the full range of readq/writeq
APIs has to be provided to drivers:

 drivers/infiniband/hw/amso1100/c2.c: In function 'c2_tx_ring_alloc':
 drivers/infiniband/hw/amso1100/c2.c:133: error: implicit declaration of function '__raw_writeq'

So provide them on 32-bit as well. Also, map all the APIs to the
strongest ordering variant. It's way too easy to mess such details
up in drivers and the difference between "memory" and "" constrained
asm() constructs is in the noise range.

Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Ingo Molnar 2008-11-30 10:20:20 +01:00
parent a0b1131e47
commit 93093d099e
1 changed files with 9 additions and 9 deletions
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18
arch/x86/include/asm/io.h
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@ -46,16 +46,11 @@ build_mmio_write(__writel, "l", unsigned int, "r", )
#define mmiowb() barrier()
#ifdef CONFIG_X86_64
build_mmio_read(readq, "q", unsigned long, "=r", :"memory")
build_mmio_read(__readq, "q", unsigned long, "=r", )
build_mmio_write(writeq, "q", unsigned long, "r", :"memory")
build_mmio_write(__writeq, "q", unsigned long, "r", )
#define readq_relaxed(a) __readq(a)
#define __raw_readq __readq
#define __raw_writeq writeq
#else /* CONFIG_X86_32 from here */
#else
static inline __u64 readq(const volatile void __iomem *addr)
{
@ -76,9 +71,14 @@ static inline void writeq(__u64 val, volatile void __iomem *addr)
#endif
#define readq_relaxed(a) readq(a)
#define __raw_readq(a) readq(a)
#define __raw_writeq(val, addr) writeq(val, addr)
/* Let people know that we have them */
#define readq readq
#define writeq writeq
#define readq readq
#define writeq writeq
extern int iommu_bio_merge;