ARM: zynq: add clk binding support to the ttc
Add support for retrieving TTC configuration from device tree. This includes the ability to pull information about the driving clocks from the of_clk bindings. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Josh Cartwright
Michal Simek
parent
0f586fbf6f
commit
91dc985c5e
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@ -109,5 +109,58 @@
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};
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};
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};
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ttc0: ttc0@f8001000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "xlnx,ttc";
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reg = <0xF8001000 0x1000>;
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clocks = <&cpu_clk 3>;
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clock-names = "cpu_1x";
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clock-ranges;
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ttc0_0: ttc0.0 {
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status = "disabled";
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reg = <0>;
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interrupts = <0 10 4>;
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};
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ttc0_1: ttc0.1 {
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status = "disabled";
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reg = <1>;
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interrupts = <0 11 4>;
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};
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ttc0_2: ttc0.2 {
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status = "disabled";
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reg = <2>;
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interrupts = <0 12 4>;
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};
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};
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ttc1: ttc1@f8002000 {
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#interrupt-parent = <&intc>;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "xlnx,ttc";
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reg = <0xF8002000 0x1000>;
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clocks = <&cpu_clk 3>;
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clock-names = "cpu_1x";
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clock-ranges;
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ttc1_0: ttc1.0 {
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status = "disabled";
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reg = <0>;
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interrupts = <0 37 4>;
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};
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ttc1_1: ttc1.1 {
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status = "disabled";
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reg = <1>;
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interrupts = <0 38 4>;
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};
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ttc1_2: ttc1.2 {
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status = "disabled";
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reg = <2>;
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interrupts = <0 39 4>;
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};
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};
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};
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};
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@ -32,3 +32,13 @@
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&ps_clk {
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clock-frequency = <33333330>;
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};
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&ttc0_0 {
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status = "ok";
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compatible = "xlnx,ttc-counter-clocksource";
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};
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&ttc0_1 {
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status = "ok";
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compatible = "xlnx,ttc-counter-clockevent";
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};
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@ -23,31 +23,15 @@
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#include <linux/clk-provider.h>
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#include <mach/zynq_soc.h>
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#include "common.h"
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#define IRQ_TIMERCOUNTER0 42
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/*
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* This driver configures the 2 16-bit count-up timers as follows:
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*
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* T1: Timer 1, clocksource for generic timekeeping
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* T2: Timer 2, clockevent source for hrtimers
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* T3: Timer 3, <unused>
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*
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* The input frequency to the timer module for emulation is 2.5MHz which is
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* common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
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* the timers are clocked at 78.125KHz (12.8 us resolution).
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*
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* The input frequency to the timer module in silicon will be 200MHz. With the
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* pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution).
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*/
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#define XTTCPSS_CLOCKSOURCE 0 /* Timer 1 as a generic timekeeping */
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#define XTTCPSS_CLOCKEVENT 1 /* Timer 2 as a clock event */
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#define XTTCPSS_TIMER_BASE TTC0_BASE
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#define XTTCPCC_EVENT_TIMER_IRQ (IRQ_TIMERCOUNTER0 + 1)
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/*
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* Timer Register Offset Definitions of Timer 1, Increment base address by 4
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* and use same offsets for Timer 2
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@ -64,9 +48,14 @@
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#define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1
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/* Setup the timers to use pre-scaling */
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#define TIMER_RATE (PERIPHERAL_CLOCK_RATE / 32)
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/* Setup the timers to use pre-scaling, using a fixed value for now that will
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* work across most input frequency, but it may need to be more dynamic
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*/
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#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
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#define PRESCALE 2048 /* The exponent must match this */
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#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
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#define CLK_CNTRL_PRESCALE_EN 1
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#define CNT_CNTRL_RESET (1<<4)
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/**
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* struct xttcpss_timer - This definition defines local timer structure
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@ -74,11 +63,25 @@
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* @base_addr: Base address of timer
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**/
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struct xttcpss_timer {
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void __iomem *base_addr;
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void __iomem *base_addr;
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};
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static struct xttcpss_timer timers[2];
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static struct clock_event_device xttcpss_clockevent;
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struct xttcpss_timer_clocksource {
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struct xttcpss_timer xttc;
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struct clocksource cs;
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};
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#define to_xttcpss_timer_clksrc(x) \
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container_of(x, struct xttcpss_timer_clocksource, cs)
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struct xttcpss_timer_clockevent {
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struct xttcpss_timer xttc;
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struct clock_event_device ce;
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struct clk *clk;
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};
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#define to_xttcpss_timer_clkevent(x) \
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container_of(x, struct xttcpss_timer_clockevent, ce)
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/**
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* xttcpss_set_interval - Set the timer interval value
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@ -100,7 +103,7 @@ static void xttcpss_set_interval(struct xttcpss_timer *timer,
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/* Reset the counter (0x10) so that it starts from 0, one-shot
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mode makes this needed for timing to be right. */
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ctrl_reg |= 0x10;
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ctrl_reg |= CNT_CNTRL_RESET;
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ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
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}
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@ -115,90 +118,31 @@ static void xttcpss_set_interval(struct xttcpss_timer *timer,
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**/
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static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &xttcpss_clockevent;
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struct xttcpss_timer *timer = dev_id;
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struct xttcpss_timer_clockevent *xttce = dev_id;
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struct xttcpss_timer *timer = &xttce->xttc;
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/* Acknowledge the interrupt and call event handler */
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__raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
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timer->base_addr + XTTCPSS_ISR_OFFSET);
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evt->event_handler(evt);
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xttce->ce.event_handler(&xttce->ce);
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return IRQ_HANDLED;
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}
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static struct irqaction event_timer_irq = {
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.name = "xttcpss clockevent",
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = xttcpss_clock_event_interrupt,
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};
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/**
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* xttcpss_timer_hardware_init - Initialize the timer hardware
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*
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* Initialize the hardware to start the clock source, get the clock
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* event timer ready to use, and hook up the interrupt.
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**/
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static void __init xttcpss_timer_hardware_init(void)
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{
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/* Setup the clock source counter to be an incrementing counter
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* with no interrupt and it rolls over at 0xFFFF. Pre-scale
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it by 32 also. Let it start running now.
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*/
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timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE;
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__raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr +
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XTTCPSS_IER_OFFSET);
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__raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr +
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XTTCPSS_CLK_CNTRL_OFFSET);
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__raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr +
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XTTCPSS_CNT_CNTRL_OFFSET);
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/* Setup the clock event timer to be an interval timer which
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* is prescaled by 32 using the interval interrupt. Leave it
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* disabled for now.
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*/
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timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4;
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__raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr +
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XTTCPSS_CNT_CNTRL_OFFSET);
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__raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr +
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XTTCPSS_CLK_CNTRL_OFFSET);
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__raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr +
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XTTCPSS_IER_OFFSET);
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/* Setup IRQ the clock event timer */
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event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT];
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setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq);
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}
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/**
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* __raw_readl_cycles - Reads the timer counter register
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* __xttc_clocksource_read - Reads the timer counter register
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*
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* returns: Current timer counter register value
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**/
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static cycle_t __raw_readl_cycles(struct clocksource *cs)
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static cycle_t __xttc_clocksource_read(struct clocksource *cs)
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{
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struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE];
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struct xttcpss_timer *timer = &to_xttcpss_timer_clksrc(cs)->xttc;
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return (cycle_t)__raw_readl(timer->base_addr +
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XTTCPSS_COUNT_VAL_OFFSET);
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}
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/*
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* Instantiate and initialize the clock source structure
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*/
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static struct clocksource clocksource_xttcpss = {
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.name = "xttcpss_timer1",
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.rating = 200, /* Reasonable clock source */
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.read = __raw_readl_cycles,
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.mask = CLOCKSOURCE_MASK(16),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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/**
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* xttcpss_set_next_event - Sets the time interval for next event
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*
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@ -210,7 +154,8 @@ static struct clocksource clocksource_xttcpss = {
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static int xttcpss_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
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struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt);
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struct xttcpss_timer *timer = &xttce->xttc;
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xttcpss_set_interval(timer, cycles);
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return 0;
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@ -225,12 +170,15 @@ static int xttcpss_set_next_event(unsigned long cycles,
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static void xttcpss_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
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struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt);
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struct xttcpss_timer *timer = &xttce->xttc;
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u32 ctrl_reg;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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xttcpss_set_interval(timer, TIMER_RATE / HZ);
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xttcpss_set_interval(timer,
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DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
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PRESCALE * HZ));
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_UNUSED:
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@ -251,15 +199,106 @@ static void xttcpss_set_mode(enum clock_event_mode mode,
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}
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}
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/*
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* Instantiate and initialize the clock event structure
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*/
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static struct clock_event_device xttcpss_clockevent = {
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.name = "xttcpss_timer2",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = xttcpss_set_next_event,
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.set_mode = xttcpss_set_mode,
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.rating = 200,
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static void __init zynq_ttc_setup_clocksource(struct device_node *np,
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void __iomem *base)
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{
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struct xttcpss_timer_clocksource *ttccs;
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struct clk *clk;
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int err;
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u32 reg;
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ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
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if (WARN_ON(!ttccs))
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return;
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err = of_property_read_u32(np, "reg", ®);
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if (WARN_ON(err))
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return;
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clk = of_clk_get_by_name(np, "cpu_1x");
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if (WARN_ON(IS_ERR(clk)))
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return;
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err = clk_prepare_enable(clk);
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if (WARN_ON(err))
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return;
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ttccs->xttc.base_addr = base + reg * 4;
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ttccs->cs.name = np->name;
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ttccs->cs.rating = 200;
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ttccs->cs.read = __xttc_clocksource_read;
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ttccs->cs.mask = CLOCKSOURCE_MASK(16);
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ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
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__raw_writel(0x0, ttccs->xttc.base_addr + XTTCPSS_IER_OFFSET);
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__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
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ttccs->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET);
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__raw_writel(CNT_CNTRL_RESET,
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ttccs->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
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err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
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if (WARN_ON(err))
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return;
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}
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static void __init zynq_ttc_setup_clockevent(struct device_node *np,
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void __iomem *base)
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{
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struct xttcpss_timer_clockevent *ttcce;
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int err, irq;
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u32 reg;
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ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
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if (WARN_ON(!ttcce))
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return;
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err = of_property_read_u32(np, "reg", ®);
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if (WARN_ON(err))
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return;
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ttcce->xttc.base_addr = base + reg * 4;
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ttcce->clk = of_clk_get_by_name(np, "cpu_1x");
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if (WARN_ON(IS_ERR(ttcce->clk)))
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return;
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err = clk_prepare_enable(ttcce->clk);
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if (WARN_ON(err))
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return;
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irq = irq_of_parse_and_map(np, 0);
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if (WARN_ON(!irq))
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return;
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ttcce->ce.name = np->name;
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ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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ttcce->ce.set_next_event = xttcpss_set_next_event;
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ttcce->ce.set_mode = xttcpss_set_mode;
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ttcce->ce.rating = 200;
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ttcce->ce.irq = irq;
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__raw_writel(0x23, ttcce->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
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__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
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ttcce->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET);
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__raw_writel(0x1, ttcce->xttc.base_addr + XTTCPSS_IER_OFFSET);
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err = request_irq(irq, xttcpss_clock_event_interrupt, IRQF_TIMER,
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np->name, ttcce);
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if (WARN_ON(err))
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return;
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clockevents_config_and_register(&ttcce->ce,
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clk_get_rate(ttcce->clk) / PRESCALE,
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1, 0xfffe);
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}
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static const __initconst struct of_device_id zynq_ttc_match[] = {
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{ .compatible = "xlnx,ttc-counter-clocksource",
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.data = zynq_ttc_setup_clocksource, },
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{ .compatible = "xlnx,ttc-counter-clockevent",
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.data = zynq_ttc_setup_clockevent, },
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{}
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};
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/**
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@ -270,21 +309,25 @@ static struct clock_event_device xttcpss_clockevent = {
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**/
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void __init xttcpss_timer_init(void)
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{
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xttcpss_timer_hardware_init();
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clocksource_register_hz(&clocksource_xttcpss, TIMER_RATE);
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struct device_node *np;
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/* Calculate the parameters to allow the clockevent to operate using
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integer math
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*/
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clockevents_calc_mult_shift(&xttcpss_clockevent, TIMER_RATE, 4);
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for_each_compatible_node(np, NULL, "xlnx,ttc") {
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struct device_node *np_chld;
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void __iomem *base;
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xttcpss_clockevent.max_delta_ns =
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clockevent_delta2ns(0xfffe, &xttcpss_clockevent);
|
||||
xttcpss_clockevent.min_delta_ns =
|
||||
clockevent_delta2ns(1, &xttcpss_clockevent);
|
||||
base = of_iomap(np, 0);
|
||||
if (WARN_ON(!base))
|
||||
return;
|
||||
|
||||
/* Indicate that clock event is on 1st CPU as SMP boot needs it */
|
||||
for_each_available_child_of_node(np, np_chld) {
|
||||
int (*cb)(struct device_node *np, void __iomem *base);
|
||||
const struct of_device_id *match;
|
||||
|
||||
xttcpss_clockevent.cpumask = cpumask_of(0);
|
||||
clockevents_register_device(&xttcpss_clockevent);
|
||||
match = of_match_node(zynq_ttc_match, np_chld);
|
||||
if (match) {
|
||||
cb = match->data;
|
||||
cb(np_chld, base);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Reference in New Issue