ARM: vexpress: Add Device Tree support
This patch adds generic Versatile Express DT machine description, Device Tree description for the motherboard and documentation for the bindings. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
This commit is contained in:
Pawel Moll
parent
95d59741d2
commit
8deed1786a
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@ -0,0 +1,146 @@
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ARM Versatile Express boards family
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-----------------------------------
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ARM's Versatile Express platform consists of a motherboard and one
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or more daughterboards (tiles). The motherboard provides a set of
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peripherals. Processor and RAM "live" on the tiles.
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The motherboard and each core tile should be described by a separate
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Device Tree source file, with the tile's description including
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the motherboard file using a /include/ directive. As the motherboard
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can be initialized in one of two different configurations ("memory
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maps"), care must be taken to include the correct one.
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Required properties in the root node:
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- compatible value:
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compatible = "arm,vexpress,<model>", "arm,vexpress";
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where <model> is the full tile model name (as used in the tile's
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Technical Reference Manual), eg.:
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- for Coretile Express A5x2 (V2P-CA5s):
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compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
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- for Coretile Express A9x4 (V2P-CA9):
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compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
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If a tile comes in several variants or can be used in more then one
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configuration, the compatible value should be:
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compatible = "arm,vexpress,<model>,<variant>", \
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"arm,vexpress,<model>", "arm,vexpress";
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eg:
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- Coretile Express A15x2 (V2P-CA15) with Tech Chip 1:
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compatible = "arm,vexpress,v2p-ca15,tc1", \
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"arm,vexpress,v2p-ca15", "arm,vexpress";
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- LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM:
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compatible = "arm,vexpress,v2f-2xv6,ca7x3", \
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"arm,vexpress,v2f-2xv6", "arm,vexpress";
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Optional properties in the root node:
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- tile model name (use name from the tile's Technical Reference
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Manual, eg. "V2P-CA5s")
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model = "<model>";
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- tile's HBI number (unique ARM's board model ID, visible on the
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PCB's silkscreen) in hexadecimal transcription:
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arm,hbi = <0xhbi>
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eg:
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- for Coretile Express A5x2 (V2P-CA5s) HBI-0191:
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arm,hbi = <0x191>;
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- Coretile Express A9x4 (V2P-CA9) HBI-0225:
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arm,hbi = <0x225>;
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Top-level standard "cpus" node is required. It must contain a node
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with device_type = "cpu" property for every available core, eg.:
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <0>;
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};
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};
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The motherboard description file provides a single "motherboard" node
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using 2 address cells corresponding to the Static Memory Bus used
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between the motherboard and the tile. The first cell defines the Chip
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Select (CS) line number, the second cell address offset within the CS.
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All interrupt lines between the motherboard and the tile are active
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high and are described using single cell.
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Optional properties of the "motherboard" node:
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- motherboard's memory map variant:
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arm,v2m-memory-map = "<name>";
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where name is one of:
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- "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also
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referred to as "ARM Cortex-A Series memory map":
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arm,v2m-memory-map = "rs1";
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When this property is missing, the motherboard is using the original
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memory map (also known as the "Legacy memory map", primarily used
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with the original CoreTile Express A9x4) with peripherals on CS7.
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Motherboard .dtsi files provide a set of labelled peripherals that
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can be used to obtain required phandle in the tile's "aliases" node:
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- UARTs, note that the numbers correspond to the physical connectors
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on the motherboard's back panel:
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v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3
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- I2C controllers:
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v2m_i2c_dvi and v2m_i2c_pcie
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- SP804 timers:
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v2m_timer01 and v2m_timer23
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Current Linux implementation requires a "arm,v2m_timer" alias
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pointing at one of the motherboard's SP804 timers, if it is to be
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used as the system timer. This alias should be defined in the
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motherboard files.
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The tile description must define "ranges", "interrupt-map-mask" and
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"interrupt-map" properties to translate the motherboard's address
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and interrupt space into one used by the tile's processor.
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Abbreviated example:
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/dts-v1/;
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/ {
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model = "V2P-CA5s";
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arm,hbi = <0x225>;
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compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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aliases {
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serial0 = &v2m_serial0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <0>;
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};
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};
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gic: interrupt-controller@2c001000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x2c001000 0x1000>,
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<0x2c000100 0x100>;
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};
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motherboard {
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/* CS0 is visible at 0x08000000 */
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ranges = <0 0 0x08000000 0x04000000>;
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interrupt-map-mask = <0 0 63>;
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/* Active high IRQ 0 is connected to GIC's SPI0 */
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interrupt-map = <0 0 0 &gic 0 0 4>;
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};
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};
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/include/ "vexpress-v2m-rs1.dtsi"
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@ -0,0 +1,200 @@
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/*
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* ARM Ltd. Versatile Express
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*
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* Motherboard Express uATX
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* V2M-P1
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*
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* HBI-0190D
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*
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* Original memory map ("Legacy memory map" in the board's
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* Technical Reference Manual)
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*
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* WARNING! The hardware described in this file is independent from the
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* RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
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* correspondence between the two configurations.
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*
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* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
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* CHANGES TO vexpress-v2m-rs1.dtsi!
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*/
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/ {
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aliases {
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arm,v2m_timer = &v2m_timer01;
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};
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motherboard {
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compatible = "simple-bus";
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#address-cells = <2>; /* SMB chipselect number and offset */
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#size-cells = <1>;
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#interrupt-cells = <1>;
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flash@0,00000000 {
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compatible = "arm,vexpress-flash", "cfi-flash";
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reg = <0 0x00000000 0x04000000>,
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<1 0x00000000 0x04000000>;
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bank-width = <4>;
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};
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psram@2,00000000 {
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compatible = "arm,vexpress-psram", "mtd-ram";
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reg = <2 0x00000000 0x02000000>;
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bank-width = <4>;
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};
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vram@3,00000000 {
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compatible = "arm,vexpress-vram";
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reg = <3 0x00000000 0x00800000>;
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};
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ethernet@3,02000000 {
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compatible = "smsc,lan9118", "smsc,lan9115";
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reg = <3 0x02000000 0x10000>;
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interrupts = <15>;
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phy-mode = "mii";
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reg-io-width = <4>;
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smsc,irq-active-high;
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smsc,irq-push-pull;
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};
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usb@3,03000000 {
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compatible = "nxp,usb-isp1761";
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reg = <3 0x03000000 0x20000>;
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interrupts = <16>;
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port1-otg;
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};
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iofpga@7,00000000 {
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compatible = "arm,amba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 7 0 0x20000>;
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sysreg@00000 {
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compatible = "arm,vexpress-sysreg";
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reg = <0x00000 0x1000>;
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};
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sysctl@01000 {
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compatible = "arm,sp810", "arm,primecell";
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reg = <0x01000 0x1000>;
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};
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/* PCI-E I2C bus */
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v2m_i2c_pcie: i2c@02000 {
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compatible = "arm,versatile-i2c";
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reg = <0x02000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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pcie-switch@60 {
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compatible = "idt,89hpes32h8";
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reg = <0x60>;
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};
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};
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aaci@04000 {
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compatible = "arm,pl041", "arm,primecell";
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reg = <0x04000 0x1000>;
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interrupts = <11>;
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};
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mmci@05000 {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0x05000 0x1000>;
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interrupts = <9 10>;
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};
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kmi@06000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x06000 0x1000>;
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interrupts = <12>;
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};
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kmi@07000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x07000 0x1000>;
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interrupts = <13>;
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};
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v2m_serial0: uart@09000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x09000 0x1000>;
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interrupts = <5>;
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};
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v2m_serial1: uart@0a000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0a000 0x1000>;
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interrupts = <6>;
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};
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v2m_serial2: uart@0b000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0b000 0x1000>;
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interrupts = <7>;
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};
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v2m_serial3: uart@0c000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0c000 0x1000>;
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interrupts = <8>;
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};
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wdt@0f000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x0f000 0x1000>;
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interrupts = <0>;
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};
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v2m_timer01: timer@11000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x11000 0x1000>;
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interrupts = <2>;
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};
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v2m_timer23: timer@12000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x12000 0x1000>;
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};
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/* DVI I2C bus */
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v2m_i2c_dvi: i2c@16000 {
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compatible = "arm,versatile-i2c";
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reg = <0x16000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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dvi-transmitter@39 {
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compatible = "sil,sii9022-tpi", "sil,sii9022";
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reg = <0x39>;
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};
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dvi-transmitter@60 {
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compatible = "sil,sii9022-cpi", "sil,sii9022";
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reg = <0x60>;
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};
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};
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rtc@17000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x17000 0x1000>;
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interrupts = <4>;
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};
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compact-flash@1a000 {
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compatible = "arm,vexpress-cf", "ata-generic";
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reg = <0x1a000 0x100
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0x1a100 0xf00>;
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reg-shift = <2>;
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};
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clcd@1f000 {
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compatible = "arm,pl111", "arm,primecell";
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reg = <0x1f000 0x1000>;
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interrupts = <14>;
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};
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};
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};
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};
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@ -1,14 +1,55 @@
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menu "Versatile Express platform type"
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depends on ARCH_VEXPRESS
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config ARCH_VEXPRESS_CA9X4
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bool "Versatile Express Cortex-A9x4 tile"
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select CPU_V7
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select ARM_GIC
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config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
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bool
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select ARM_ERRATA_720789
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select ARM_ERRATA_751472
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select ARM_ERRATA_753970
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select PL310_ERRATA_753970 if CACHE_PL310
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help
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Provides common dependencies for Versatile Express platforms
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based on Cortex-A5 and Cortex-A9 processors. In order to
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build a working kernel, you must also enable relevant core
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tile support or Flattened Device Tree based support options.
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config ARCH_VEXPRESS_CA9X4
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bool "Versatile Express Cortex-A9x4 tile"
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select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
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select ARM_GIC
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select CPU_V7
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select HAVE_SMP
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select MIGHT_HAVE_CACHE_L2X0
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config ARCH_VEXPRESS_DT
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bool "Device Tree support for Versatile Express platforms"
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select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
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select ARM_GIC
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select ARM_PATCH_PHYS_VIRT
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select AUTO_ZRELADDR
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select CPU_V7
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select HAVE_SMP
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select MIGHT_HAVE_CACHE_L2X0
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select USE_OF
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help
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New Versatile Express platforms require Flattened Device Tree to
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be passed to the kernel.
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This option enables support for systems using Cortex processor based
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ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
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for example:
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- CoreTile Express A5x2 (V2P-CA5s)
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- CoreTile Express A9x4 (V2P-CA9)
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- CoreTile Express A15x2 (V2P-CA15)
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- LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs
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(Soft Macrocell Models)
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- Versatile Express RTSMs (Models)
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You must boot using a Flattened Device Tree in order to use these
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platforms. The traditional (ATAGs) boot method is not usable on
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these boards with this option.
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If your bootloader supports Flattened Device Tree based booting,
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say Y here.
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endmenu
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@ -1,3 +1,5 @@
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# Those numbers are used only by the non-DT V2P-CA9 platform
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# The DT-enabled ones require CONFIG_AUTO_ZRELADDR=y
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zreladdr-y += 0x60008000
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params_phys-y := 0x60000100
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initrd_phys-y := 0x60800000
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@ -116,6 +116,12 @@ int v2m_cfg_write(u32 devfn, u32 data);
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int v2m_cfg_read(u32 devfn, u32 *data);
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void v2m_flags_set(u32 data);
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/*
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* Miscellaneous
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*/
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#define SYS_MISC_MASTERSITE (1 << 14)
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#define SYS_PROCIDx_HBI_MASK 0xfff
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/*
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* Core tile IDs
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*/
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@ -6,6 +6,10 @@
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#include <linux/amba/mmci.h>
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/of_address.h>
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#include <linux/of_fdt.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/ata_platform.h>
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#include <linux/smsc911x.h>
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@ -21,6 +25,8 @@
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/hardware/gic.h>
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#include <asm/hardware/timer-sp.h>
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#include <asm/hardware/sp810.h>
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#include <asm/hardware/gic.h>
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@ -430,8 +436,9 @@ static void __init v2m_populate_ct_desc(void)
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ct_desc = ct_descs[i];
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if (!ct_desc)
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panic("vexpress: failed to populate core tile description "
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"for tile ID 0x%8x\n", current_tile_id);
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panic("vexpress: this kernel does not support core tile ID 0x%08x when booting via ATAGs.\n"
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"You may need a device tree blob or a different kernel to boot on this board.\n",
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current_tile_id);
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}
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static void __init v2m_map_io(void)
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@ -476,3 +483,145 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
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.init_machine = v2m_init,
|
||||
.restart = v2m_restart,
|
||||
MACHINE_END
|
||||
|
||||
#if defined(CONFIG_ARCH_VEXPRESS_DT)
|
||||
|
||||
void __init v2m_dt_map_io(void)
|
||||
{
|
||||
iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
|
||||
|
||||
#if defined(CONFIG_SMP)
|
||||
vexpress_dt_smp_map_io();
|
||||
#endif
|
||||
}
|
||||
|
||||
static struct clk_lookup v2m_dt_lookups[] = {
|
||||
{ /* AMBA bus clock */
|
||||
.con_id = "apb_pclk",
|
||||
.clk = &dummy_apb_pclk,
|
||||
}, { /* SP804 timers */
|
||||
.dev_id = "sp804",
|
||||
.con_id = "v2m-timer0",
|
||||
.clk = &v2m_sp804_clk,
|
||||
}, { /* SP804 timers */
|
||||
.dev_id = "sp804",
|
||||
.con_id = "v2m-timer1",
|
||||
.clk = &v2m_sp804_clk,
|
||||
}, { /* PL180 MMCI */
|
||||
.dev_id = "mb:mmci", /* 10005000.mmci */
|
||||
.clk = &osc2_clk,
|
||||
}, { /* PL050 KMI0 */
|
||||
.dev_id = "10006000.kmi",
|
||||
.clk = &osc2_clk,
|
||||
}, { /* PL050 KMI1 */
|
||||
.dev_id = "10007000.kmi",
|
||||
.clk = &osc2_clk,
|
||||
}, { /* PL011 UART0 */
|
||||
.dev_id = "10009000.uart",
|
||||
.clk = &osc2_clk,
|
||||
}, { /* PL011 UART1 */
|
||||
.dev_id = "1000a000.uart",
|
||||
.clk = &osc2_clk,
|
||||
}, { /* PL011 UART2 */
|
||||
.dev_id = "1000b000.uart",
|
||||
.clk = &osc2_clk,
|
||||
}, { /* PL011 UART3 */
|
||||
.dev_id = "1000c000.uart",
|
||||
.clk = &osc2_clk,
|
||||
}, { /* SP805 WDT */
|
||||
.dev_id = "1000f000.wdt",
|
||||
.clk = &v2m_ref_clk,
|
||||
}, { /* PL111 CLCD */
|
||||
.dev_id = "1001f000.clcd",
|
||||
.clk = &osc1_clk,
|
||||
},
|
||||
};
|
||||
|
||||
void __init v2m_dt_init_early(void)
|
||||
{
|
||||
struct device_node *node;
|
||||
u32 dt_hbi;
|
||||
|
||||
node = of_find_compatible_node(NULL, NULL, "arm,vexpress-sysreg");
|
||||
v2m_sysreg_base = of_iomap(node, 0);
|
||||
if (WARN_ON(!v2m_sysreg_base))
|
||||
return;
|
||||
|
||||
/* Confirm board type against DT property, if available */
|
||||
if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) {
|
||||
u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
|
||||
u32 id = readl(v2m_sysreg_base + (misc & SYS_MISC_MASTERSITE ?
|
||||
V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
|
||||
u32 hbi = id & SYS_PROCIDx_HBI_MASK;
|
||||
|
||||
if (WARN_ON(dt_hbi != hbi))
|
||||
pr_warning("vexpress: DT HBI (%x) is not matching "
|
||||
"hardware (%x)!\n", dt_hbi, hbi);
|
||||
}
|
||||
|
||||
clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups));
|
||||
versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
|
||||
}
|
||||
|
||||
static struct of_device_id vexpress_irq_match[] __initdata = {
|
||||
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
|
||||
{}
|
||||
};
|
||||
|
||||
static void __init v2m_dt_init_irq(void)
|
||||
{
|
||||
of_irq_init(vexpress_irq_match);
|
||||
}
|
||||
|
||||
static void __init v2m_dt_timer_init(void)
|
||||
{
|
||||
struct device_node *node;
|
||||
const char *path;
|
||||
int err;
|
||||
|
||||
node = of_find_compatible_node(NULL, NULL, "arm,sp810");
|
||||
v2m_sysctl_init(of_iomap(node, 0));
|
||||
|
||||
err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
|
||||
if (WARN_ON(err))
|
||||
return;
|
||||
node = of_find_node_by_path(path);
|
||||
v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
|
||||
}
|
||||
|
||||
static struct sys_timer v2m_dt_timer = {
|
||||
.init = v2m_dt_timer_init,
|
||||
};
|
||||
|
||||
static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
|
||||
OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
|
||||
&v2m_flash_data),
|
||||
OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
|
||||
{}
|
||||
};
|
||||
|
||||
static void __init v2m_dt_init(void)
|
||||
{
|
||||
l2x0_of_init(0x00400000, 0xfe0fffff);
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
v2m_dt_auxdata_lookup, NULL);
|
||||
pm_power_off = v2m_power_off;
|
||||
}
|
||||
|
||||
const static char *v2m_dt_match[] __initconst = {
|
||||
"arm,vexpress",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
|
||||
.dt_compat = v2m_dt_match,
|
||||
.map_io = v2m_dt_map_io,
|
||||
.init_early = v2m_dt_init_early,
|
||||
.init_irq = v2m_dt_init_irq,
|
||||
.timer = &v2m_dt_timer,
|
||||
.init_machine = v2m_dt_init,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.restart = v2m_restart,
|
||||
MACHINE_END
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Reference in New Issue