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[PATCH] powerpc: More serial probe fixes (#2) 

This fixes the new serial probe code with some PCI MMIO UARTs, and fixes
CHRP build with ARCH=powerpc.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Benjamin Herrenschmidt 2005-11-29 11:21:59 +11:00 committed by Paul Mackerras
parent 1c3eb62910
commit 8dacaedf04
2 changed files with 34 additions and 27 deletions
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45
arch/powerpc/kernel/legacy_serial.c
View File

@ -38,15 +38,13 @@ static int __init add_legacy_port(struct device_node *np, int want_index,
int iotype, phys_addr_t base,
phys_addr_t taddr, unsigned long irq)
{
u32 *clk, *spd, clock;
u32 *clk, *spd, clock = BASE_BAUD * 16;
int index;
/* get clock freq. if present */
clk = (u32 *)get_property(np, "clock-frequency", NULL);
if (clk && *clk)
clock = *clk;
else
clock = BASE_BAUD * 16;
/* get default speed if present */
spd = (u32 *)get_property(np, "current-speed", NULL);
@ -88,7 +86,7 @@ static int __init add_legacy_port(struct device_node *np, int want_index,
if (iotype == UPIO_PORT)
legacy_serial_ports[index].iobase = base;
else
legacy_serial_ports[index].membase = (void __iomem *)base;
legacy_serial_ports[index].mapbase = base;
legacy_serial_ports[index].iotype = iotype;
legacy_serial_ports[index].uartclk = clock;
legacy_serial_ports[index].irq = irq;
@ -148,17 +146,17 @@ static int __init add_legacy_pci_port(struct device_node *np,
{
phys_addr_t addr, base;
u32 *addrp;
int iotype, index = -1;
int iotype, index = -1, lindex = 0;
#if 0
/* We only support ports that have a clock frequency properly
* encoded in the device-tree (that is have an fcode). Anything
* else can't be used that early and will be normally probed by
* the generic 8250_pci driver later on.
* the generic 8250_pci driver later on. The reason is that 8250
* compatible UARTs on PCI need all sort of quirks (port offsets
* etc...) that this code doesn't know about
*/
if (get_property(np, "clock-frequency", NULL) == NULL)
return -1;
#endif
/* Get the PCI address. Assume BAR 0 */
addrp = of_get_pci_address(pci_dev, 0, NULL);
@ -183,7 +181,23 @@ static int __init add_legacy_pci_port(struct device_node *np,
if (np != pci_dev) {
u32 *reg = (u32 *)get_property(np, "reg", NULL);
if (reg && (*reg < 4))
index = legacy_serial_count + *reg;
index = lindex = *reg;
}
/* Local index means it's the Nth port in the PCI chip. Unfortunately
* the offset to add here is device specific. We know about those
* EXAR ports and we default to the most common case. If your UART
* doesn't work for these settings, you'll have to add your own special
* cases here
*/
if (device_is_compatible(pci_dev, "pci13a8,152") ||
device_is_compatible(pci_dev, "pci13a8,154") ||
device_is_compatible(pci_dev, "pci13a8,158")) {
addr += 0x200 * lindex;
base += 0x200 * lindex;
} else {
addr += 8 * lindex;
base += 8 * lindex;
}
/* Add port, irq will be dealt with later. We passed a translated
@ -264,7 +278,6 @@ void __init find_legacy_serial_ports(void)
DBG("legacy_serial_console = %d\n", legacy_serial_console);
/* udbg is 64 bits only for now, that will change soon though ... */
#ifdef CONFIG_PPC64
while (legacy_serial_console >= 0) {
struct legacy_serial_info *info =
&legacy_serial_infos[legacy_serial_console];
@ -281,7 +294,6 @@ void __init find_legacy_serial_ports(void)
udbg_init_uart(addr, info->speed, info->clock);
break;
}
#endif /* CONFIG_PPC64 */
DBG(" <- find_legacy_serial_port()\n");
}
@ -343,6 +355,15 @@ static void __init fixup_port_pio(int index,
}
}
static void __init fixup_port_mmio(int index,
struct device_node *np,
struct plat_serial8250_port *port)
{
DBG("fixup_port_mmio(%d)\n", index);
port->membase = ioremap(port->mapbase, 0x100);
}
/*
* This is called as an arch initcall, hopefully before the PCI bus is
* probed and/or the 8250 driver loaded since we need to register our
@ -377,6 +398,8 @@ static int __init serial_dev_init(void)
fixup_port_irq(i, np, port);
if (port->iotype == UPIO_PORT)
fixup_port_pio(i, np, port);
if (port->iotype == UPIO_MEM)
fixup_port_mmio(i, np, port);
}
DBG("Registering platform serial ports\n");

16
arch/powerpc/platforms/chrp/setup.c
View File

@ -49,7 +49,6 @@
#include <asm/hydra.h>
#include <asm/sections.h>
#include <asm/time.h>
#include <asm/btext.h>
#include <asm/i8259.h>
#include <asm/mpic.h>
#include <asm/rtas.h>
@ -58,7 +57,6 @@
#include "chrp.h"
void rtas_indicator_progress(char *, unsigned short);
void btext_progress(char *, unsigned short);
int _chrp_type;
EXPORT_SYMBOL(_chrp_type);
@ -264,11 +262,6 @@ void __init chrp_setup_arch(void)
ppc_md.set_rtc_time = rtas_set_rtc_time;
}
#ifdef CONFIG_BOOTX_TEXT
if (ppc_md.progress == NULL && boot_text_mapped)
ppc_md.progress = btext_progress;
#endif
#ifdef CONFIG_BLK_DEV_INITRD
/* this is fine for chrp */
initrd_below_start_ok = 1;
@ -522,12 +515,3 @@ void __init chrp_init(void)
smp_ops = &chrp_smp_ops;
#endif /* CONFIG_SMP */
}
#ifdef CONFIG_BOOTX_TEXT
void
btext_progress(char *s, unsigned short hex)
{
btext_drawstring(s);
btext_drawstring("\n");
}
#endif /* CONFIG_BOOTX_TEXT */