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ARM: 7023/1: L2x0: Add interrupts property to OF binding 

Following the discussion here:
http://lists.ozlabs.org/pipermail/devicetree-discuss/2011-August/007301.html

The L2x0 L2 Cache Controllers support a combined interrupt line
which can be used for several events (e.g. read/write/parity errors on
tag/data RAM, event counter increment/overflow). Unfortunately the
OF binding added in c519ecf2 ("ARM: 7009/1: l2x0: Add OF based
initialization") does not represent the interrupt.

This patch adds an "interrupts" property to the L2x0 OF binding,
representing the combined interrupt line.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Barry Song <21cnbao@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Mark Rutland 2011-08-17 18:03:17 +01:00 committed by Russell King
parent 74d41f39a9
commit 8d4e652d1b
1 changed files with 2 additions and 0 deletions
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2
Documentation/devicetree/bindings/arm/l2cc.txt
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@ -28,6 +28,7 @@ Optional properties:
- arm,filter-ranges : <start length> Starting address and length of window to - arm,filter-ranges : <start length> Starting address and length of window to
filter. Addresses in the filter window are directed to the M1 port. Other filter. Addresses in the filter window are directed to the M1 port. Other
addresses will go to the M0 port. addresses will go to the M0 port.
- interrupts : 1 combined interrupt.
Example: Example:
@ -39,4 +40,5 @@ L2: cache-controller {
arm,filter-latency = <0x80000000 0x8000000>; arm,filter-latency = <0x80000000 0x8000000>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
interrupts = <45>;
}; };