x86_64: introduce CalIOC2 support
CalIOC2 is a PCI-e implementation of the Calgary logic. Most of the programming details are the same, but some differ, e.g., TCE cache flush. This patch introduces CalIOC2 support - detection and various support routines. It's not expected to work yet (but will with follow-on patches). Signed-off-by: Muli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Muli Ben-Yehuda
Linus Torvalds
parent
35b6dfa087
commit
8a244590ca
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@ -50,8 +50,7 @@ int use_calgary __read_mostly = 0;
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#endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
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#define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
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#define PCI_VENDOR_DEVICE_ID_CALGARY \
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(PCI_VENDOR_ID_IBM | PCI_DEVICE_ID_IBM_CALGARY << 16)
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#define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
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/* we need these for register space address calculation */
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#define START_ADDRESS 0xfe000000
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@ -193,6 +192,7 @@ static inline unsigned long verify_bit_range(unsigned long* bitmap,
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{
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return ~0UL;
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}
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#endif /* CONFIG_IOMMU_DEBUG */
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static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
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@ -346,9 +346,20 @@ static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
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static inline struct iommu_table *find_iommu_table(struct device *dev)
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{
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struct pci_dev *pdev;
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struct pci_bus *pbus;
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struct iommu_table *tbl;
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tbl = to_pci_dev(dev)->bus->self->sysdata;
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pdev = to_pci_dev(dev);
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/* is the device behind a bridge? */
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if (unlikely(pdev->bus->parent))
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pbus = pdev->bus->parent;
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else
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pbus = pdev->bus;
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tbl = pbus->self->sysdata;
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BUG_ON(pdev->bus->parent && (tbl->it_busno != pdev->bus->parent->number));
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return tbl;
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}
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@ -565,6 +576,21 @@ static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
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return (void __iomem*)target;
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}
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static inline int is_calioc2(unsigned short device)
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{
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return (device == PCI_DEVICE_ID_IBM_CALIOC2);
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}
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static inline int is_calgary(unsigned short device)
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{
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return (device == PCI_DEVICE_ID_IBM_CALGARY);
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}
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static inline int is_cal_pci_dev(unsigned short device)
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{
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return (is_calgary(device) || is_calioc2(device));
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}
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static void calgary_tce_cache_blast(struct iommu_table *tbl)
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{
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u64 val;
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@ -685,8 +711,14 @@ static void __init calgary_reserve_regions(struct pci_dev *dev)
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iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
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/* avoid the BIOS/VGA first 640KB-1MB region */
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start = (640 * 1024);
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npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
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/* for CalIOC2 - avoid the entire first 2MB */
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if (is_calgary(dev->device)) {
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start = (640 * 1024);
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npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
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} else { /* calioc2 */
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start = 0;
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npages = (2 * 1024 * 1024) >> PAGE_SHIFT;
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}
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iommu_range_reserve(tbl, start, npages);
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/* reserve the two PCI peripheral memory regions in IO space */
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@ -721,15 +753,15 @@ static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
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/* zero out all TAR bits under sw control */
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val64 &= ~TAR_SW_BITS;
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tbl = dev->sysdata;
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table_phys = (u64)__pa(tbl->it_base);
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val64 |= table_phys;
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BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
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val64 |= (u64) specified_table_size;
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tbl->tar_val = cpu_to_be64(val64);
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writeq(tbl->tar_val, target);
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readq(target); /* flush */
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@ -760,6 +792,43 @@ static void __init calgary_free_bus(struct pci_dev *dev)
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bus_info[dev->bus->number].tce_space = NULL;
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}
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static void calgary_dump_error_regs(struct iommu_table *tbl)
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{
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void __iomem *bbar = tbl->bbar;
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u32 csr, csmr, plssr, mck;
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void __iomem *target;
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unsigned long phboff = phb_offset(tbl->it_busno);
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unsigned long erroff;
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u32 errregs[7];
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int i;
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/* dump CSR */
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target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
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csr = be32_to_cpu(readl(target));
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/* dump PLSSR */
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target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
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plssr = be32_to_cpu(readl(target));
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/* dump CSMR */
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target = calgary_reg(bbar, phboff | 0x290);
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csmr = be32_to_cpu(readl(target));
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/* dump mck */
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target = calgary_reg(bbar, phboff | 0x800);
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mck = be32_to_cpu(readl(target));
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printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR "
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"0x%08x@MCK\n", csr, plssr, csmr, mck);
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/* dump rest of error regs */
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printk(KERN_EMERG "Calgary: ");
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for (i = 0; i < ARRAY_SIZE(errregs); i++) {
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erroff = (0x810 + (i * 0x10)); /* err regs are at 0x810 - 0x870 */
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target = calgary_reg(bbar, phboff | erroff);
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errregs[i] = be32_to_cpu(readl(target));
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printk("0x%08x@0x%lx ", errregs[i], erroff);
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}
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printk("\n");
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}
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static void calgary_watchdog(unsigned long data)
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{
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struct pci_dev *dev = (struct pci_dev *)data;
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@ -773,13 +842,16 @@ static void calgary_watchdog(unsigned long data)
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/* If no error, the agent ID in the CSR is not valid */
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if (val32 & CSR_AGENT_MASK) {
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printk(KERN_EMERG "calgary_watchdog: DMA error on PHB %#x, "
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"CSR = %#x\n", dev->bus->number, val32);
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printk(KERN_EMERG "Calgary: DMA error on PHB %#x\n",
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dev->bus->number);
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calgary_dump_error_regs(tbl);
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/* reset error */
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writel(0, target);
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/* Disable bus that caused the error */
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target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
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PHB_CONFIG_RW_OFFSET);
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PHB_CONFIG_RW_OFFSET);
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val32 = be32_to_cpu(readl(target));
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val32 |= PHB_SLOT_DISABLE;
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writel(cpu_to_be32(val32), target);
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@ -853,7 +925,9 @@ static void __init calgary_enable_translation(struct pci_dev *dev)
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val32 = be32_to_cpu(readl(target));
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val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
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printk(KERN_INFO "Calgary: enabling translation on PHB %#x\n", busnum);
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printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
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(dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
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"Calgary" : "CalIOC2", busnum);
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printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
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"bus.\n");
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@ -894,7 +968,12 @@ static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
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{
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pci_dev_get(dev);
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dev->sysdata = NULL;
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dev->bus->self = dev;
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/* is the device behind a bridge? */
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if (dev->bus->parent)
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dev->bus->parent->self = dev;
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else
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dev->bus->self = dev;
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}
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static int __init calgary_init_one(struct pci_dev *dev)
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@ -911,7 +990,14 @@ static int __init calgary_init_one(struct pci_dev *dev)
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goto done;
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pci_dev_get(dev);
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dev->bus->self = dev;
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if (dev->bus->parent) {
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if (dev->bus->parent->self)
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printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
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"bus->parent->self!\n", dev);
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dev->bus->parent->self = dev;
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} else
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dev->bus->self = dev;
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tbl = dev->sysdata;
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tbl->chip_ops->handle_quirks(tbl, dev);
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@ -951,11 +1037,18 @@ static int __init calgary_locate_bbars(void)
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target = calgary_reg(bbar, offset);
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val = be32_to_cpu(readl(target));
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start_bus = (u8)((val & 0x00FF0000) >> 16);
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end_bus = (u8)((val & 0x0000FF00) >> 8);
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for (bus = start_bus; bus <= end_bus; bus++) {
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bus_info[bus].bbar = bbar;
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bus_info[bus].phbid = phb;
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if (end_bus) {
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for (bus = start_bus; bus <= end_bus; bus++) {
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bus_info[bus].bbar = bbar;
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bus_info[bus].phbid = phb;
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}
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} else {
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bus_info[start_bus].bbar = bbar;
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bus_info[start_bus].phbid = phb;
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}
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}
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}
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@ -975,24 +1068,27 @@ static int __init calgary_init(void)
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{
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int ret;
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struct pci_dev *dev = NULL;
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void* tce_space;
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ret = calgary_locate_bbars();
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if (ret)
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return ret;
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do {
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dev = pci_get_device(PCI_VENDOR_ID_IBM,
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PCI_DEVICE_ID_IBM_CALGARY,
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dev);
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dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
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if (!dev)
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break;
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if (!is_cal_pci_dev(dev->device))
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continue;
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if (!translate_phb(dev)) {
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calgary_init_one_nontraslated(dev);
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continue;
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}
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if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
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tce_space = bus_info[dev->bus->number].tce_space;
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if (!tce_space && !translate_empty_slots) {
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printk("Calg: %p failed tce_space check\n", dev);
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continue;
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}
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ret = calgary_init_one(dev);
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if (ret)
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goto error;
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@ -1003,10 +1099,11 @@ static int __init calgary_init(void)
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error:
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do {
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dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM,
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PCI_DEVICE_ID_IBM_CALGARY,
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dev);
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PCI_ANY_ID, dev);
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if (!dev)
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break;
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if (!is_cal_pci_dev(dev->device))
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continue;
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if (!translate_phb(dev)) {
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pci_dev_put(dev);
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continue;
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@ -1084,9 +1181,29 @@ static int __init build_detail_arrays(void)
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return 0;
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}
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static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
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{
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int dev;
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u32 val;
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if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
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/*
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* FIXME: properly scan for devices accross the
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* PCI-to-PCI bridge on every CalIOC2 port.
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*/
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return 1;
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}
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for (dev = 1; dev < 8; dev++) {
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val = read_pci_config(bus, dev, 0, 0);
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if (val != 0xffffffff)
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break;
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}
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return (val != 0xffffffff);
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}
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void __init detect_calgary(void)
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{
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u32 val;
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int bus;
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void *tbl;
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int calgary_found = 0;
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@ -1143,29 +1260,28 @@ void __init detect_calgary(void)
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specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
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for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
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int dev;
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struct calgary_bus_info *info = &bus_info[bus];
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unsigned short pci_device;
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u32 val;
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if (read_pci_config(bus, 0, 0, 0) != PCI_VENDOR_DEVICE_ID_CALGARY)
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val = read_pci_config(bus, 0, 0, 0);
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pci_device = (val & 0xFFFF0000) >> 16;
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if (!is_cal_pci_dev(pci_device))
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continue;
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if (info->translation_disabled)
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continue;
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/*
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* Scan the slots of the PCI bus to see if there is a device present.
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* The parent bus will be the zero-ith device, so start at 1.
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*/
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for (dev = 1; dev < 8; dev++) {
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val = read_pci_config(bus, dev, 0, 0);
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if (val != 0xffffffff || translate_empty_slots) {
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tbl = alloc_tce_table();
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if (!tbl)
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goto cleanup;
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info->tce_space = tbl;
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calgary_found = 1;
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break;
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}
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if (calgary_bus_has_devices(bus, pci_device) ||
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translate_empty_slots) {
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tbl = alloc_tce_table();
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if (!tbl)
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goto cleanup;
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info->tce_space = tbl;
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calgary_found = 1;
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printk("Calg: allocated tce_table %p for bus 0x%x\n",
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info->tce_space, bus);
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}
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}
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