drm/nvc0: initial vm implementation, use for bar1/bar3 management
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
4c74eb7ff2
commit
8984e04615
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@ -28,7 +28,8 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
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nv10_gpio.o nv50_gpio.o \
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nv50_calc.o \
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nv04_pm.o nv50_pm.o nva3_pm.o \
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nv50_vram.o nv50_vm.o nvc0_vm.o
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nv50_vram.o nvc0_vram.o \
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nv50_vm.o nvc0_vm.o
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nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o
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nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o
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@ -120,6 +120,9 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
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align >>= PAGE_SHIFT;
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if (!nvbo->no_vm && dev_priv->chan_vm) {
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if (dev_priv->card_type == NV_C0)
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page_shift = 12;
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ret = nouveau_vm_get(dev_priv->chan_vm, size, page_shift,
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NV_MEM_ACCESS_RW, &nvbo->vma);
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if (ret) {
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@ -413,7 +416,7 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
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man->default_caching = TTM_PL_FLAG_CACHED;
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break;
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case TTM_PL_VRAM:
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if (dev_priv->card_type == NV_50) {
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if (dev_priv->card_type >= NV_50) {
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man->func = &nouveau_vram_manager;
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man->io_reserve_fastpath = false;
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man->use_io_reserve_lru = true;
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@ -901,6 +904,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
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case TTM_PL_VRAM:
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{
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struct nouveau_vram *vram = mem->mm_node;
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u8 page_shift;
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if (!dev_priv->bar1_vm) {
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mem->bus.offset = mem->start << PAGE_SHIFT;
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@ -909,8 +913,13 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
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break;
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}
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if (dev_priv->card_type == NV_C0)
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page_shift = vram->page_shift;
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else
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page_shift = 12;
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ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size,
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vram->page_shift, NV_MEM_ACCESS_RW,
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page_shift, NV_MEM_ACCESS_RW,
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&vram->bar_vma);
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if (ret)
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return ret;
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@ -921,8 +930,9 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
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return ret;
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}
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mem->bus.offset = vram->bar_vma.offset;
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mem->bus.offset -= 0x0020000000ULL;
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mem->bus.offset = vram->bar_vma.offset;
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if (dev_priv->card_type == NV_50) /*XXX*/
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mem->bus.offset -= 0x0020000000ULL;
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mem->bus.base = pci_resource_start(dev->pdev, 1);
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mem->bus.is_iomem = true;
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}
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@ -842,6 +842,9 @@ extern void nv10_mem_put_tile_region(struct drm_device *dev,
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struct nouveau_fence *fence);
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extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
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/* nvc0_vram.c */
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extern const struct ttm_mem_type_manager_func nvc0_vram_manager;
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/* nouveau_notifier.c */
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extern int nouveau_notifier_init_channel(struct nouveau_channel *);
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extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
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@ -1229,11 +1232,6 @@ extern int nvc0_instmem_init(struct drm_device *);
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extern void nvc0_instmem_takedown(struct drm_device *);
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extern int nvc0_instmem_suspend(struct drm_device *);
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extern void nvc0_instmem_resume(struct drm_device *);
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extern int nvc0_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
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extern void nvc0_instmem_put(struct nouveau_gpuobj *);
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extern int nvc0_instmem_map(struct nouveau_gpuobj *);
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extern void nvc0_instmem_unmap(struct nouveau_gpuobj *);
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extern void nvc0_instmem_flush(struct drm_device *);
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/* nv04_mc.c */
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extern int nv04_mc_init(struct drm_device *);
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@ -255,9 +255,6 @@ nouveau_mem_detect(struct drm_device *dev)
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if (dev_priv->card_type < NV_50) {
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dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
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dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
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} else {
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dev_priv->vram_size = nv_rd32(dev, 0x10f20c) << 20;
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dev_priv->vram_size *= nv_rd32(dev, 0x121c74);
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}
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if (dev_priv->vram_size)
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@ -59,4 +59,9 @@ int nv50_vram_new(struct drm_device *, u64 size, u32 align, u32 size_nc,
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void nv50_vram_del(struct drm_device *, struct nouveau_vram **);
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bool nv50_vram_flags_valid(struct drm_device *, u32 tile_flags);
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int nvc0_vram_init(struct drm_device *);
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int nvc0_vram_new(struct drm_device *, u64 size, u32 align, u32 ncmin,
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u32 memtype, struct nouveau_vram **);
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bool nvc0_vram_flags_valid(struct drm_device *, u32 tile_flags);
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#endif
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@ -464,11 +464,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->instmem.takedown = nvc0_instmem_takedown;
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engine->instmem.suspend = nvc0_instmem_suspend;
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engine->instmem.resume = nvc0_instmem_resume;
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engine->instmem.get = nvc0_instmem_get;
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engine->instmem.put = nvc0_instmem_put;
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engine->instmem.map = nvc0_instmem_map;
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engine->instmem.unmap = nvc0_instmem_unmap;
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engine->instmem.flush = nvc0_instmem_flush;
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engine->instmem.get = nv50_instmem_get;
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engine->instmem.put = nv50_instmem_put;
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engine->instmem.map = nv50_instmem_map;
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engine->instmem.unmap = nv50_instmem_unmap;
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engine->instmem.flush = nv84_instmem_flush;
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engine->mc.init = nv50_mc_init;
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engine->mc.takedown = nv50_mc_takedown;
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engine->timer.init = nv04_timer_init;
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@ -509,8 +509,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->gpio.irq_enable = nv50_gpio_irq_enable;
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engine->crypt.init = nouveau_stub_init;
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engine->crypt.takedown = nouveau_stub_takedown;
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engine->vram.init = nouveau_mem_detect;
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engine->vram.flags_valid = nouveau_mem_flags_valid;
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engine->vram.init = nvc0_vram_init;
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engine->vram.get = nvc0_vram_new;
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engine->vram.put = nv50_vram_del;
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engine->vram.flags_valid = nvc0_vram_flags_valid;
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break;
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default:
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NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
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@ -25,159 +25,21 @@
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_vm.h"
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struct nvc0_gpuobj_node {
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struct nouveau_bo *vram;
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struct drm_mm_node *ramin;
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u32 align;
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struct nvc0_instmem_priv {
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struct nouveau_gpuobj *bar1_pgd;
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struct nouveau_channel *bar1;
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struct nouveau_gpuobj *bar3_pgd;
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struct nouveau_channel *bar3;
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};
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int
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nvc0_instmem_get(struct nouveau_gpuobj *gpuobj, u32 size, u32 align)
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{
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struct drm_device *dev = gpuobj->dev;
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struct nvc0_gpuobj_node *node = NULL;
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int ret;
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node = kzalloc(sizeof(*node), GFP_KERNEL);
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if (!node)
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return -ENOMEM;
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node->align = align;
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ret = nouveau_bo_new(dev, NULL, size, align, TTM_PL_FLAG_VRAM,
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0, 0x0000, true, false, &node->vram);
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if (ret) {
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NV_ERROR(dev, "error getting PRAMIN backing pages: %d\n", ret);
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return ret;
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}
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ret = nouveau_bo_pin(node->vram, TTM_PL_FLAG_VRAM);
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if (ret) {
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NV_ERROR(dev, "error pinning PRAMIN backing VRAM: %d\n", ret);
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nouveau_bo_ref(NULL, &node->vram);
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return ret;
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}
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gpuobj->vinst = node->vram->bo.mem.start << PAGE_SHIFT;
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gpuobj->size = node->vram->bo.mem.num_pages << PAGE_SHIFT;
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gpuobj->node = node;
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return 0;
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}
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void
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nvc0_instmem_put(struct nouveau_gpuobj *gpuobj)
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{
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struct nvc0_gpuobj_node *node;
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node = gpuobj->node;
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gpuobj->node = NULL;
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nouveau_bo_unpin(node->vram);
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nouveau_bo_ref(NULL, &node->vram);
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kfree(node);
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}
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int
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nvc0_instmem_map(struct nouveau_gpuobj *gpuobj)
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{
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struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
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struct nvc0_gpuobj_node *node = gpuobj->node;
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struct drm_device *dev = gpuobj->dev;
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struct drm_mm_node *ramin = NULL;
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u32 pte, pte_end;
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u64 vram;
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do {
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if (drm_mm_pre_get(&dev_priv->ramin_heap))
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return -ENOMEM;
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spin_lock(&dev_priv->ramin_lock);
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ramin = drm_mm_search_free(&dev_priv->ramin_heap, gpuobj->size,
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node->align, 0);
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if (ramin == NULL) {
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spin_unlock(&dev_priv->ramin_lock);
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return -ENOMEM;
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}
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ramin = drm_mm_get_block_atomic(ramin, gpuobj->size, node->align);
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spin_unlock(&dev_priv->ramin_lock);
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} while (ramin == NULL);
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pte = (ramin->start >> 12) << 1;
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pte_end = ((ramin->size >> 12) << 1) + pte;
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vram = gpuobj->vinst;
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NV_DEBUG(dev, "pramin=0x%lx, pte=%d, pte_end=%d\n",
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ramin->start, pte, pte_end);
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NV_DEBUG(dev, "first vram page: 0x%010llx\n", gpuobj->vinst);
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while (pte < pte_end) {
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nv_wr32(dev, 0x702000 + (pte * 8), (vram >> 8) | 1);
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nv_wr32(dev, 0x702004 + (pte * 8), 0);
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vram += 4096;
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pte++;
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}
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dev_priv->engine.instmem.flush(dev);
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if (1) {
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u32 chan = nv_rd32(dev, 0x1700) << 16;
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nv_wr32(dev, 0x100cb8, (chan + 0x1000) >> 8);
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nv_wr32(dev, 0x100cbc, 0x80000005);
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}
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node->ramin = ramin;
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gpuobj->pinst = ramin->start;
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return 0;
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}
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void
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nvc0_instmem_unmap(struct nouveau_gpuobj *gpuobj)
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{
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struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
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struct nvc0_gpuobj_node *node = gpuobj->node;
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u32 pte, pte_end;
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if (!node->ramin || !dev_priv->ramin_available)
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return;
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pte = (node->ramin->start >> 12) << 1;
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pte_end = ((node->ramin->size >> 12) << 1) + pte;
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while (pte < pte_end) {
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nv_wr32(gpuobj->dev, 0x702000 + (pte * 8), 0);
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nv_wr32(gpuobj->dev, 0x702004 + (pte * 8), 0);
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pte++;
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}
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dev_priv->engine.instmem.flush(gpuobj->dev);
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spin_lock(&dev_priv->ramin_lock);
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drm_mm_put_block(node->ramin);
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node->ramin = NULL;
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spin_unlock(&dev_priv->ramin_lock);
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}
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void
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nvc0_instmem_flush(struct drm_device *dev)
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{
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nv_wr32(dev, 0x070000, 1);
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if (!nv_wait(dev, 0x070000, 0x00000002, 0x00000000))
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NV_ERROR(dev, "PRAMIN flush timeout\n");
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}
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int
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nvc0_instmem_suspend(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 *buf;
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int i;
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dev_priv->susres.ramin_copy = vmalloc(65536);
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if (!dev_priv->susres.ramin_copy)
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return -ENOMEM;
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buf = dev_priv->susres.ramin_copy;
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for (i = 0; i < 65536; i += 4)
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buf[i/4] = nv_rd32(dev, NV04_PRAMIN + i);
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dev_priv->ramin_available = false;
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return 0;
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}
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@ -185,73 +47,169 @@ void
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nvc0_instmem_resume(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 *buf = dev_priv->susres.ramin_copy;
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u64 chan;
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int i;
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struct nvc0_instmem_priv *priv = dev_priv->engine.instmem.priv;
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chan = dev_priv->vram_size - dev_priv->ramin_rsvd_vram;
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nv_wr32(dev, 0x001700, chan >> 16);
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nv_mask(dev, 0x100c80, 0x00000001, 0x00000000);
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nv_wr32(dev, 0x001704, 0x80000000 | priv->bar1->ramin->vinst >> 12);
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nv_wr32(dev, 0x001714, 0xc0000000 | priv->bar3->ramin->vinst >> 12);
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dev_priv->ramin_available = true;
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}
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for (i = 0; i < 65536; i += 4)
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nv_wr32(dev, NV04_PRAMIN + i, buf[i/4]);
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vfree(dev_priv->susres.ramin_copy);
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dev_priv->susres.ramin_copy = NULL;
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static void
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nvc0_channel_del(struct nouveau_channel **pchan)
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{
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struct nouveau_channel *chan;
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nv_wr32(dev, 0x001714, 0xc0000000 | (chan >> 12));
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chan = *pchan;
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*pchan = NULL;
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if (!chan)
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return;
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nouveau_vm_ref(NULL, &chan->vm, NULL);
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if (chan->ramin_heap.free_stack.next)
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drm_mm_takedown(&chan->ramin_heap);
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nouveau_gpuobj_ref(NULL, &chan->ramin);
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kfree(chan);
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}
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static int
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nvc0_channel_new(struct drm_device *dev, u32 size, struct nouveau_vm *vm,
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struct nouveau_channel **pchan,
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struct nouveau_gpuobj *pgd, u64 vm_size)
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{
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struct nouveau_channel *chan;
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int ret;
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chan = kzalloc(sizeof(*chan), GFP_KERNEL);
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if (!chan)
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return -ENOMEM;
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chan->dev = dev;
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ret = nouveau_gpuobj_new(dev, NULL, size, 0x1000, 0, &chan->ramin);
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if (ret) {
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nvc0_channel_del(&chan);
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return ret;
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}
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ret = drm_mm_init(&chan->ramin_heap, 0x1000, size - 0x1000);
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if (ret) {
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nvc0_channel_del(&chan);
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return ret;
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}
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ret = nouveau_vm_ref(vm, &chan->vm, NULL);
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if (ret) {
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nvc0_channel_del(&chan);
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return ret;
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}
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nv_wo32(chan->ramin, 0x0200, lower_32_bits(pgd->vinst));
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nv_wo32(chan->ramin, 0x0204, upper_32_bits(pgd->vinst));
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nv_wo32(chan->ramin, 0x0208, lower_32_bits(vm_size - 1));
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nv_wo32(chan->ramin, 0x020c, upper_32_bits(vm_size - 1));
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*pchan = chan;
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return 0;
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}
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int
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nvc0_instmem_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u64 chan, pgt3, imem, lim3 = dev_priv->ramin_size - 1;
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int ret, i;
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struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
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struct pci_dev *pdev = dev->pdev;
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struct nvc0_instmem_priv *priv;
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struct nouveau_vm *vm = NULL;
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int ret;
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dev_priv->ramin_rsvd_vram = 1 * 1024 * 1024;
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chan = dev_priv->vram_size - dev_priv->ramin_rsvd_vram;
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imem = 4096 + 4096 + 32768;
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nv_wr32(dev, 0x001700, chan >> 16);
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/* channel setup */
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nv_wr32(dev, 0x700200, lower_32_bits(chan + 0x1000));
|
||||
nv_wr32(dev, 0x700204, upper_32_bits(chan + 0x1000));
|
||||
nv_wr32(dev, 0x700208, lower_32_bits(lim3));
|
||||
nv_wr32(dev, 0x70020c, upper_32_bits(lim3));
|
||||
|
||||
/* point pgd -> pgt */
|
||||
nv_wr32(dev, 0x701000, 0);
|
||||
nv_wr32(dev, 0x701004, ((chan + 0x2000) >> 8) | 1);
|
||||
|
||||
/* point pgt -> physical vram for channel */
|
||||
pgt3 = 0x2000;
|
||||
for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4096, pgt3 += 8) {
|
||||
nv_wr32(dev, 0x700000 + pgt3, ((chan + i) >> 8) | 1);
|
||||
nv_wr32(dev, 0x700004 + pgt3, 0);
|
||||
}
|
||||
|
||||
/* clear rest of pgt */
|
||||
for (; i < dev_priv->ramin_size; i += 4096, pgt3 += 8) {
|
||||
nv_wr32(dev, 0x700000 + pgt3, 0);
|
||||
nv_wr32(dev, 0x700004 + pgt3, 0);
|
||||
}
|
||||
|
||||
/* point bar3 at the channel */
|
||||
nv_wr32(dev, 0x001714, 0xc0000000 | (chan >> 12));
|
||||
|
||||
/* Global PRAMIN heap */
|
||||
ret = drm_mm_init(&dev_priv->ramin_heap, imem,
|
||||
dev_priv->ramin_size - imem);
|
||||
if (ret) {
|
||||
NV_ERROR(dev, "Failed to init RAMIN heap\n");
|
||||
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
}
|
||||
pinstmem->priv = priv;
|
||||
|
||||
/* BAR3 VM */
|
||||
ret = nouveau_vm_new(dev, 0, pci_resource_len(pdev, 3), 0,
|
||||
&dev_priv->bar3_vm);
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
ret = nouveau_gpuobj_new(dev, NULL,
|
||||
(pci_resource_len(pdev, 3) >> 12) * 8, 0,
|
||||
NVOBJ_FLAG_DONT_MAP |
|
||||
NVOBJ_FLAG_ZERO_ALLOC,
|
||||
&dev_priv->bar3_vm->pgt[0].obj[0]);
|
||||
if (ret)
|
||||
goto error;
|
||||
dev_priv->bar3_vm->pgt[0].refcount[0] = 1;
|
||||
|
||||
nv50_instmem_map(dev_priv->bar3_vm->pgt[0].obj[0]);
|
||||
|
||||
ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 4096,
|
||||
NVOBJ_FLAG_ZERO_ALLOC, &priv->bar3_pgd);
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
ret = nouveau_vm_ref(dev_priv->bar3_vm, &vm, priv->bar3_pgd);
|
||||
if (ret)
|
||||
goto error;
|
||||
nouveau_vm_ref(NULL, &vm, NULL);
|
||||
|
||||
ret = nvc0_channel_new(dev, 8192, dev_priv->bar3_vm, &priv->bar3,
|
||||
priv->bar3_pgd, pci_resource_len(dev->pdev, 3));
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
/* BAR1 VM */
|
||||
ret = nouveau_vm_new(dev, 0, pci_resource_len(pdev, 1), 0, &vm);
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 4096,
|
||||
NVOBJ_FLAG_ZERO_ALLOC, &priv->bar1_pgd);
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
ret = nouveau_vm_ref(vm, &dev_priv->bar1_vm, priv->bar1_pgd);
|
||||
if (ret)
|
||||
goto error;
|
||||
nouveau_vm_ref(NULL, &vm, NULL);
|
||||
|
||||
ret = nvc0_channel_new(dev, 8192, dev_priv->bar1_vm, &priv->bar1,
|
||||
priv->bar1_pgd, pci_resource_len(dev->pdev, 1));
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
nvc0_instmem_resume(dev);
|
||||
return 0;
|
||||
error:
|
||||
nvc0_instmem_takedown(dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
void
|
||||
nvc0_instmem_takedown(struct drm_device *dev)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
struct nvc0_instmem_priv *priv = dev_priv->engine.instmem.priv;
|
||||
struct nouveau_vm *vm = NULL;
|
||||
|
||||
nvc0_instmem_suspend(dev);
|
||||
|
||||
nv_wr32(dev, 0x1704, 0x00000000);
|
||||
nv_wr32(dev, 0x1714, 0x00000000);
|
||||
|
||||
nvc0_channel_del(&priv->bar1);
|
||||
nouveau_vm_ref(NULL, &dev_priv->bar1_vm, priv->bar1_pgd);
|
||||
nouveau_gpuobj_ref(NULL, &priv->bar1_pgd);
|
||||
|
||||
nvc0_channel_del(&priv->bar3);
|
||||
nouveau_vm_ref(dev_priv->bar3_vm, &vm, NULL);
|
||||
nouveau_vm_ref(NULL, &vm, priv->bar3_pgd);
|
||||
nouveau_gpuobj_ref(NULL, &priv->bar3_pgd);
|
||||
nouveau_gpuobj_ref(NULL, &dev_priv->bar3_vm->pgt[0].obj[0]);
|
||||
nouveau_vm_ref(NULL, &dev_priv->bar3_vm, NULL);
|
||||
|
||||
dev_priv->engine.instmem.priv = NULL;
|
||||
kfree(priv);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,91 @@
|
|||
/*
|
||||
* Copyright 2010 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
|
||||
#include "drmP.h"
|
||||
#include "nouveau_drv.h"
|
||||
#include "nouveau_mm.h"
|
||||
|
||||
bool
|
||||
nvc0_vram_flags_valid(struct drm_device *dev, u32 tile_flags)
|
||||
{
|
||||
if (likely(!(tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)))
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
int
|
||||
nvc0_vram_new(struct drm_device *dev, u64 size, u32 align, u32 ncmin,
|
||||
u32 type, struct nouveau_vram **pvram)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
|
||||
struct ttm_mem_type_manager *man = &bdev->man[TTM_PL_VRAM];
|
||||
struct nouveau_mm *mm = man->priv;
|
||||
struct nouveau_mm_node *r;
|
||||
struct nouveau_vram *vram;
|
||||
int ret;
|
||||
|
||||
size >>= 12;
|
||||
align >>= 12;
|
||||
ncmin >>= 12;
|
||||
|
||||
vram = kzalloc(sizeof(*vram), GFP_KERNEL);
|
||||
if (!vram)
|
||||
return -ENOMEM;
|
||||
|
||||
INIT_LIST_HEAD(&vram->regions);
|
||||
vram->dev = dev_priv->dev;
|
||||
vram->memtype = type;
|
||||
vram->size = size;
|
||||
|
||||
mutex_lock(&mm->mutex);
|
||||
do {
|
||||
ret = nouveau_mm_get(mm, 1, size, ncmin, align, &r);
|
||||
if (ret) {
|
||||
mutex_unlock(&mm->mutex);
|
||||
nv50_vram_del(dev, &vram);
|
||||
return ret;
|
||||
}
|
||||
|
||||
list_add_tail(&r->rl_entry, &vram->regions);
|
||||
size -= r->length;
|
||||
} while (size);
|
||||
mutex_unlock(&mm->mutex);
|
||||
|
||||
r = list_first_entry(&vram->regions, struct nouveau_mm_node, rl_entry);
|
||||
vram->offset = (u64)r->offset << 12;
|
||||
*pvram = vram;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
nvc0_vram_init(struct drm_device *dev)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
|
||||
dev_priv->vram_size = nv_rd32(dev, 0x10f20c) << 20;
|
||||
dev_priv->vram_size *= nv_rd32(dev, 0x121c74);
|
||||
dev_priv->vram_rblock_size = 4096;
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue