ath9k_hw: Add IQ cal changes for AR9485
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Vasanthakumar Thiagarajan
John W. Linville
parent
31faff815b
commit
858b7e36e8
2 changed files with 255 additions and 3 deletions
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@ -18,6 +18,16 @@
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#include "hw-ops.h"
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#include "ar9003_phy.h"
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#define MPASS 3
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#define MAX_MEASUREMENT 8
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#define MAX_DIFFERENCE 10
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struct coeff {
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int mag_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MPASS];
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int phs_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MPASS];
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int iqc_coeff[2];
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};
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enum ar9003_cal_types {
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IQ_MISMATCH_CAL = BIT(0),
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TEMP_COMP_CAL = BIT(1),
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@ -712,6 +722,229 @@ TX_IQ_CAL_FAILED:
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ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
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}
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static bool ar9003_hw_compute_closest_pass_and_avg(int *mp_coeff, int *mp_avg)
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{
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int diff[MPASS];
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diff[0] = abs(mp_coeff[0] - mp_coeff[1]);
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diff[1] = abs(mp_coeff[1] - mp_coeff[2]);
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diff[2] = abs(mp_coeff[2] - mp_coeff[0]);
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if (diff[0] > MAX_MEASUREMENT &&
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diff[1] > MAX_MEASUREMENT &&
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diff[2] > MAX_MEASUREMENT)
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return false;
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if (diff[0] <= diff[1] && diff[0] <= diff[2])
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*mp_avg = (mp_coeff[0] + mp_coeff[1]) / 2;
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else if (diff[1] <= diff[2])
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*mp_avg = (mp_coeff[1] + mp_coeff[2]) / 2;
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else
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*mp_avg = (mp_coeff[2] + mp_coeff[0]) / 2;
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return true;
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}
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static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
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u8 num_chains,
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struct coeff *coeff)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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int i, im, nmeasurement;
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int magnitude, phase;
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u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
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memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
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for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
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tx_corr_coeff[i * 2][0] = tx_corr_coeff[(i * 2) + 1][0] =
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AR_PHY_TX_IQCAL_CORR_COEFF_B0(i);
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if (!AR_SREV_9485(ah)) {
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tx_corr_coeff[i * 2][1] =
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tx_corr_coeff[(i * 2) + 1][1] =
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AR_PHY_TX_IQCAL_CORR_COEFF_B1(i);
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tx_corr_coeff[i * 2][2] =
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tx_corr_coeff[(i * 2) + 1][2] =
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AR_PHY_TX_IQCAL_CORR_COEFF_B2(i);
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}
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}
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/* Load the average of 2 passes */
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for (i = 0; i < num_chains; i++) {
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if (AR_SREV_9485(ah))
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nmeasurement = REG_READ_FIELD(ah,
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AR_PHY_TX_IQCAL_STATUS_B0_9485,
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AR_PHY_CALIBRATED_GAINS_0);
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else
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nmeasurement = REG_READ_FIELD(ah,
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AR_PHY_TX_IQCAL_STATUS_B0,
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AR_PHY_CALIBRATED_GAINS_0);
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if (nmeasurement > MAX_MEASUREMENT)
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nmeasurement = MAX_MEASUREMENT;
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for (im = 0; im < nmeasurement; im++) {
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/*
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* Determine which 2 passes are closest and compute avg
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* magnitude
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*/
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if (!ar9003_hw_compute_closest_pass_and_avg(coeff->mag_coeff[i][im],
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&magnitude))
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goto disable_txiqcal;
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/*
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* Determine which 2 passes are closest and compute avg
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* phase
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*/
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if (!ar9003_hw_compute_closest_pass_and_avg(coeff->phs_coeff[i][im],
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&phase))
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goto disable_txiqcal;
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coeff->iqc_coeff[0] = (magnitude & 0x7f) |
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((phase & 0x7f) << 7);
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if ((im % 2) == 0)
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REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
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AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE,
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coeff->iqc_coeff[0]);
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else
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REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
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AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
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coeff->iqc_coeff[0]);
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}
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}
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REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
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AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
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REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
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AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
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return;
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disable_txiqcal:
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REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
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AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x0);
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REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
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AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x0);
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ath_dbg(common, ATH_DBG_CALIBRATE, "TX IQ Cal disabled\n");
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}
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static void ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
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{
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u8 tx_gain_forced;
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REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1_9485,
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AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT);
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tx_gain_forced = REG_READ_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
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AR_PHY_TXGAIN_FORCE);
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if (tx_gain_forced)
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REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
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AR_PHY_TXGAIN_FORCE, 0);
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REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START_9485,
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AR_PHY_TX_IQCAL_START_DO_CAL_9485, 1);
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}
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static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
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AR_PHY_TX_IQCAL_STATUS_B0_9485,
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AR_PHY_TX_IQCAL_STATUS_B1,
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AR_PHY_TX_IQCAL_STATUS_B2,
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};
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const u_int32_t chan_info_tab[] = {
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AR_PHY_CHAN_INFO_TAB_0,
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AR_PHY_CHAN_INFO_TAB_1,
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AR_PHY_CHAN_INFO_TAB_2,
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};
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struct coeff coeff;
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s32 iq_res[6];
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u8 num_chains = 0;
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int i, ip, im, j;
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int nmeasurement;
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for (i = 0; i < AR9300_MAX_CHAINS; i++) {
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if (ah->txchainmask & (1 << i))
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num_chains++;
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}
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for (ip = 0; ip < MPASS; ip++) {
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for (i = 0; i < num_chains; i++) {
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nmeasurement = REG_READ_FIELD(ah,
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AR_PHY_TX_IQCAL_STATUS_B0_9485,
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AR_PHY_CALIBRATED_GAINS_0);
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if (nmeasurement > MAX_MEASUREMENT)
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nmeasurement = MAX_MEASUREMENT;
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for (im = 0; im < nmeasurement; im++) {
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ath_dbg(common, ATH_DBG_CALIBRATE,
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"Doing Tx IQ Cal for chain %d.\n", i);
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if (REG_READ(ah, txiqcal_status[i]) &
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AR_PHY_TX_IQCAL_STATUS_FAILED) {
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ath_dbg(common, ATH_DBG_CALIBRATE,
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"Tx IQ Cal failed for chain %d.\n", i);
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goto tx_iqcal_fail;
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}
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for (j = 0; j < 3; j++) {
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u32 idx = 2 * j, offset = 4 * (3 * im + j);
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REG_RMW_FIELD(ah,
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AR_PHY_CHAN_INFO_MEMORY,
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AR_PHY_CHAN_INFO_TAB_S2_READ,
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0);
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/* 32 bits */
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iq_res[idx] = REG_READ(ah,
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chan_info_tab[i] +
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offset);
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REG_RMW_FIELD(ah,
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AR_PHY_CHAN_INFO_MEMORY,
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AR_PHY_CHAN_INFO_TAB_S2_READ,
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1);
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/* 16 bits */
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iq_res[idx + 1] = 0xffff & REG_READ(ah,
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chan_info_tab[i] + offset);
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ath_dbg(common, ATH_DBG_CALIBRATE,
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"IQ RES[%d]=0x%x"
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"IQ_RES[%d]=0x%x\n",
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idx, iq_res[idx], idx + 1,
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iq_res[idx + 1]);
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}
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if (!ar9003_hw_calc_iq_corr(ah, i, iq_res,
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coeff.iqc_coeff)) {
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ath_dbg(common, ATH_DBG_CALIBRATE,
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"Failed in calculation of IQ correction.\n");
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goto tx_iqcal_fail;
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}
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coeff.mag_coeff[i][im][ip] =
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coeff.iqc_coeff[0] & 0x7f;
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coeff.phs_coeff[i][im][ip] =
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(coeff.iqc_coeff[0] >> 7) & 0x7f;
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if (coeff.mag_coeff[i][im][ip] > 63)
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coeff.mag_coeff[i][im][ip] -= 128;
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if (coeff.phs_coeff[i][im][ip] > 63)
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coeff.phs_coeff[i][im][ip] -= 128;
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}
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}
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}
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ar9003_hw_tx_iqcal_load_avg_2_passes(ah, num_chains, &coeff);
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return;
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tx_iqcal_fail:
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ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
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return;
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}
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static bool ar9003_hw_init_cal(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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@ -733,7 +966,11 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
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ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
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/* Do Tx IQ Calibration */
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ar9003_hw_tx_iq_cal(ah);
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if (AR_SREV_9485(ah))
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ar9003_hw_tx_iq_cal_run(ah);
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else
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ar9003_hw_tx_iq_cal(ah);
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REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
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udelay(5);
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REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
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@ -751,6 +988,9 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
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return false;
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}
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if (AR_SREV_9485(ah))
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ar9003_hw_tx_iq_cal_post_proc(ah);
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/* Revert chainmasks to their original values before NF cal */
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ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
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@ -546,6 +546,12 @@
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#define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300)
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#define AR_PHY_TX_IQCAL_START_9485 (AR_SM_BASE + 0x3c4)
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#define AR_PHY_TX_IQCAL_START_DO_CAL_9485 0x80000000
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#define AR_PHY_TX_IQCAL_START_DO_CAL_9485_S 31
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#define AR_PHY_TX_IQCAL_CONTROL_1_9485 (AR_SM_BASE + 0x3c8)
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#define AR_PHY_TX_IQCAL_STATUS_B0_9485 (AR_SM_BASE + 0x3f0)
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#define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + 0x448)
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#define AR_PHY_TX_IQCAL_START (AR_SM_BASE + 0x440)
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#define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + 0x48c)
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@ -713,6 +719,7 @@
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#define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1
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#define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001
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#define AR_PHY_TXGAIN_FORCE 0x00000001
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#define AR_PHY_TXGAIN_FORCE_S 0
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#define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00
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#define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10
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#define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000
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@ -755,8 +762,13 @@
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#define AR_PHY_TX_IQCAL_START_DO_CAL_S 0
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#define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001
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#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x00003fff
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#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 0
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#define AR_PHY_CALIBRATED_GAINS_0 0x3e
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#define AR_PHY_CALIBRATED_GAINS_0_S 1
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#define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE 0x00003fff
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#define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S 0
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#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x0fffc000
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#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 14
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#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
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#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
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