ath9k_hw: prevent reset control register zeroing on AR9003 reset
Also, no need for the udelay(2) on AR9003 hardware. Signed-off-by: Senthil Balasubramanian <senthilkumar@atheros.com> Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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1 changed files with 4 additions and 2 deletions
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@ -1385,9 +1385,11 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
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REG_WRITE(ah, AR_RC, AR_RC_AHB);
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REG_WRITE(ah, AR_RTC_RESET, 0);
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if (!AR_SREV_9300_20_OR_LATER(ah))
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udelay(2);
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if (!AR_SREV_9100(ah))
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if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
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REG_WRITE(ah, AR_RC, 0);
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REG_WRITE(ah, AR_RTC_RESET, 1);
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