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ARM: LPC32xx: Add the motor PWM clock

This commit is contained in:
Alban Bedel 2012-11-12 11:27:40 +01:00 committed by Roland Stigge
parent 91deef8069
commit 84cee34db4
2 changed files with 9 additions and 0 deletions

View File

@ -585,6 +585,13 @@ static struct clk clk_timer3 = {
.enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
.get_rate = local_return_parent_rate,
};
static struct clk clk_mpwm = {
.parent = &clk_pclk,
.enable = local_onoff_enable,
.enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
.enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN,
.get_rate = local_return_parent_rate,
};
static struct clk clk_wdt = {
.parent = &clk_pclk,
.enable = local_onoff_enable,
@ -1202,6 +1209,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm),
CLKDEV_INIT("400e8000.mpwm", NULL, &clk_mpwm),
CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),

View File

@ -515,6 +515,7 @@
/*
* clkpwr_timers_pwms_clk_ctrl_1 register definitions
*/
#define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN 0x40
#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 0x20
#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 0x10
#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 0x08