ARM: S5PV310: Add IRQ support
This patch adds IRQ support for S5PV310. ARM GIC is installed in S5PV310 instead of VIC which is in every other CPUs in S5P series. Several irq combiners are used to resolve the lack of irq lines in current implementation. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Changhwan Youn
Kukjin Kim
parent
c8bef14051
commit
84bbc16c1f
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@ -0,0 +1,74 @@
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/* linux/arch/arm/mach-s5pv310/include/mach/irqs.h
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5PV210 - IRQ definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_IRQS_H
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#define __ASM_ARCH_IRQS_H __FILE__
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#include <plat/irqs.h>
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/* Private Peripheral Interrupt */
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#define IRQ_PPI(x) S5P_IRQ(x+16)
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#define IRQ_LOCALTIMER IRQ_PPI(13)
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/* Shared Peripheral Interrupt */
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#define IRQ_SPI(x) S5P_IRQ(x+32)
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#define IRQ_EINT0 IRQ_SPI(40)
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#define IRQ_EINT1 IRQ_SPI(41)
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#define IRQ_EINT2 IRQ_SPI(42)
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#define IRQ_EINT3 IRQ_SPI(43)
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#define IRQ_USB_HSOTG IRQ_SPI(44)
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#define IRQ_USB_HOST IRQ_SPI(45)
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#define IRQ_MODEM_IF IRQ_SPI(46)
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#define IRQ_ROTATOR IRQ_SPI(47)
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#define IRQ_JPEG IRQ_SPI(48)
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#define IRQ_2D IRQ_SPI(49)
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#define IRQ_PCIE IRQ_SPI(50)
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#define IRQ_SYSTEM_TIMER IRQ_SPI(51)
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#define IRQ_MFC IRQ_SPI(52)
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#define IRQ_WTD IRQ_SPI(53)
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#define IRQ_AUDIO_SS IRQ_SPI(54)
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#define IRQ_AC97 IRQ_SPI(55)
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#define IRQ_SPDIF IRQ_SPI(56)
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#define IRQ_KEYPAD IRQ_SPI(57)
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#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(58)
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#define IRQ_SLIMBUS IRQ_SPI(59)
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#define IRQ_PMU IRQ_SPI(60)
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#define IRQ_TSI IRQ_SPI(61)
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#define IRQ_SATA IRQ_SPI(62)
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#define IRQ_GPS IRQ_SPI(63)
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#define MAX_IRQ_IN_COMBINER 8
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#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64))
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#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
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#define IRQ_TIMER0_VIC COMBINER_IRQ(22, 0)
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#define IRQ_TIMER1_VIC COMBINER_IRQ(22, 1)
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#define IRQ_TIMER2_VIC COMBINER_IRQ(22, 2)
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#define IRQ_TIMER3_VIC COMBINER_IRQ(22, 3)
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#define IRQ_TIMER4_VIC COMBINER_IRQ(22, 4)
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#define IRQ_UART0 COMBINER_IRQ(26, 0)
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#define IRQ_UART1 COMBINER_IRQ(26, 1)
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#define IRQ_UART2 COMBINER_IRQ(26, 2)
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#define IRQ_UART3 COMBINER_IRQ(26, 3)
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#define IRQ_UART4 COMBINER_IRQ(26, 4)
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#define IRQ_IIC COMBINER_IRQ(27, 0)
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/* Set the default NR_IRQS */
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#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0)
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#define MAX_COMBINER_NR 39
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#endif /* ASM_ARCH_IRQS_H */
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@ -0,0 +1,19 @@
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/* linux/arch/arm/mach-s5pv310/include/mach/regs-irq.h
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5PV310 - IRQ register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGS_IRQ_H
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#define __ASM_ARCH_REGS_IRQ_H __FILE__
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#include <asm/hardware/gic.h>
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#include <mach/map.h>
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#endif /* __ASM_ARCH_REGS_IRQ_H */
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@ -0,0 +1,125 @@
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/* linux/arch/arm/mach-s5pv310/irq-combiner.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Based on arch/arm/common/gic.c
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*
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* IRQ COMBINER support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <asm/mach/irq.h>
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#define COMBINER_ENABLE_SET 0x0
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#define COMBINER_ENABLE_CLEAR 0x4
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#define COMBINER_INT_STATUS 0xC
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static DEFINE_SPINLOCK(irq_controller_lock);
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struct combiner_chip_data {
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unsigned int irq_offset;
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void __iomem *base;
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};
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static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
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static inline void __iomem *combiner_base(unsigned int irq)
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{
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struct combiner_chip_data *combiner_data = get_irq_chip_data(irq);
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return combiner_data->base;
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}
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static void combiner_mask_irq(unsigned int irq)
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{
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u32 mask = 1 << (irq % 32);
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__raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_CLEAR);
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}
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static void combiner_unmask_irq(unsigned int irq)
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{
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u32 mask = 1 << (irq % 32);
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__raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_SET);
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}
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static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct combiner_chip_data *chip_data = get_irq_data(irq);
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struct irq_chip *chip = get_irq_chip(irq);
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unsigned int cascade_irq, combiner_irq;
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unsigned long status;
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/* primary controller ack'ing */
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chip->ack(irq);
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spin_lock(&irq_controller_lock);
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status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
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spin_unlock(&irq_controller_lock);
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if (status == 0)
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goto out;
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for (combiner_irq = 0; combiner_irq < 32; combiner_irq++) {
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if (status & 0x1)
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break;
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status >>= 1;
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}
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cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
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if (unlikely(cascade_irq >= NR_IRQS))
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do_bad_IRQ(cascade_irq, desc);
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else
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generic_handle_irq(cascade_irq);
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out:
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/* primary controller unmasking */
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chip->unmask(irq);
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}
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static struct irq_chip combiner_chip = {
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.name = "COMBINER",
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.mask = combiner_mask_irq,
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.unmask = combiner_unmask_irq,
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};
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void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
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{
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if (combiner_nr >= MAX_COMBINER_NR)
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BUG();
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if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0)
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BUG();
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set_irq_chained_handler(irq, combiner_handle_cascade_irq);
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}
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void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
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unsigned int irq_start)
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{
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unsigned int i;
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if (combiner_nr >= MAX_COMBINER_NR)
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BUG();
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combiner_data[combiner_nr].base = base;
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combiner_data[combiner_nr].irq_offset = irq_start;
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/* Disable all interrupts */
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__raw_writel(0xffffffff, base + COMBINER_ENABLE_CLEAR);
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/* Setup the Linux IRQ subsystem */
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for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
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+ MAX_IRQ_IN_COMBINER; i++) {
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set_irq_chip(i, &combiner_chip);
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set_irq_chip_data(i, &combiner_data[combiner_nr]);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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}
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@ -56,11 +56,13 @@ static struct s3c_uart_irq uart_irqs[] = {
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void __init s5p_init_irq(u32 *vic, u32 num_vic)
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{
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#ifdef CONFIG_ARM_VIC
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int irq;
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/* initialize the VICs */
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for (irq = 0; irq < num_vic; irq++)
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vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
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#endif
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s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
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s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
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