ARM: 6310/1: mmci: support different FIFO sizes
The Ux500 variant has a 32-word FIFO (TXFIFOEMPTY is asserted when it has 2 left) and TXFIFOHALFEMPTY is repurposed as TXFIFOBURSTWRITEABLE, with a burst being defined as 8-words. Likewise for RX. Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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2971944582
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2 changed files with 19 additions and 10 deletions
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@ -41,23 +41,35 @@ static unsigned int fmax = 515633;
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* @clkreg: default value for MCICLOCK register
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* @clkreg_enable: enable value for MMCICLOCK register
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* @datalength_bits: number of bits in the MMCIDATALENGTH register
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* @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
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* is asserted (likewise for RX)
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* @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
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* is asserted (likewise for RX)
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*/
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struct variant_data {
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unsigned int clkreg;
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unsigned int clkreg_enable;
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unsigned int datalength_bits;
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unsigned int fifosize;
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unsigned int fifohalfsize;
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};
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static struct variant_data variant_arm = {
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.fifosize = 16 * 4,
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.fifohalfsize = 8 * 4,
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.datalength_bits = 16,
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};
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static struct variant_data variant_u300 = {
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.fifosize = 16 * 4,
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.fifohalfsize = 8 * 4,
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.clkreg_enable = 1 << 13, /* HWFCEN */
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.datalength_bits = 16,
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};
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static struct variant_data variant_ux500 = {
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.fifosize = 30 * 4,
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.fifohalfsize = 8 * 4,
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.clkreg = MCI_CLK_ENABLE,
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.clkreg_enable = 1 << 14, /* HWFCEN */
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.datalength_bits = 24,
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@ -138,6 +150,7 @@ static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
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static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
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{
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struct variant_data *variant = host->variant;
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unsigned int datactrl, timeout, irqmask;
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unsigned long long clks;
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void __iomem *base;
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@ -173,7 +186,7 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
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* If we have less than a FIFOSIZE of bytes to transfer,
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* trigger a PIO interrupt as soon as any data is available.
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*/
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if (host->size < MCI_FIFOSIZE)
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if (host->size < variant->fifosize)
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irqmask |= MCI_RXDATAAVLBLMASK;
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} else {
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/*
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@ -332,13 +345,15 @@ static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int rema
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static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
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{
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struct variant_data *variant = host->variant;
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void __iomem *base = host->base;
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char *ptr = buffer;
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do {
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unsigned int count, maxcnt;
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maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE;
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maxcnt = status & MCI_TXFIFOEMPTY ?
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variant->fifosize : variant->fifohalfsize;
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count = min(remain, maxcnt);
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writesl(base + MMCIFIFO, ptr, count >> 2);
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@ -362,6 +377,7 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
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{
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struct mmci_host *host = dev_id;
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struct sg_mapping_iter *sg_miter = &host->sg_miter;
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struct variant_data *variant = host->variant;
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void __iomem *base = host->base;
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unsigned long flags;
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u32 status;
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@ -420,7 +436,7 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
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* If we're nearing the end of the read, switch to
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* "any data available" mode.
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*/
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if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE)
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if (status & MCI_RXACTIVE && host->size < variant->fifosize)
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writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
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/*
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@ -133,13 +133,6 @@
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MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
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MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATABLOCKENDMASK)
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/*
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* The size of the FIFO in bytes.
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*/
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#define MCI_FIFOSIZE (16*4)
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#define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2)
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#define NR_SG 16
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struct clk;
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