Merge branches 'regmap/irq' and 'regmap/cache' into regmap-next
This commit is contained in:
commit
81bf58eb3c
8 changed files with 361 additions and 3 deletions
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@ -13,3 +13,6 @@ config REGMAP_I2C
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config REGMAP_SPI
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config REGMAP_SPI
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tristate
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tristate
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config REGMAP_IRQ
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bool
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@ -3,3 +3,4 @@ obj-$(CONFIG_REGMAP) += regcache-rbtree.o regcache-lzo.o
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obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o
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obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o
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obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o
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obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o
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obj-$(CONFIG_REGMAP_SPI) += regmap-spi.o
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obj-$(CONFIG_REGMAP_SPI) += regmap-spi.o
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obj-$(CONFIG_REGMAP_IRQ) += regmap-irq.o
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@ -74,6 +74,7 @@ struct regmap {
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struct reg_default *reg_defaults;
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struct reg_default *reg_defaults;
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const void *reg_defaults_raw;
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const void *reg_defaults_raw;
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void *cache;
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void *cache;
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bool cache_dirty;
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};
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};
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struct regcache_ops {
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struct regcache_ops {
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@ -354,7 +354,7 @@ static int regcache_lzo_sync(struct regmap *map)
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}
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}
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struct regcache_ops regcache_lzo_ops = {
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struct regcache_ops regcache_lzo_ops = {
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.type = REGCACHE_LZO,
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.type = REGCACHE_COMPRESSED,
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.name = "lzo",
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.name = "lzo",
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.init = regcache_lzo_init,
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.init = regcache_lzo_init,
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.exit = regcache_lzo_exit,
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.exit = regcache_lzo_exit,
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@ -241,6 +241,8 @@ int regcache_sync(struct regmap *map)
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map->cache_ops->name);
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map->cache_ops->name);
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name = map->cache_ops->name;
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name = map->cache_ops->name;
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trace_regcache_sync(map->dev, name, "start");
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trace_regcache_sync(map->dev, name, "start");
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if (!map->cache_dirty)
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goto out;
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if (map->cache_ops->sync) {
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if (map->cache_ops->sync) {
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ret = map->cache_ops->sync(map);
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ret = map->cache_ops->sync(map);
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} else {
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} else {
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@ -290,6 +292,23 @@ void regcache_cache_only(struct regmap *map, bool enable)
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}
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}
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EXPORT_SYMBOL_GPL(regcache_cache_only);
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EXPORT_SYMBOL_GPL(regcache_cache_only);
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/**
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* regcache_mark_dirty: Mark the register cache as dirty
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*
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* @map: map to mark
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*
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* Mark the register cache as dirty, for example due to the device
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* having been powered down for suspend. If the cache is not marked
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* as dirty then the cache sync will be suppressed.
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*/
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void regcache_mark_dirty(struct regmap *map)
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{
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mutex_lock(&map->lock);
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map->cache_dirty = true;
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mutex_unlock(&map->lock);
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}
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EXPORT_SYMBOL_GPL(regcache_mark_dirty);
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/**
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/**
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* regcache_cache_bypass: Put a register map into cache bypass mode
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* regcache_cache_bypass: Put a register map into cache bypass mode
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*
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*
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284
drivers/base/regmap/regmap-irq.c
Normal file
284
drivers/base/regmap/regmap-irq.c
Normal file
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@ -0,0 +1,284 @@
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/*
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* regmap based irq_chip
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*
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* Copyright 2011 Wolfson Microelectronics plc
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*
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* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/export.h>
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#include <linux/regmap.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include "internal.h"
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struct regmap_irq_chip_data {
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struct mutex lock;
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struct regmap *map;
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struct regmap_irq_chip *chip;
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int irq_base;
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void *status_reg_buf;
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unsigned int *status_buf;
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unsigned int *mask_buf;
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unsigned int *mask_buf_def;
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};
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static inline const
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struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
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int irq)
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{
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return &data->chip->irqs[irq - data->irq_base];
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}
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static void regmap_irq_lock(struct irq_data *data)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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mutex_lock(&d->lock);
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}
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static void regmap_irq_sync_unlock(struct irq_data *data)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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int i, ret;
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/*
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* If there's been a change in the mask write it back to the
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* hardware. We rely on the use of the regmap core cache to
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* suppress pointless writes.
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*/
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for (i = 0; i < d->chip->num_regs; i++) {
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ret = regmap_update_bits(d->map, d->chip->mask_base + i,
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d->mask_buf_def[i], d->mask_buf[i]);
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if (ret != 0)
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dev_err(d->map->dev, "Failed to sync masks in %x\n",
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d->chip->mask_base + i);
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}
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mutex_unlock(&d->lock);
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}
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static void regmap_irq_enable(struct irq_data *data)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->irq);
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d->mask_buf[irq_data->reg_offset] &= ~irq_data->mask;
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}
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static void regmap_irq_disable(struct irq_data *data)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->irq);
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d->mask_buf[irq_data->reg_offset] |= irq_data->mask;
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}
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static struct irq_chip regmap_irq_chip = {
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.name = "regmap",
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.irq_bus_lock = regmap_irq_lock,
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.irq_bus_sync_unlock = regmap_irq_sync_unlock,
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.irq_disable = regmap_irq_disable,
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.irq_enable = regmap_irq_enable,
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};
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static irqreturn_t regmap_irq_thread(int irq, void *d)
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{
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struct regmap_irq_chip_data *data = d;
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struct regmap_irq_chip *chip = data->chip;
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struct regmap *map = data->map;
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int ret, i;
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u8 *buf8 = data->status_reg_buf;
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u16 *buf16 = data->status_reg_buf;
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u32 *buf32 = data->status_reg_buf;
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ret = regmap_bulk_read(map, chip->status_base, data->status_reg_buf,
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chip->num_regs);
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if (ret != 0) {
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dev_err(map->dev, "Failed to read IRQ status: %d\n", ret);
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return IRQ_NONE;
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}
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/*
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* Ignore masked IRQs and ack if we need to; we ack early so
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* there is no race between handling and acknowleding the
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* interrupt. We assume that typically few of the interrupts
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* will fire simultaneously so don't worry about overhead from
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* doing a write per register.
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*/
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for (i = 0; i < data->chip->num_regs; i++) {
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switch (map->format.val_bytes) {
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case 1:
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data->status_buf[i] = buf8[i];
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break;
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case 2:
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data->status_buf[i] = buf16[i];
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break;
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case 4:
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data->status_buf[i] = buf32[i];
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break;
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default:
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BUG();
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return IRQ_NONE;
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}
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data->status_buf[i] &= ~data->mask_buf[i];
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if (data->status_buf[i] && chip->ack_base) {
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ret = regmap_write(map, chip->ack_base + i,
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data->status_buf[i]);
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if (ret != 0)
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dev_err(map->dev, "Failed to ack 0x%x: %d\n",
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chip->ack_base + i, ret);
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}
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}
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for (i = 0; i < chip->num_irqs; i++) {
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if (data->status_buf[chip->irqs[i].reg_offset] &
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chip->irqs[i].mask) {
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handle_nested_irq(data->irq_base + i);
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}
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}
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return IRQ_HANDLED;
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}
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/**
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* regmap_add_irq_chip(): Use standard regmap IRQ controller handling
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*
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* map: The regmap for the device.
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* irq: The IRQ the device uses to signal interrupts
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* irq_flags: The IRQF_ flags to use for the primary interrupt.
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* chip: Configuration for the interrupt controller.
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* data: Runtime data structure for the controller, allocated on success
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*
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* Returns 0 on success or an errno on failure.
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*
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* In order for this to be efficient the chip really should use a
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* register cache. The chip driver is responsible for restoring the
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* register values used by the IRQ controller over suspend and resume.
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*/
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int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
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int irq_base, struct regmap_irq_chip *chip,
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struct regmap_irq_chip_data **data)
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{
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struct regmap_irq_chip_data *d;
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int cur_irq, i;
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int ret = -ENOMEM;
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irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
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if (irq_base < 0) {
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dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
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irq_base);
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return irq_base;
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}
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|
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d = kzalloc(sizeof(*d), GFP_KERNEL);
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|
if (!d)
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return -ENOMEM;
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|
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d->status_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
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|
GFP_KERNEL);
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|
if (!d->status_buf)
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goto err_alloc;
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|
|
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d->status_reg_buf = kzalloc(map->format.val_bytes * chip->num_regs,
|
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|
GFP_KERNEL);
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if (!d->status_reg_buf)
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goto err_alloc;
|
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|
|
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d->mask_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
|
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GFP_KERNEL);
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if (!d->mask_buf)
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goto err_alloc;
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|
|
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d->mask_buf_def = kzalloc(sizeof(unsigned int) * chip->num_regs,
|
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GFP_KERNEL);
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|
if (!d->mask_buf_def)
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goto err_alloc;
|
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|
|
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d->map = map;
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d->chip = chip;
|
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d->irq_base = irq_base;
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|
mutex_init(&d->lock);
|
||||||
|
|
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|
for (i = 0; i < chip->num_irqs; i++)
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d->mask_buf_def[chip->irqs[i].reg_offset]
|
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|
|= chip->irqs[i].mask;
|
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|
|
||||||
|
/* Mask all the interrupts by default */
|
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|
for (i = 0; i < chip->num_regs; i++) {
|
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d->mask_buf[i] = d->mask_buf_def[i];
|
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ret = regmap_write(map, chip->mask_base + i, d->mask_buf[i]);
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|
if (ret != 0) {
|
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|
dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
|
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|
chip->mask_base + i, ret);
|
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|
goto err_alloc;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Register them with genirq */
|
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|
for (cur_irq = irq_base;
|
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|
cur_irq < chip->num_irqs + irq_base;
|
||||||
|
cur_irq++) {
|
||||||
|
irq_set_chip_data(cur_irq, d);
|
||||||
|
irq_set_chip_and_handler(cur_irq, ®map_irq_chip,
|
||||||
|
handle_edge_irq);
|
||||||
|
irq_set_nested_thread(cur_irq, 1);
|
||||||
|
|
||||||
|
/* ARM needs us to explicitly flag the IRQ as valid
|
||||||
|
* and will set them noprobe when we do so. */
|
||||||
|
#ifdef CONFIG_ARM
|
||||||
|
set_irq_flags(cur_irq, IRQF_VALID);
|
||||||
|
#else
|
||||||
|
irq_set_noprobe(cur_irq);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = request_threaded_irq(irq, NULL, regmap_irq_thread, irq_flags,
|
||||||
|
chip->name, d);
|
||||||
|
if (ret != 0) {
|
||||||
|
dev_err(map->dev, "Failed to request IRQ %d: %d\n", irq, ret);
|
||||||
|
goto err_alloc;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
err_alloc:
|
||||||
|
kfree(d->mask_buf_def);
|
||||||
|
kfree(d->mask_buf);
|
||||||
|
kfree(d->status_reg_buf);
|
||||||
|
kfree(d->status_buf);
|
||||||
|
kfree(d);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* regmap_del_irq_chip(): Stop interrupt handling for a regmap IRQ chip
|
||||||
|
*
|
||||||
|
* @irq: Primary IRQ for the device
|
||||||
|
* @d: regmap_irq_chip_data allocated by regmap_add_irq_chip()
|
||||||
|
*/
|
||||||
|
void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
|
||||||
|
{
|
||||||
|
if (!d)
|
||||||
|
return;
|
||||||
|
|
||||||
|
free_irq(irq, d);
|
||||||
|
kfree(d->mask_buf_def);
|
||||||
|
kfree(d->mask_buf);
|
||||||
|
kfree(d->status_reg_buf);
|
||||||
|
kfree(d->status_buf);
|
||||||
|
kfree(d);
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
|
|
@ -306,8 +306,10 @@ int _regmap_write(struct regmap *map, unsigned int reg,
|
||||||
ret = regcache_write(map, reg, val);
|
ret = regcache_write(map, reg, val);
|
||||||
if (ret != 0)
|
if (ret != 0)
|
||||||
return ret;
|
return ret;
|
||||||
if (map->cache_only)
|
if (map->cache_only) {
|
||||||
|
map->cache_dirty = true;
|
||||||
return 0;
|
return 0;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
trace_regmap_reg_write(map->dev, reg, val);
|
trace_regmap_reg_write(map->dev, reg, val);
|
||||||
|
|
|
@ -25,7 +25,7 @@ enum regcache_type {
|
||||||
REGCACHE_NONE,
|
REGCACHE_NONE,
|
||||||
REGCACHE_INDEXED,
|
REGCACHE_INDEXED,
|
||||||
REGCACHE_RBTREE,
|
REGCACHE_RBTREE,
|
||||||
REGCACHE_LZO
|
REGCACHE_COMPRESSED
|
||||||
};
|
};
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -143,5 +143,53 @@ int regmap_update_bits(struct regmap *map, unsigned int reg,
|
||||||
int regcache_sync(struct regmap *map);
|
int regcache_sync(struct regmap *map);
|
||||||
void regcache_cache_only(struct regmap *map, bool enable);
|
void regcache_cache_only(struct regmap *map, bool enable);
|
||||||
void regcache_cache_bypass(struct regmap *map, bool enable);
|
void regcache_cache_bypass(struct regmap *map, bool enable);
|
||||||
|
void regcache_mark_dirty(struct regmap *map);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Description of an IRQ for the generic regmap irq_chip.
|
||||||
|
*
|
||||||
|
* @reg_offset: Offset of the status/mask register within the bank
|
||||||
|
* @mask: Mask used to flag/control the register.
|
||||||
|
*/
|
||||||
|
struct regmap_irq {
|
||||||
|
unsigned int reg_offset;
|
||||||
|
unsigned int mask;
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Description of a generic regmap irq_chip. This is not intended to
|
||||||
|
* handle every possible interrupt controller, but it should handle a
|
||||||
|
* substantial proportion of those that are found in the wild.
|
||||||
|
*
|
||||||
|
* @name: Descriptive name for IRQ controller.
|
||||||
|
*
|
||||||
|
* @status_base: Base status register address.
|
||||||
|
* @mask_base: Base mask register address.
|
||||||
|
* @ack_base: Base ack address. If zero then the chip is clear on read.
|
||||||
|
*
|
||||||
|
* @num_regs: Number of registers in each control bank.
|
||||||
|
* @irqs: Descriptors for individual IRQs. Interrupt numbers are
|
||||||
|
* assigned based on the index in the array of the interrupt.
|
||||||
|
* @num_irqs: Number of descriptors.
|
||||||
|
*/
|
||||||
|
struct regmap_irq_chip {
|
||||||
|
const char *name;
|
||||||
|
|
||||||
|
unsigned int status_base;
|
||||||
|
unsigned int mask_base;
|
||||||
|
unsigned int ack_base;
|
||||||
|
|
||||||
|
int num_regs;
|
||||||
|
|
||||||
|
const struct regmap_irq *irqs;
|
||||||
|
int num_irqs;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct regmap_irq_chip_data;
|
||||||
|
|
||||||
|
int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
|
||||||
|
int irq_base, struct regmap_irq_chip *chip,
|
||||||
|
struct regmap_irq_chip_data **data);
|
||||||
|
void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *data);
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
Reference in a new issue