arm-soc: soc-specific pinctrl changes
With this, five platforms are moving to the relatively new pinctrl
subsystem for their pin management, replacing the older soc specific
in-kernel interfaces with common code.
There is quite a bit of net addition of code for each platform being
added to the pinctrl subsystem. but the payback comes later when adding
new boards can be done by only providing new device trees instead.
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Merge tag 'pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm soc-specific pinctrl changes from Olof Johansson:
"With this, five platforms are moving to the relatively new pinctrl
subsystem for their pin management, replacing the older soc specific
in-kernel interfaces with common code.
There is quite a bit of net addition of code for each platform being
added to the pinctrl subsystem. But the payback comes later when
adding new boards can be done by only providing new device trees
instead."
Fix up trivial conflicts in arch/arm/mach-ux500/{Makefile,board-mop500.c}
* tag 'pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (61 commits)
mtd: nand: gpmi: fix compile error caused by pinctrl call
ARM: PRIMA2: select PINCTRL and PINCTRL_SIRF in Kconfig
ARM: nomadik: enable PINCTRL_NOMADIK where needed
ARM: mxs: enable pinctrl support
video: mxsfb: adopt pinctrl support
ASoC: mxs-saif: adopt pinctrl support
i2c: mxs: adopt pinctrl support
mtd: nand: gpmi: adopt pinctrl support
mmc: mxs-mmc: adopt pinctrl support
serial: mxs-auart: adopt pinctrl support
serial: amba-pl011: adopt pinctrl support
spi/imx: adopt pinctrl support
i2c: imx: adopt pinctrl support
can: flexcan: adopt pinctrl support
net: fec: adopt pinctrl support
ARM: ux500: switch MSP to using pinctrl for pins
ARM: ux500: alter MSP registration to return a device pointer
ARM: ux500: switch to using pinctrl for uart0
ARM: ux500: delete custom pin control system
ARM: ux500: switch over to Nomadik pinctrl driver
...
This commit is contained in:
Linus Torvalds
commit
813a95e5b4
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@ -0,0 +1,108 @@
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ST Microelectronics, SPEAr pinmux controller
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Required properties:
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- compatible : "st,spear300-pinmux"
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: "st,spear310-pinmux"
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: "st,spear320-pinmux"
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- reg : Address range of the pinctrl registers
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- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
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- Its values for SPEAr300:
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- NAND_MODE : <0>
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- NOR_MODE : <1>
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- PHOTO_FRAME_MODE : <2>
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- LEND_IP_PHONE_MODE : <3>
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- HEND_IP_PHONE_MODE : <4>
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- LEND_WIFI_PHONE_MODE : <5>
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- HEND_WIFI_PHONE_MODE : <6>
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- ATA_PABX_WI2S_MODE : <7>
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- ATA_PABX_I2S_MODE : <8>
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- CAML_LCDW_MODE : <9>
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- CAMU_LCD_MODE : <10>
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- CAMU_WLCD_MODE : <11>
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- CAML_LCD_MODE : <12>
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- Its values for SPEAr320:
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- AUTO_NET_SMII_MODE : <0>
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- AUTO_NET_MII_MODE : <1>
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- AUTO_EXP_MODE : <2>
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- SMALL_PRINTERS_MODE : <3>
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- EXTENDED_MODE : <4>
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Please refer to pinctrl-bindings.txt in this directory for details of the common
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pinctrl bindings used by client devices.
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SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each
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of these subnodes represents muxing for a pin, a group, or a list of pins or
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groups.
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Required subnode-properties:
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- st,pins : An array of strings. Each string contains the name of a pin or
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group.
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- st,function: A string containing the name of the function to mux to the pin or
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group. See the SPEAr's TRM to determine which are valid for each pin or group.
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Valid values for group and function names can be found from looking at the
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group and function arrays in driver files:
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drivers/pinctrl/spear/pinctrl-spear3*0.c
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Valid values for group names are:
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For All SPEAr3xx machines:
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"firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp",
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"gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp",
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"gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp",
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"timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp"
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For SPEAr300 machines:
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"fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp",
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"clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp",
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"dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp",
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"gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
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For SPEAr310 machines:
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"emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp",
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"uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp"
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For SPEAr320 machines:
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"clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp",
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"sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp",
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"uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp",
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"uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp",
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"uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp",
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"uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp",
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"uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp",
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"uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
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"uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp",
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"uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp",
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"uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp",
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"can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp",
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"pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp",
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"pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp",
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"pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp",
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"pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp",
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"pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp",
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"pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp",
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"ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp",
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"ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp",
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"ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp",
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"rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
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"i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
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Valid values for function names are:
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For All SPEAr3xx machines:
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"firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
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"uart0", "timer_0_1", "timer_2_3"
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For SPEAr300 machines:
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"fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1"
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For SPEAr310 machines:
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"emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0",
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"rs485_1", "tdm"
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For SPEAr320 machines:
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"clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem",
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"uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
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"can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
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"mii0_1", "i2c1", "i2c2"
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23
MAINTAINERS
23
MAINTAINERS
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@ -5240,6 +5240,14 @@ M: Linus Walleij <linus.walleij@linaro.org>
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S: Maintained
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F: drivers/pinctrl/
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PIN CONTROLLER - ST SPEAR
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M: Viresh Kumar <viresh.kumar@st.com>
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L: spear-devel@list.st.com
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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W: http://www.st.com/spear
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S: Maintained
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F: driver/pinctrl/spear/
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PKTCDVD DRIVER
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M: Peter Osterlund <petero2@telia.com>
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S: Maintained
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@ -6344,21 +6352,6 @@ F: arch/arm/mach-spear*/clock.c
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F: arch/arm/plat-spear/clock.c
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F: arch/arm/plat-spear/include/plat/clock.h
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SPEAR PAD MULTIPLEXING SUPPORT
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M: Viresh Kumar <viresh.kumar@st.com>
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L: spear-devel@list.st.com
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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W: http://www.st.com/spear
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S: Maintained
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F: arch/arm/plat-spear/include/plat/padmux.h
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F: arch/arm/plat-spear/padmux.c
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F: arch/arm/mach-spear*/spear*xx.c
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F: arch/arm/mach-spear*/include/mach/generic.h
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F: arch/arm/mach-spear3xx/spear3*0.c
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F: arch/arm/mach-spear3xx/spear3*0_evb.c
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F: arch/arm/mach-spear6xx/spear600.c
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F: arch/arm/mach-spear6xx/spear600_evb.c
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SPI SUBSYSTEM
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M: Grant Likely <grant.likely@secretlab.ca>
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L: spi-devel-general@lists.sourceforge.net
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@ -403,6 +403,8 @@ config ARCH_PRIMA2
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select CLKDEV_LOOKUP
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select GENERIC_IRQ_CHIP
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select MIGHT_HAVE_CACHE_L2X0
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select PINCTRL
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select PINCTRL_SIRF
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select USE_OF
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select ZONE_DMA
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help
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@ -465,6 +467,7 @@ config ARCH_MXS
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select CLKDEV_LOOKUP
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select CLKSRC_MMIO
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select HAVE_CLK_PREPARE
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select PINCTRL
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help
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Support for Freescale MXS-based family of processors
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@ -919,6 +922,7 @@ config ARCH_NOMADIK
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select CPU_ARM926T
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select CLKDEV_LOOKUP
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select GENERIC_CLOCKEVENTS
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select PINCTRL
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select MIGHT_HAVE_CACHE_L2X0
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select ARCH_REQUIRE_GPIOLIB
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help
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|
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@ -25,6 +25,44 @@
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};
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ahb {
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pinmux@99000000 {
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st,pinmux-mode = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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i2c0 {
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st,pins = "i2c0_grp";
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st,function = "i2c0";
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};
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ssp0 {
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st,pins = "ssp0_grp";
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st,function = "ssp0";
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};
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mii0 {
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st,pins = "mii0_grp";
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st,function = "mii0";
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};
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uart0 {
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st,pins = "uart0_grp";
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st,function = "uart0";
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};
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clcd {
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st,pins = "clcd_pfmode_grp";
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st,function = "clcd";
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};
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sdhci {
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st,pins = "sdhci_4bit_grp";
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st,function = "sdhci";
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};
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gpio1 {
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st,pins = "gpio1_4_to_7_grp",
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"gpio1_0_to_3_grp";
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st,function = "gpio1";
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};
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};
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};
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clcd@60000000 {
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status = "okay";
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};
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|
|
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|
@ -21,6 +21,11 @@
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ranges = <0x60000000 0x60000000 0x50000000
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0xd0000000 0xd0000000 0x30000000>;
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pinmux@99000000 {
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compatible = "st,spear300-pinmux";
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reg = <0x99000000 0x1000>;
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};
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clcd@60000000 {
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compatible = "arm,clcd-pl110", "arm,primecell";
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reg = <0x60000000 0x1000>;
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|
|
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|
@ -25,6 +25,67 @@
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};
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ahb {
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pinmux@b4000000 {
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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|
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state_default: pinmux {
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gpio0 {
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st,pins = "gpio0_pin0_grp",
|
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"gpio0_pin1_grp",
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"gpio0_pin2_grp",
|
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"gpio0_pin3_grp",
|
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"gpio0_pin4_grp",
|
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"gpio0_pin5_grp";
|
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st,function = "gpio0";
|
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};
|
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i2c0 {
|
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st,pins = "i2c0_grp";
|
||||
st,function = "i2c0";
|
||||
};
|
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mii0 {
|
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st,pins = "mii0_grp";
|
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st,function = "mii0";
|
||||
};
|
||||
ssp0 {
|
||||
st,pins = "ssp0_grp";
|
||||
st,function = "ssp0";
|
||||
};
|
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uart0 {
|
||||
st,pins = "uart0_grp";
|
||||
st,function = "uart0";
|
||||
};
|
||||
emi {
|
||||
st,pins = "emi_cs_0_to_5_grp";
|
||||
st,function = "emi";
|
||||
};
|
||||
fsmc {
|
||||
st,pins = "fsmc_grp";
|
||||
st,function = "fsmc";
|
||||
};
|
||||
uart1 {
|
||||
st,pins = "uart1_grp";
|
||||
st,function = "uart1";
|
||||
};
|
||||
uart2 {
|
||||
st,pins = "uart2_grp";
|
||||
st,function = "uart2";
|
||||
};
|
||||
uart3 {
|
||||
st,pins = "uart3_grp";
|
||||
st,function = "uart3";
|
||||
};
|
||||
uart4 {
|
||||
st,pins = "uart4_grp";
|
||||
st,function = "uart4";
|
||||
};
|
||||
uart5 {
|
||||
st,pins = "uart5_grp";
|
||||
st,function = "uart5";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dma@fc400000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -22,6 +22,11 @@
|
|||
0xb0000000 0xb0000000 0x10000000
|
||||
0xd0000000 0xd0000000 0x30000000>;
|
||||
|
||||
pinmux@b4000000 {
|
||||
compatible = "st,spear310-pinmux";
|
||||
reg = <0xb4000000 0x1000>;
|
||||
};
|
||||
|
||||
fsmc: flash@44000000 {
|
||||
compatible = "st,spear600-fsmc-nand";
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -25,6 +25,67 @@
|
|||
};
|
||||
|
||||
ahb {
|
||||
pinmux@b3000000 {
|
||||
st,pinmux-mode = <3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
i2c0 {
|
||||
st,pins = "i2c0_grp";
|
||||
st,function = "i2c0";
|
||||
};
|
||||
mii0 {
|
||||
st,pins = "mii0_grp";
|
||||
st,function = "mii0";
|
||||
};
|
||||
ssp0 {
|
||||
st,pins = "ssp0_grp";
|
||||
st,function = "ssp0";
|
||||
};
|
||||
uart0 {
|
||||
st,pins = "uart0_grp";
|
||||
st,function = "uart0";
|
||||
};
|
||||
sdhci {
|
||||
st,pins = "sdhci_cd_51_grp";
|
||||
st,function = "sdhci";
|
||||
};
|
||||
i2s {
|
||||
st,pins = "i2s_grp";
|
||||
st,function = "i2s";
|
||||
};
|
||||
uart1 {
|
||||
st,pins = "uart1_grp";
|
||||
st,function = "uart1";
|
||||
};
|
||||
uart2 {
|
||||
st,pins = "uart2_grp";
|
||||
st,function = "uart2";
|
||||
};
|
||||
can0 {
|
||||
st,pins = "can0_grp";
|
||||
st,function = "can0";
|
||||
};
|
||||
can1 {
|
||||
st,pins = "can1_grp";
|
||||
st,function = "can1";
|
||||
};
|
||||
mii2 {
|
||||
st,pins = "mii2_grp";
|
||||
st,function = "mii2";
|
||||
};
|
||||
pwm0_1 {
|
||||
st,pins = "pwm0_1_pin_14_15_grp";
|
||||
st,function = "pwm0_1";
|
||||
};
|
||||
pwm2 {
|
||||
st,pins = "pwm2_pin_13_grp";
|
||||
st,function = "pwm2";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clcd@90000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -18,9 +18,14 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x40000000 0x40000000 0x70000000
|
||||
ranges = <0x40000000 0x40000000 0x80000000
|
||||
0xd0000000 0xd0000000 0x30000000>;
|
||||
|
||||
pinmux@b3000000 {
|
||||
compatible = "st,spear320-pinmux";
|
||||
reg = <0xb3000000 0x1000>;
|
||||
};
|
||||
|
||||
clcd@90000000 {
|
||||
compatible = "arm,clcd-pl110", "arm,primecell";
|
||||
reg = <0x90000000 0x1000>;
|
||||
|
|
|
|||
|
|
@ -10,6 +10,50 @@
|
|||
reg = < 0x80000000 0x40000000 >;
|
||||
};
|
||||
|
||||
pinmux@70000000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
sdmmc1_clk_pz0 {
|
||||
nvidia,pins = "sdmmc1_clk_pz0";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc1_cmd_pz1 {
|
||||
nvidia,pins = "sdmmc1_cmd_pz1",
|
||||
"sdmmc1_dat0_py7",
|
||||
"sdmmc1_dat1_py6",
|
||||
"sdmmc1_dat2_py5",
|
||||
"sdmmc1_dat3_py4";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc4_clk_pcc4 {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4",
|
||||
"sdmmc4_rst_n_pcc3";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc4_dat0_paa0 {
|
||||
nvidia,pins = "sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial@70006000 {
|
||||
clock-frequency = < 408000000 >;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,6 +10,230 @@
|
|||
reg = < 0x00000000 0x40000000 >;
|
||||
};
|
||||
|
||||
pinmux@70000000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
ata {
|
||||
nvidia,pins = "ata";
|
||||
nvidia,function = "ide";
|
||||
};
|
||||
atb {
|
||||
nvidia,pins = "atb", "gma", "gme";
|
||||
nvidia,function = "sdio4";
|
||||
};
|
||||
atc {
|
||||
nvidia,pins = "atc";
|
||||
nvidia,function = "nand";
|
||||
};
|
||||
atd {
|
||||
nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
|
||||
"spia", "spib", "spic";
|
||||
nvidia,function = "gmi";
|
||||
};
|
||||
cdev1 {
|
||||
nvidia,pins = "cdev1";
|
||||
nvidia,function = "plla_out";
|
||||
};
|
||||
cdev2 {
|
||||
nvidia,pins = "cdev2";
|
||||
nvidia,function = "pllp_out4";
|
||||
};
|
||||
crtp {
|
||||
nvidia,pins = "crtp";
|
||||
nvidia,function = "crt";
|
||||
};
|
||||
csus {
|
||||
nvidia,pins = "csus";
|
||||
nvidia,function = "vi_sensor_clk";
|
||||
};
|
||||
dap1 {
|
||||
nvidia,pins = "dap1";
|
||||
nvidia,function = "dap1";
|
||||
};
|
||||
dap2 {
|
||||
nvidia,pins = "dap2";
|
||||
nvidia,function = "dap2";
|
||||
};
|
||||
dap3 {
|
||||
nvidia,pins = "dap3";
|
||||
nvidia,function = "dap3";
|
||||
};
|
||||
dap4 {
|
||||
nvidia,pins = "dap4";
|
||||
nvidia,function = "dap4";
|
||||
};
|
||||
ddc {
|
||||
nvidia,pins = "ddc";
|
||||
nvidia,function = "i2c2";
|
||||
};
|
||||
dta {
|
||||
nvidia,pins = "dta", "dtd";
|
||||
nvidia,function = "sdio2";
|
||||
};
|
||||
dtb {
|
||||
nvidia,pins = "dtb", "dtc", "dte";
|
||||
nvidia,function = "rsvd1";
|
||||
};
|
||||
dtf {
|
||||
nvidia,pins = "dtf";
|
||||
nvidia,function = "i2c3";
|
||||
};
|
||||
gmc {
|
||||
nvidia,pins = "gmc";
|
||||
nvidia,function = "uartd";
|
||||
};
|
||||
gpu7 {
|
||||
nvidia,pins = "gpu7";
|
||||
nvidia,function = "rtck";
|
||||
};
|
||||
gpv {
|
||||
nvidia,pins = "gpv", "slxa", "slxk";
|
||||
nvidia,function = "pcie";
|
||||
};
|
||||
hdint {
|
||||
nvidia,pins = "hdint", "pta";
|
||||
nvidia,function = "hdmi";
|
||||
};
|
||||
i2cp {
|
||||
nvidia,pins = "i2cp";
|
||||
nvidia,function = "i2cp";
|
||||
};
|
||||
irrx {
|
||||
nvidia,pins = "irrx", "irtx";
|
||||
nvidia,function = "uarta";
|
||||
};
|
||||
kbca {
|
||||
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
|
||||
"kbce", "kbcf";
|
||||
nvidia,function = "kbc";
|
||||
};
|
||||
lcsn {
|
||||
nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
|
||||
"ld3", "ld4", "ld5", "ld6", "ld7",
|
||||
"ld8", "ld9", "ld10", "ld11", "ld12",
|
||||
"ld13", "ld14", "ld15", "ld16", "ld17",
|
||||
"ldc", "ldi", "lhp0", "lhp1", "lhp2",
|
||||
"lhs", "lm0", "lm1", "lpp", "lpw0",
|
||||
"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
|
||||
"lsda", "lsdi", "lspi", "lvp0", "lvp1",
|
||||
"lvs";
|
||||
nvidia,function = "displaya";
|
||||
};
|
||||
owc {
|
||||
nvidia,pins = "owc", "spdi", "spdo", "uac";
|
||||
nvidia,function = "rsvd2";
|
||||
};
|
||||
pmc {
|
||||
nvidia,pins = "pmc";
|
||||
nvidia,function = "pwr_on";
|
||||
};
|
||||
rm {
|
||||
nvidia,pins = "rm";
|
||||
nvidia,function = "i2c1";
|
||||
};
|
||||
sdb {
|
||||
nvidia,pins = "sdb", "sdc", "sdd";
|
||||
nvidia,function = "pwm";
|
||||
};
|
||||
sdio1 {
|
||||
nvidia,pins = "sdio1";
|
||||
nvidia,function = "sdio1";
|
||||
};
|
||||
slxc {
|
||||
nvidia,pins = "slxc", "slxd";
|
||||
nvidia,function = "spdif";
|
||||
};
|
||||
spid {
|
||||
nvidia,pins = "spid", "spie", "spif";
|
||||
nvidia,function = "spi1";
|
||||
};
|
||||
spig {
|
||||
nvidia,pins = "spig", "spih";
|
||||
nvidia,function = "spi2_alt";
|
||||
};
|
||||
uaa {
|
||||
nvidia,pins = "uaa", "uab", "uda";
|
||||
nvidia,function = "ulpi";
|
||||
};
|
||||
uad {
|
||||
nvidia,pins = "uad";
|
||||
nvidia,function = "irda";
|
||||
};
|
||||
uca {
|
||||
nvidia,pins = "uca", "ucb";
|
||||
nvidia,function = "uartc";
|
||||
};
|
||||
conf_ata {
|
||||
nvidia,pins = "ata", "atb", "atc", "atd", "ate",
|
||||
"cdev1", "dap1", "dtb", "gma", "gmb",
|
||||
"gmc", "gmd", "gme", "gpu7", "gpv",
|
||||
"i2cp", "pta", "rm", "slxa", "slxk",
|
||||
"spia", "spib";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_cdev2 {
|
||||
nvidia,pins = "cdev2", "csus", "spid", "spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
||||
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
||||
nvidia,pull = <0>;
|
||||
};
|
||||
conf_crtp {
|
||||
nvidia,pins = "crtp", "dap2", "dap3", "dap4",
|
||||
"dtc", "dte", "dtf", "gpu", "sdio1",
|
||||
"slxc", "slxd", "spdi", "spdo", "spig",
|
||||
"uac", "uda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_ddc {
|
||||
nvidia,pins = "ddc", "dta", "dtd", "kbca",
|
||||
"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
|
||||
"sdc";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_hdint {
|
||||
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
|
||||
"lpw1", "lsc1", "lsck", "lsda", "lsdi",
|
||||
"lvp0", "owc", "sdb";
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_irrx {
|
||||
nvidia,pins = "irrx", "irtx", "sdd", "spic",
|
||||
"spie", "spih", "uaa", "uab", "uad",
|
||||
"uca", "ucb";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_lc {
|
||||
nvidia,pins = "lc", "ls";
|
||||
nvidia,pull = <2>;
|
||||
};
|
||||
conf_ld0 {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
||||
"ld5", "ld6", "ld7", "ld8", "ld9",
|
||||
"ld10", "ld11", "ld12", "ld13", "ld14",
|
||||
"ld15", "ld16", "ld17", "ldi", "lhp0",
|
||||
"lhp1", "lhp2", "lhs", "lm0", "lpp",
|
||||
"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
|
||||
"lvs", "pmc";
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmc@7000f400 {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,6 +10,226 @@
|
|||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
pinmux@70000000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
ata {
|
||||
nvidia,pins = "ata", "atc", "atd", "ate",
|
||||
"dap2", "gmb", "gmc", "gmd", "spia",
|
||||
"spib", "spic", "spid", "spie";
|
||||
nvidia,function = "gmi";
|
||||
};
|
||||
atb {
|
||||
nvidia,pins = "atb", "gma", "gme";
|
||||
nvidia,function = "sdio4";
|
||||
};
|
||||
cdev1 {
|
||||
nvidia,pins = "cdev1";
|
||||
nvidia,function = "plla_out";
|
||||
};
|
||||
cdev2 {
|
||||
nvidia,pins = "cdev2";
|
||||
nvidia,function = "pllp_out4";
|
||||
};
|
||||
crtp {
|
||||
nvidia,pins = "crtp";
|
||||
nvidia,function = "crt";
|
||||
};
|
||||
csus {
|
||||
nvidia,pins = "csus";
|
||||
nvidia,function = "pllc_out1";
|
||||
};
|
||||
dap1 {
|
||||
nvidia,pins = "dap1";
|
||||
nvidia,function = "dap1";
|
||||
};
|
||||
dap3 {
|
||||
nvidia,pins = "dap3";
|
||||
nvidia,function = "dap3";
|
||||
};
|
||||
dap4 {
|
||||
nvidia,pins = "dap4";
|
||||
nvidia,function = "dap4";
|
||||
};
|
||||
ddc {
|
||||
nvidia,pins = "ddc";
|
||||
nvidia,function = "i2c2";
|
||||
};
|
||||
dta {
|
||||
nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
|
||||
nvidia,function = "rsvd1";
|
||||
};
|
||||
dtf {
|
||||
nvidia,pins = "dtf";
|
||||
nvidia,function = "i2c3";
|
||||
};
|
||||
gpu {
|
||||
nvidia,pins = "gpu", "sdb", "sdd";
|
||||
nvidia,function = "pwm";
|
||||
};
|
||||
gpu7 {
|
||||
nvidia,pins = "gpu7";
|
||||
nvidia,function = "rtck";
|
||||
};
|
||||
gpv {
|
||||
nvidia,pins = "gpv", "slxa", "slxk";
|
||||
nvidia,function = "pcie";
|
||||
};
|
||||
hdint {
|
||||
nvidia,pins = "hdint", "pta";
|
||||
nvidia,function = "hdmi";
|
||||
};
|
||||
i2cp {
|
||||
nvidia,pins = "i2cp";
|
||||
nvidia,function = "i2cp";
|
||||
};
|
||||
irrx {
|
||||
nvidia,pins = "irrx", "irtx";
|
||||
nvidia,function = "uarta";
|
||||
};
|
||||
kbca {
|
||||
nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
|
||||
nvidia,function = "kbc";
|
||||
};
|
||||
kbcb {
|
||||
nvidia,pins = "kbcb", "kbcd";
|
||||
nvidia,function = "sdio2";
|
||||
};
|
||||
lcsn {
|
||||
nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
|
||||
"ld3", "ld4", "ld5", "ld6", "ld7",
|
||||
"ld8", "ld9", "ld10", "ld11", "ld12",
|
||||
"ld13", "ld14", "ld15", "ld16", "ld17",
|
||||
"ldc", "ldi", "lhp0", "lhp1", "lhp2",
|
||||
"lhs", "lm0", "lm1", "lpp", "lpw0",
|
||||
"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
|
||||
"lsda", "lsdi", "lspi", "lvp0", "lvp1",
|
||||
"lvs";
|
||||
nvidia,function = "displaya";
|
||||
};
|
||||
owc {
|
||||
nvidia,pins = "owc";
|
||||
nvidia,function = "owr";
|
||||
};
|
||||
pmc {
|
||||
nvidia,pins = "pmc";
|
||||
nvidia,function = "pwr_on";
|
||||
};
|
||||
rm {
|
||||
nvidia,pins = "rm";
|
||||
nvidia,function = "i2c1";
|
||||
};
|
||||
sdc {
|
||||
nvidia,pins = "sdc";
|
||||
nvidia,function = "twc";
|
||||
};
|
||||
sdio1 {
|
||||
nvidia,pins = "sdio1";
|
||||
nvidia,function = "sdio1";
|
||||
};
|
||||
slxc {
|
||||
nvidia,pins = "slxc", "slxd";
|
||||
nvidia,function = "spi4";
|
||||
};
|
||||
spdi {
|
||||
nvidia,pins = "spdi", "spdo";
|
||||
nvidia,function = "rsvd2";
|
||||
};
|
||||
spif {
|
||||
nvidia,pins = "spif", "uac";
|
||||
nvidia,function = "rsvd4";
|
||||
};
|
||||
spig {
|
||||
nvidia,pins = "spig", "spih";
|
||||
nvidia,function = "spi2_alt";
|
||||
};
|
||||
uaa {
|
||||
nvidia,pins = "uaa", "uab", "uda";
|
||||
nvidia,function = "ulpi";
|
||||
};
|
||||
uad {
|
||||
nvidia,pins = "uad";
|
||||
nvidia,function = "spdif";
|
||||
};
|
||||
uca {
|
||||
nvidia,pins = "uca", "ucb";
|
||||
nvidia,function = "uartc";
|
||||
};
|
||||
conf_ata {
|
||||
nvidia,pins = "ata", "atb", "atc", "atd", "ate",
|
||||
"cdev1", "dap1", "dap2", "dtf", "gma",
|
||||
"gmb", "gmc", "gmd", "gme", "gpu",
|
||||
"gpu7", "gpv", "i2cp", "pta", "rm",
|
||||
"sdio1", "slxk", "spdo", "uac", "uda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_cdev2 {
|
||||
nvidia,pins = "cdev2";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
||||
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
||||
nvidia,pull = <0>;
|
||||
};
|
||||
conf_crtp {
|
||||
nvidia,pins = "crtp", "dap3", "dap4", "dtb",
|
||||
"dtc", "dte", "slxa", "slxc", "slxd",
|
||||
"spdi";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_csus {
|
||||
nvidia,pins = "csus", "spia", "spib", "spid",
|
||||
"spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_ddc {
|
||||
nvidia,pins = "ddc", "irrx", "irtx", "kbca",
|
||||
"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
|
||||
"spic", "spig", "uaa", "uab";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_dta {
|
||||
nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
|
||||
"spie", "spih", "uad", "uca", "ucb";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_hdint {
|
||||
nvidia,pins = "hdint", "ld0", "ld1", "ld2",
|
||||
"ld3", "ld4", "ld5", "ld6", "ld7",
|
||||
"ld8", "ld9", "ld10", "ld11", "ld12",
|
||||
"ld13", "ld14", "ld15", "ld16", "ld17",
|
||||
"ldc", "ldi", "lhs", "lsc0", "lspi",
|
||||
"lvs", "pmc";
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_lc {
|
||||
nvidia,pins = "lc", "ls";
|
||||
nvidia,pull = <2>;
|
||||
};
|
||||
conf_lcsn {
|
||||
nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
|
||||
"lm0", "lm1", "lpp", "lpw0", "lpw1",
|
||||
"lpw2", "lsc1", "lsck", "lsda", "lsdi",
|
||||
"lvp0", "lvp1", "sdb";
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
|
|
|
|||
|
|
@ -11,6 +11,249 @@
|
|||
reg = < 0x00000000 0x40000000 >;
|
||||
};
|
||||
|
||||
pinmux@70000000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
ata {
|
||||
nvidia,pins = "ata";
|
||||
nvidia,function = "ide";
|
||||
};
|
||||
atb {
|
||||
nvidia,pins = "atb", "gma", "gme";
|
||||
nvidia,function = "sdio4";
|
||||
};
|
||||
atc {
|
||||
nvidia,pins = "atc";
|
||||
nvidia,function = "nand";
|
||||
};
|
||||
atd {
|
||||
nvidia,pins = "atd", "ate", "gmb", "spia",
|
||||
"spib", "spic";
|
||||
nvidia,function = "gmi";
|
||||
};
|
||||
cdev1 {
|
||||
nvidia,pins = "cdev1";
|
||||
nvidia,function = "plla_out";
|
||||
};
|
||||
cdev2 {
|
||||
nvidia,pins = "cdev2";
|
||||
nvidia,function = "pllp_out4";
|
||||
};
|
||||
crtp {
|
||||
nvidia,pins = "crtp", "lm1";
|
||||
nvidia,function = "crt";
|
||||
};
|
||||
csus {
|
||||
nvidia,pins = "csus";
|
||||
nvidia,function = "vi_sensor_clk";
|
||||
};
|
||||
dap1 {
|
||||
nvidia,pins = "dap1";
|
||||
nvidia,function = "dap1";
|
||||
};
|
||||
dap2 {
|
||||
nvidia,pins = "dap2";
|
||||
nvidia,function = "dap2";
|
||||
};
|
||||
dap3 {
|
||||
nvidia,pins = "dap3";
|
||||
nvidia,function = "dap3";
|
||||
};
|
||||
dap4 {
|
||||
nvidia,pins = "dap4";
|
||||
nvidia,function = "dap4";
|
||||
};
|
||||
ddc {
|
||||
nvidia,pins = "ddc", "owc", "spdi", "spdo",
|
||||
"uac";
|
||||
nvidia,function = "rsvd2";
|
||||
};
|
||||
dta {
|
||||
nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
|
||||
nvidia,function = "vi";
|
||||
};
|
||||
dtf {
|
||||
nvidia,pins = "dtf";
|
||||
nvidia,function = "i2c3";
|
||||
};
|
||||
gmc {
|
||||
nvidia,pins = "gmc";
|
||||
nvidia,function = "uartd";
|
||||
};
|
||||
gmd {
|
||||
nvidia,pins = "gmd";
|
||||
nvidia,function = "sflash";
|
||||
};
|
||||
gpu {
|
||||
nvidia,pins = "gpu";
|
||||
nvidia,function = "pwm";
|
||||
};
|
||||
gpu7 {
|
||||
nvidia,pins = "gpu7";
|
||||
nvidia,function = "rtck";
|
||||
};
|
||||
gpv {
|
||||
nvidia,pins = "gpv", "slxa", "slxk";
|
||||
nvidia,function = "pcie";
|
||||
};
|
||||
hdint {
|
||||
nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
|
||||
"lsck", "lsda", "pta";
|
||||
nvidia,function = "hdmi";
|
||||
};
|
||||
i2cp {
|
||||
nvidia,pins = "i2cp";
|
||||
nvidia,function = "i2cp";
|
||||
};
|
||||
irrx {
|
||||
nvidia,pins = "irrx", "irtx";
|
||||
nvidia,function = "uartb";
|
||||
};
|
||||
kbca {
|
||||
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
|
||||
"kbce", "kbcf";
|
||||
nvidia,function = "kbc";
|
||||
};
|
||||
lcsn {
|
||||
nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
|
||||
"lsdi", "lvp0";
|
||||
nvidia,function = "rsvd4";
|
||||
};
|
||||
ld0 {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
||||
"ld5", "ld6", "ld7", "ld8", "ld9",
|
||||
"ld10", "ld11", "ld12", "ld13", "ld14",
|
||||
"ld15", "ld16", "ld17", "ldi", "lhp0",
|
||||
"lhp1", "lhp2", "lhs", "lpp", "lsc0",
|
||||
"lspi", "lvp1", "lvs";
|
||||
nvidia,function = "displaya";
|
||||
};
|
||||
pmc {
|
||||
nvidia,pins = "pmc";
|
||||
nvidia,function = "pwr_on";
|
||||
};
|
||||
rm {
|
||||
nvidia,pins = "rm";
|
||||
nvidia,function = "i2c1";
|
||||
};
|
||||
sdb {
|
||||
nvidia,pins = "sdb", "sdc", "sdd";
|
||||
nvidia,function = "sdio3";
|
||||
};
|
||||
sdio1 {
|
||||
nvidia,pins = "sdio1";
|
||||
nvidia,function = "sdio1";
|
||||
};
|
||||
slxc {
|
||||
nvidia,pins = "slxc", "slxd";
|
||||
nvidia,function = "spdif";
|
||||
};
|
||||
spid {
|
||||
nvidia,pins = "spid", "spie", "spif";
|
||||
nvidia,function = "spi1";
|
||||
};
|
||||
spig {
|
||||
nvidia,pins = "spig", "spih";
|
||||
nvidia,function = "spi2_alt";
|
||||
};
|
||||
uaa {
|
||||
nvidia,pins = "uaa", "uab", "uda";
|
||||
nvidia,function = "ulpi";
|
||||
};
|
||||
uad {
|
||||
nvidia,pins = "uad";
|
||||
nvidia,function = "irda";
|
||||
};
|
||||
uca {
|
||||
nvidia,pins = "uca", "ucb";
|
||||
nvidia,function = "uartc";
|
||||
};
|
||||
conf_ata {
|
||||
nvidia,pins = "ata", "atb", "atc", "atd",
|
||||
"cdev1", "cdev2", "dap1", "dap2",
|
||||
"dap4", "dtf", "gma", "gmc", "gmd",
|
||||
"gme", "gpu", "gpu7", "i2cp", "irrx",
|
||||
"irtx", "pta", "rm", "sdc", "sdd",
|
||||
"slxd", "slxk", "spdi", "spdo", "uac",
|
||||
"uad", "uca", "ucb", "uda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_ate {
|
||||
nvidia,pins = "ate", "csus", "dap3", "ddc",
|
||||
"gpv", "owc", "slxc", "spib", "spid",
|
||||
"spie";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
||||
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
||||
nvidia,pull = <0>;
|
||||
};
|
||||
conf_crtp {
|
||||
nvidia,pins = "crtp", "gmb", "slxa", "spia",
|
||||
"spig", "spih";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_dta {
|
||||
nvidia,pins = "dta", "dtb", "dtc", "dtd";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_dte {
|
||||
nvidia,pins = "dte", "spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_hdint {
|
||||
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
|
||||
"lpw1", "lsc1", "lsck", "lsda", "lsdi",
|
||||
"lvp0";
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_kbca {
|
||||
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
|
||||
"kbce", "kbcf", "sdio1", "spic", "uaa",
|
||||
"uab";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_lc {
|
||||
nvidia,pins = "lc", "ls";
|
||||
nvidia,pull = <2>;
|
||||
};
|
||||
conf_ld0 {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
||||
"ld5", "ld6", "ld7", "ld8", "ld9",
|
||||
"ld10", "ld11", "ld12", "ld13", "ld14",
|
||||
"ld15", "ld16", "ld17", "ldi", "lhp0",
|
||||
"lhp1", "lhp2", "lhs", "lm0", "lpp",
|
||||
"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
|
||||
"lvs", "pmc", "sdb";
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
};
|
||||
drive_sdio1 {
|
||||
nvidia,pins = "drive_sdio1";
|
||||
nvidia,high-speed-mode = <0>;
|
||||
nvidia,schmitt = <0>;
|
||||
nvidia,low-power-mode = <3>;
|
||||
nvidia,pull-down-strength = <31>;
|
||||
nvidia,pull-up-strength = <31>;
|
||||
nvidia,slew-rate-rising = <3>;
|
||||
nvidia,slew-rate-falling = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,236 @@
|
|||
reg = < 0x00000000 0x40000000 >;
|
||||
};
|
||||
|
||||
pinmux@70000000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
ata {
|
||||
nvidia,pins = "ata";
|
||||
nvidia,function = "ide";
|
||||
};
|
||||
atb {
|
||||
nvidia,pins = "atb", "gma";
|
||||
nvidia,function = "sdio4";
|
||||
};
|
||||
atc {
|
||||
nvidia,pins = "atc", "gmb";
|
||||
nvidia,function = "nand";
|
||||
};
|
||||
atd {
|
||||
nvidia,pins = "atd", "ate", "gme", "pta";
|
||||
nvidia,function = "gmi";
|
||||
};
|
||||
cdev1 {
|
||||
nvidia,pins = "cdev1";
|
||||
nvidia,function = "plla_out";
|
||||
};
|
||||
cdev2 {
|
||||
nvidia,pins = "cdev2";
|
||||
nvidia,function = "pllp_out4";
|
||||
};
|
||||
crtp {
|
||||
nvidia,pins = "crtp";
|
||||
nvidia,function = "crt";
|
||||
};
|
||||
csus {
|
||||
nvidia,pins = "csus";
|
||||
nvidia,function = "vi_sensor_clk";
|
||||
};
|
||||
dap1 {
|
||||
nvidia,pins = "dap1";
|
||||
nvidia,function = "dap1";
|
||||
};
|
||||
dap2 {
|
||||
nvidia,pins = "dap2";
|
||||
nvidia,function = "dap2";
|
||||
};
|
||||
dap3 {
|
||||
nvidia,pins = "dap3";
|
||||
nvidia,function = "dap3";
|
||||
};
|
||||
dap4 {
|
||||
nvidia,pins = "dap4";
|
||||
nvidia,function = "dap4";
|
||||
};
|
||||
ddc {
|
||||
nvidia,pins = "ddc";
|
||||
nvidia,function = "i2c2";
|
||||
};
|
||||
dta {
|
||||
nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
|
||||
nvidia,function = "vi";
|
||||
};
|
||||
dtf {
|
||||
nvidia,pins = "dtf";
|
||||
nvidia,function = "i2c3";
|
||||
};
|
||||
gmc {
|
||||
nvidia,pins = "gmc", "gmd";
|
||||
nvidia,function = "sflash";
|
||||
};
|
||||
gpu {
|
||||
nvidia,pins = "gpu";
|
||||
nvidia,function = "uarta";
|
||||
};
|
||||
gpu7 {
|
||||
nvidia,pins = "gpu7";
|
||||
nvidia,function = "rtck";
|
||||
};
|
||||
gpv {
|
||||
nvidia,pins = "gpv", "slxa", "slxk";
|
||||
nvidia,function = "pcie";
|
||||
};
|
||||
hdint {
|
||||
nvidia,pins = "hdint";
|
||||
nvidia,function = "hdmi";
|
||||
};
|
||||
i2cp {
|
||||
nvidia,pins = "i2cp";
|
||||
nvidia,function = "i2cp";
|
||||
};
|
||||
irrx {
|
||||
nvidia,pins = "irrx", "irtx";
|
||||
nvidia,function = "uartb";
|
||||
};
|
||||
kbca {
|
||||
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
|
||||
"kbce", "kbcf";
|
||||
nvidia,function = "kbc";
|
||||
};
|
||||
lcsn {
|
||||
nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
|
||||
"ld3", "ld4", "ld5", "ld6", "ld7",
|
||||
"ld8", "ld9", "ld10", "ld11", "ld12",
|
||||
"ld13", "ld14", "ld15", "ld16", "ld17",
|
||||
"ldc", "ldi", "lhp0", "lhp1", "lhp2",
|
||||
"lhs", "lm0", "lm1", "lpp", "lpw0",
|
||||
"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
|
||||
"lsda", "lsdi", "lspi", "lvp0", "lvp1",
|
||||
"lvs";
|
||||
nvidia,function = "displaya";
|
||||
};
|
||||
owc {
|
||||
nvidia,pins = "owc", "uac";
|
||||
nvidia,function = "rsvd2";
|
||||
};
|
||||
pmc {
|
||||
nvidia,pins = "pmc";
|
||||
nvidia,function = "pwr_on";
|
||||
};
|
||||
rm {
|
||||
nvidia,pins = "rm";
|
||||
nvidia,function = "i2c1";
|
||||
};
|
||||
sdb {
|
||||
nvidia,pins = "sdb", "sdc", "sdd";
|
||||
nvidia,function = "pwm";
|
||||
};
|
||||
sdio1 {
|
||||
nvidia,pins = "sdio1";
|
||||
nvidia,function = "sdio1";
|
||||
};
|
||||
slxc {
|
||||
nvidia,pins = "slxc", "slxd";
|
||||
nvidia,function = "sdio3";
|
||||
};
|
||||
spdi {
|
||||
nvidia,pins = "spdi", "spdo";
|
||||
nvidia,function = "spdif";
|
||||
};
|
||||
spia {
|
||||
nvidia,pins = "spia", "spib", "spic";
|
||||
nvidia,function = "spi2";
|
||||
};
|
||||
spid {
|
||||
nvidia,pins = "spid", "spie", "spif";
|
||||
nvidia,function = "spi1";
|
||||
};
|
||||
spig {
|
||||
nvidia,pins = "spig", "spih";
|
||||
nvidia,function = "spi2_alt";
|
||||
};
|
||||
uaa {
|
||||
nvidia,pins = "uaa", "uab", "uda";
|
||||
nvidia,function = "ulpi";
|
||||
};
|
||||
uad {
|
||||
nvidia,pins = "uad";
|
||||
nvidia,function = "irda";
|
||||
};
|
||||
uca {
|
||||
nvidia,pins = "uca", "ucb";
|
||||
nvidia,function = "uartc";
|
||||
};
|
||||
conf_ata {
|
||||
nvidia,pins = "ata", "atc", "atd", "ate",
|
||||
"crtp", "dap2", "dap3", "dap4", "dta",
|
||||
"dtb", "dtc", "dtd", "dte", "gmb",
|
||||
"gme", "i2cp", "pta", "slxc", "slxd",
|
||||
"spdi", "spdo", "uda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_atb {
|
||||
nvidia,pins = "atb", "cdev1", "dap1", "gma",
|
||||
"gmc", "gmd", "gpu", "gpu7", "gpv",
|
||||
"sdio1", "slxa", "slxk", "uac";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_cdev2 {
|
||||
nvidia,pins = "cdev2", "csus", "spia", "spib",
|
||||
"spid", "spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
||||
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
||||
nvidia,pull = <0>;
|
||||
};
|
||||
conf_ddc {
|
||||
nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_hdint {
|
||||
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
|
||||
"lpw1", "lsc1", "lsck", "lsda", "lsdi",
|
||||
"lvp0", "pmc";
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_irrx {
|
||||
nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
|
||||
"kbcc", "kbcd", "kbce", "kbcf", "owc",
|
||||
"spic", "spie", "spig", "spih", "uaa",
|
||||
"uab", "uad", "uca", "ucb";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_lc {
|
||||
nvidia,pins = "lc", "ls";
|
||||
nvidia,pull = <2>;
|
||||
};
|
||||
conf_ld0 {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
||||
"ld5", "ld6", "ld7", "ld8", "ld9",
|
||||
"ld10", "ld11", "ld12", "ld13", "ld14",
|
||||
"ld15", "ld16", "ld17", "ldi", "lhp0",
|
||||
"lhp1", "lhp2", "lhs", "lm0", "lpp",
|
||||
"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
|
||||
"lvs", "sdb";
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,6 +10,236 @@
|
|||
reg = < 0x00000000 0x40000000 >;
|
||||
};
|
||||
|
||||
pinmux@70000000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
ata {
|
||||
nvidia,pins = "ata";
|
||||
nvidia,function = "ide";
|
||||
};
|
||||
atb {
|
||||
nvidia,pins = "atb", "gma", "gme";
|
||||
nvidia,function = "sdio4";
|
||||
};
|
||||
atc {
|
||||
nvidia,pins = "atc";
|
||||
nvidia,function = "nand";
|
||||
};
|
||||
atd {
|
||||
nvidia,pins = "atd", "ate", "gmb", "spia",
|
||||
"spib", "spic";
|
||||
nvidia,function = "gmi";
|
||||
};
|
||||
cdev1 {
|
||||
nvidia,pins = "cdev1";
|
||||
nvidia,function = "plla_out";
|
||||
};
|
||||
cdev2 {
|
||||
nvidia,pins = "cdev2";
|
||||
nvidia,function = "pllp_out4";
|
||||
};
|
||||
crtp {
|
||||
nvidia,pins = "crtp", "lm1";
|
||||
nvidia,function = "crt";
|
||||
};
|
||||
csus {
|
||||
nvidia,pins = "csus";
|
||||
nvidia,function = "vi_sensor_clk";
|
||||
};
|
||||
dap1 {
|
||||
nvidia,pins = "dap1";
|
||||
nvidia,function = "dap1";
|
||||
};
|
||||
dap2 {
|
||||
nvidia,pins = "dap2";
|
||||
nvidia,function = "dap2";
|
||||
};
|
||||
dap3 {
|
||||
nvidia,pins = "dap3";
|
||||
nvidia,function = "dap3";
|
||||
};
|
||||
dap4 {
|
||||
nvidia,pins = "dap4";
|
||||
nvidia,function = "dap4";
|
||||
};
|
||||
ddc {
|
||||
nvidia,pins = "ddc", "owc", "spdi", "spdo",
|
||||
"uac";
|
||||
nvidia,function = "rsvd2";
|
||||
};
|
||||
dta {
|
||||
nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
|
||||
nvidia,function = "vi";
|
||||
};
|
||||
dtf {
|
||||
nvidia,pins = "dtf";
|
||||
nvidia,function = "i2c3";
|
||||
};
|
||||
gmc {
|
||||
nvidia,pins = "gmc";
|
||||
nvidia,function = "uartd";
|
||||
};
|
||||
gmd {
|
||||
nvidia,pins = "gmd";
|
||||
nvidia,function = "sflash";
|
||||
};
|
||||
gpu {
|
||||
nvidia,pins = "gpu";
|
||||
nvidia,function = "pwm";
|
||||
};
|
||||
gpu7 {
|
||||
nvidia,pins = "gpu7";
|
||||
nvidia,function = "rtck";
|
||||
};
|
||||
gpv {
|
||||
nvidia,pins = "gpv", "slxa", "slxk";
|
||||
nvidia,function = "pcie";
|
||||
};
|
||||
hdint {
|
||||
nvidia,pins = "hdint", "pta";
|
||||
nvidia,function = "hdmi";
|
||||
};
|
||||
i2cp {
|
||||
nvidia,pins = "i2cp";
|
||||
nvidia,function = "i2cp";
|
||||
};
|
||||
irrx {
|
||||
nvidia,pins = "irrx", "irtx";
|
||||
nvidia,function = "uartb";
|
||||
};
|
||||
kbca {
|
||||
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
|
||||
"kbce", "kbcf";
|
||||
nvidia,function = "kbc";
|
||||
};
|
||||
lcsn {
|
||||
nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
|
||||
"lsdi", "lvp0";
|
||||
nvidia,function = "rsvd4";
|
||||
};
|
||||
ld0 {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
||||
"ld5", "ld6", "ld7", "ld8", "ld9",
|
||||
"ld10", "ld11", "ld12", "ld13", "ld14",
|
||||
"ld15", "ld16", "ld17", "ldi", "lhp0",
|
||||
"lhp1", "lhp2", "lhs", "lpp", "lpw0",
|
||||
"lpw2", "lsc0", "lsc1", "lsck", "lsda",
|
||||
"lspi", "lvp1", "lvs";
|
||||
nvidia,function = "displaya";
|
||||
};
|
||||
pmc {
|
||||
nvidia,pins = "pmc";
|
||||
nvidia,function = "pwr_on";
|
||||
};
|
||||
rm {
|
||||
nvidia,pins = "rm";
|
||||
nvidia,function = "i2c1";
|
||||
};
|
||||
sdb {
|
||||
nvidia,pins = "sdb", "sdc", "sdd", "slxc";
|
||||
nvidia,function = "sdio3";
|
||||
};
|
||||
sdio1 {
|
||||
nvidia,pins = "sdio1";
|
||||
nvidia,function = "sdio1";
|
||||
};
|
||||
slxd {
|
||||
nvidia,pins = "slxd";
|
||||
nvidia,function = "spdif";
|
||||
};
|
||||
spid {
|
||||
nvidia,pins = "spid", "spie", "spif";
|
||||
nvidia,function = "spi1";
|
||||
};
|
||||
spig {
|
||||
nvidia,pins = "spig", "spih";
|
||||
nvidia,function = "spi2_alt";
|
||||
};
|
||||
uaa {
|
||||
nvidia,pins = "uaa", "uab", "uda";
|
||||
nvidia,function = "ulpi";
|
||||
};
|
||||
uad {
|
||||
nvidia,pins = "uad";
|
||||
nvidia,function = "irda";
|
||||
};
|
||||
uca {
|
||||
nvidia,pins = "uca", "ucb";
|
||||
nvidia,function = "uartc";
|
||||
};
|
||||
conf_ata {
|
||||
nvidia,pins = "ata", "atb", "atc", "atd",
|
||||
"cdev1", "cdev2", "dap1", "dap2",
|
||||
"dap4", "ddc", "dtf", "gma", "gmc",
|
||||
"gme", "gpu", "gpu7", "i2cp", "irrx",
|
||||
"irtx", "pta", "rm", "sdc", "sdd",
|
||||
"slxc", "slxd", "slxk", "spdi", "spdo",
|
||||
"uac", "uad", "uca", "ucb", "uda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_ate {
|
||||
nvidia,pins = "ate", "csus", "dap3", "gmd",
|
||||
"gpv", "owc", "spia", "spib", "spic",
|
||||
"spid", "spie", "spig";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
||||
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
||||
nvidia,pull = <0>;
|
||||
};
|
||||
conf_crtp {
|
||||
nvidia,pins = "crtp", "gmb", "slxa", "spih";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_dta {
|
||||
nvidia,pins = "dta", "dtb", "dtc", "dtd";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_dte {
|
||||
nvidia,pins = "dte", "spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_hdint {
|
||||
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
|
||||
"lpw1", "lsck", "lsda", "lsdi", "lvp0";
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_kbca {
|
||||
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
|
||||
"kbce", "kbcf", "sdio1", "uaa", "uab";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_lc {
|
||||
nvidia,pins = "lc", "ls";
|
||||
nvidia,pull = <2>;
|
||||
};
|
||||
conf_ld0 {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
||||
"ld5", "ld6", "ld7", "ld8", "ld9",
|
||||
"ld10", "ld11", "ld12", "ld13", "ld14",
|
||||
"ld15", "ld16", "ld17", "ldi", "lhp0",
|
||||
"lhp1", "lhp2", "lhs", "lm0", "lpp",
|
||||
"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
|
||||
"lvp1", "lvs", "pmc", "sdb";
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
|
|
|
|||
|
|
@ -97,6 +97,7 @@ CONFIG_I2C=y
|
|||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_GPIO=y
|
||||
CONFIG_DEBUG_GPIO=y
|
||||
CONFIG_PINCTRL_NOMADIK=y
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_RTC_CLASS=y
|
||||
|
|
|
|||
|
|
@ -844,6 +844,8 @@ config SOC_IMX6Q
|
|||
select HAVE_IMX_MMDC
|
||||
select HAVE_IMX_SRC
|
||||
select HAVE_SMP
|
||||
select PINCTRL
|
||||
select PINCTRL_IMX6Q
|
||||
select USE_OF
|
||||
|
||||
help
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/irqdomain.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/common.h>
|
||||
|
|
@ -81,6 +82,8 @@ static void __init imx51_dt_init(void)
|
|||
|
||||
of_irq_init(imx51_irq_match);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
|
||||
node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
|
||||
if (node) {
|
||||
of_id = of_match_node(imx51_iomuxc_of_match, node);
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
#include <linux/irqdomain.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/common.h>
|
||||
|
|
@ -88,6 +89,8 @@ static void __init imx53_dt_init(void)
|
|||
|
||||
of_irq_init(imx53_irq_match);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
|
||||
node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
|
||||
if (node) {
|
||||
of_id = of_match_node(imx53_iomuxc_of_match, node);
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/micrel_phy.h>
|
||||
#include <asm/smp_twd.h>
|
||||
|
|
@ -77,6 +78,12 @@ static int ksz9021rn_phy_fixup(struct phy_device *phydev)
|
|||
|
||||
static void __init imx6q_init_machine(void)
|
||||
{
|
||||
/*
|
||||
* This should be removed when all imx6q boards have pinctrl
|
||||
* states for devices defined in device tree.
|
||||
*/
|
||||
pinctrl_provide_dummies();
|
||||
|
||||
if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
|
||||
phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
|
||||
ksz9021rn_phy_fixup);
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
|
|
@ -58,4 +59,5 @@ void __init imx1_soc_init(void)
|
|||
MX1_GPIO_INT_PORTC, 0);
|
||||
mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256,
|
||||
MX1_GPIO_INT_PORTD, 0);
|
||||
pinctrl_provide_dummies();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/devices-common.h>
|
||||
|
|
@ -88,6 +89,7 @@ void __init imx21_soc_init(void)
|
|||
mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
|
||||
mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
imx_add_imx_dma();
|
||||
platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res,
|
||||
ARRAY_SIZE(imx21_audmux_res));
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
|
@ -95,6 +96,7 @@ void __init imx25_soc_init(void)
|
|||
mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
|
||||
mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
/* i.mx25 has the i.mx35 type sdma */
|
||||
imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
|
||||
/* i.mx25 has the i.mx31 type audmux */
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/devices-common.h>
|
||||
|
|
@ -89,6 +90,7 @@ void __init imx27_soc_init(void)
|
|||
mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
|
||||
mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
imx_add_imx_dma();
|
||||
/* imx27 has the imx21 type audmux */
|
||||
platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/system_misc.h>
|
||||
|
|
@ -267,6 +268,7 @@ void __init imx35_soc_init(void)
|
|||
mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
|
||||
mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
if (to_version == 1) {
|
||||
strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
|
||||
strlen(imx35_sdma_pdata.fw_name));
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/system_misc.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
|
@ -223,6 +224,7 @@ void __init imx53_soc_init(void)
|
|||
mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
|
||||
mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
/* i.mx53 has the i.mx35 type sdma */
|
||||
imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
|
||||
|
||||
|
|
|
|||
|
|
@ -9,11 +9,13 @@ config SOC_IMX23
|
|||
bool
|
||||
select CPU_ARM926T
|
||||
select HAVE_PWM
|
||||
select PINCTRL_IMX23
|
||||
|
||||
config SOC_IMX28
|
||||
bool
|
||||
select CPU_ARM926T
|
||||
select HAVE_PWM
|
||||
select PINCTRL_IMX28
|
||||
|
||||
comment "MXS platforms:"
|
||||
|
||||
|
|
|
|||
|
|
@ -19,11 +19,13 @@ extern void mxs_timer_init(struct clk *, int);
|
|||
extern void mxs_restart(char, const char *);
|
||||
extern int mxs_saif_clkmux_select(unsigned int clkmux);
|
||||
|
||||
extern void mx23_soc_init(void);
|
||||
extern int mx23_register_gpios(void);
|
||||
extern int mx23_clocks_init(void);
|
||||
extern void mx23_map_io(void);
|
||||
extern void mx23_init_irq(void);
|
||||
|
||||
extern void mx28_soc_init(void);
|
||||
extern int mx28_register_gpios(void);
|
||||
extern int mx28_clocks_init(void);
|
||||
extern void mx28_map_io(void);
|
||||
|
|
|
|||
|
|
@ -207,6 +207,8 @@ static int apx4devkit_phy_fixup(struct phy_device *phy)
|
|||
|
||||
static void __init apx4devkit_init(void)
|
||||
{
|
||||
mx28_soc_init();
|
||||
|
||||
mxs_iomux_setup_multiple_pads(apx4devkit_pads,
|
||||
ARRAY_SIZE(apx4devkit_pads));
|
||||
|
||||
|
|
|
|||
|
|
@ -319,6 +319,8 @@ static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = {
|
|||
|
||||
static void __init m28evk_init(void)
|
||||
{
|
||||
mx28_soc_init();
|
||||
|
||||
mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads));
|
||||
|
||||
mx28_add_duart();
|
||||
|
|
|
|||
|
|
@ -141,6 +141,8 @@ static void __init mx23evk_init(void)
|
|||
{
|
||||
int ret;
|
||||
|
||||
mx23_soc_init();
|
||||
|
||||
mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
|
||||
|
||||
mx23_add_duart();
|
||||
|
|
|
|||
|
|
@ -413,6 +413,8 @@ static void __init mx28evk_init(void)
|
|||
{
|
||||
int ret;
|
||||
|
||||
mx28_soc_init();
|
||||
|
||||
mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
|
||||
|
||||
mx28_add_duart();
|
||||
|
|
|
|||
|
|
@ -85,6 +85,8 @@ static void __init stmp378x_dvb_init(void)
|
|||
{
|
||||
int ret;
|
||||
|
||||
mx23_soc_init();
|
||||
|
||||
mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads,
|
||||
ARRAY_SIZE(stmp378x_dvb_pads));
|
||||
|
||||
|
|
|
|||
|
|
@ -146,6 +146,8 @@ static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = {
|
|||
|
||||
static void __init tx28_stk5v3_init(void)
|
||||
{
|
||||
mx28_soc_init();
|
||||
|
||||
mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
|
||||
ARRAY_SIZE(tx28_stk5v3_pads));
|
||||
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
|
|
@ -61,3 +62,13 @@ void __init mx28_init_irq(void)
|
|||
{
|
||||
icoll_init_irq();
|
||||
}
|
||||
|
||||
void __init mx23_soc_init(void)
|
||||
{
|
||||
pinctrl_provide_dummies();
|
||||
}
|
||||
|
||||
void __init mx28_soc_init(void)
|
||||
{
|
||||
pinctrl_provide_dummies();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@ config NOMADIK_8815
|
|||
config I2C_BITBANG_8815NHK
|
||||
tristate "Driver for bit-bang busses found on the 8815 NHK"
|
||||
depends on I2C && MACH_NOMADIK_8815NHK
|
||||
depends on PINCTRL_NOMADIK
|
||||
select I2C_ALGOBIT
|
||||
default y
|
||||
|
||||
|
|
|
|||
|
|
@ -7,16 +7,19 @@ if ARCH_SPEAR3XX
|
|||
menu "SPEAr3xx Implementations"
|
||||
config MACH_SPEAR300
|
||||
bool "SPEAr300 Machine support with Device Tree"
|
||||
select PINCTRL_SPEAR300
|
||||
help
|
||||
Supports ST SPEAr300 machine configured via the device-tree
|
||||
|
||||
config MACH_SPEAR310
|
||||
bool "SPEAr310 Machine support with Device Tree"
|
||||
select PINCTRL_SPEAR310
|
||||
help
|
||||
Supports ST SPEAr310 machine configured via the device-tree
|
||||
|
||||
config MACH_SPEAR320
|
||||
bool "SPEAr320 Machine support with Device Tree"
|
||||
select PINCTRL_SPEAR320
|
||||
help
|
||||
Supports ST SPEAr320 machine configured via the device-tree
|
||||
endmenu
|
||||
|
|
|
|||
|
|
@ -20,7 +20,6 @@
|
|||
#include <linux/amba/bus.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <plat/padmux.h>
|
||||
|
||||
/* Add spear3xx family device structure declarations here */
|
||||
extern struct sys_timer spear3xx_timer;
|
||||
|
|
@ -34,147 +33,20 @@ void __init spear3xx_dt_init_irq(void);
|
|||
|
||||
void spear_restart(char, const char *);
|
||||
|
||||
/* pad mux declarations */
|
||||
#define PMX_FIRDA_MASK (1 << 14)
|
||||
#define PMX_I2C_MASK (1 << 13)
|
||||
#define PMX_SSP_CS_MASK (1 << 12)
|
||||
#define PMX_SSP_MASK (1 << 11)
|
||||
#define PMX_MII_MASK (1 << 10)
|
||||
#define PMX_GPIO_PIN0_MASK (1 << 9)
|
||||
#define PMX_GPIO_PIN1_MASK (1 << 8)
|
||||
#define PMX_GPIO_PIN2_MASK (1 << 7)
|
||||
#define PMX_GPIO_PIN3_MASK (1 << 6)
|
||||
#define PMX_GPIO_PIN4_MASK (1 << 5)
|
||||
#define PMX_GPIO_PIN5_MASK (1 << 4)
|
||||
#define PMX_UART0_MODEM_MASK (1 << 3)
|
||||
#define PMX_UART0_MASK (1 << 2)
|
||||
#define PMX_TIMER_3_4_MASK (1 << 1)
|
||||
#define PMX_TIMER_1_2_MASK (1 << 0)
|
||||
|
||||
/* pad mux devices */
|
||||
extern struct pmx_dev spear3xx_pmx_firda;
|
||||
extern struct pmx_dev spear3xx_pmx_i2c;
|
||||
extern struct pmx_dev spear3xx_pmx_ssp_cs;
|
||||
extern struct pmx_dev spear3xx_pmx_ssp;
|
||||
extern struct pmx_dev spear3xx_pmx_mii;
|
||||
extern struct pmx_dev spear3xx_pmx_gpio_pin0;
|
||||
extern struct pmx_dev spear3xx_pmx_gpio_pin1;
|
||||
extern struct pmx_dev spear3xx_pmx_gpio_pin2;
|
||||
extern struct pmx_dev spear3xx_pmx_gpio_pin3;
|
||||
extern struct pmx_dev spear3xx_pmx_gpio_pin4;
|
||||
extern struct pmx_dev spear3xx_pmx_gpio_pin5;
|
||||
extern struct pmx_dev spear3xx_pmx_uart0_modem;
|
||||
extern struct pmx_dev spear3xx_pmx_uart0;
|
||||
extern struct pmx_dev spear3xx_pmx_timer_3_4;
|
||||
extern struct pmx_dev spear3xx_pmx_timer_1_2;
|
||||
|
||||
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
|
||||
/* padmux plgpio devices */
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_28;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_29;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_30;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_31;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_32;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_33;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
|
||||
#endif
|
||||
|
||||
/* spear300 declarations */
|
||||
#ifdef CONFIG_MACH_SPEAR300
|
||||
/* pad mux modes */
|
||||
extern struct pmx_mode spear300_nand_mode;
|
||||
extern struct pmx_mode spear300_nor_mode;
|
||||
extern struct pmx_mode spear300_photo_frame_mode;
|
||||
extern struct pmx_mode spear300_lend_ip_phone_mode;
|
||||
extern struct pmx_mode spear300_hend_ip_phone_mode;
|
||||
extern struct pmx_mode spear300_lend_wifi_phone_mode;
|
||||
extern struct pmx_mode spear300_hend_wifi_phone_mode;
|
||||
extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
|
||||
extern struct pmx_mode spear300_ata_pabx_i2s_mode;
|
||||
extern struct pmx_mode spear300_caml_lcdw_mode;
|
||||
extern struct pmx_mode spear300_camu_lcd_mode;
|
||||
extern struct pmx_mode spear300_camu_wlcd_mode;
|
||||
extern struct pmx_mode spear300_caml_lcd_mode;
|
||||
|
||||
/* pad mux devices */
|
||||
extern struct pmx_dev spear300_pmx_fsmc_2_chips;
|
||||
extern struct pmx_dev spear300_pmx_fsmc_4_chips;
|
||||
extern struct pmx_dev spear300_pmx_keyboard;
|
||||
extern struct pmx_dev spear300_pmx_clcd;
|
||||
extern struct pmx_dev spear300_pmx_telecom_gpio;
|
||||
extern struct pmx_dev spear300_pmx_telecom_tdm;
|
||||
extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
|
||||
extern struct pmx_dev spear300_pmx_telecom_camera;
|
||||
extern struct pmx_dev spear300_pmx_telecom_dac;
|
||||
extern struct pmx_dev spear300_pmx_telecom_i2s;
|
||||
extern struct pmx_dev spear300_pmx_telecom_boot_pins;
|
||||
extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
|
||||
extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
|
||||
extern struct pmx_dev spear300_pmx_gpio1;
|
||||
|
||||
/* Add spear300 machine declarations here */
|
||||
void __init spear300_clk_init(void);
|
||||
|
||||
#endif /* CONFIG_MACH_SPEAR300 */
|
||||
|
||||
/* spear310 declarations */
|
||||
#ifdef CONFIG_MACH_SPEAR310
|
||||
/* pad mux devices */
|
||||
extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
|
||||
extern struct pmx_dev spear310_pmx_emi_cs_2_3;
|
||||
extern struct pmx_dev spear310_pmx_uart1;
|
||||
extern struct pmx_dev spear310_pmx_uart2;
|
||||
extern struct pmx_dev spear310_pmx_uart3_4_5;
|
||||
extern struct pmx_dev spear310_pmx_fsmc;
|
||||
extern struct pmx_dev spear310_pmx_rs485_0_1;
|
||||
extern struct pmx_dev spear310_pmx_tdm0;
|
||||
|
||||
/* Add spear310 machine declarations here */
|
||||
void __init spear310_clk_init(void);
|
||||
|
||||
#endif /* CONFIG_MACH_SPEAR310 */
|
||||
|
||||
/* spear320 declarations */
|
||||
#ifdef CONFIG_MACH_SPEAR320
|
||||
/* pad mux modes */
|
||||
extern struct pmx_mode spear320_auto_net_smii_mode;
|
||||
extern struct pmx_mode spear320_auto_net_mii_mode;
|
||||
extern struct pmx_mode spear320_auto_exp_mode;
|
||||
extern struct pmx_mode spear320_small_printers_mode;
|
||||
|
||||
/* pad mux devices */
|
||||
extern struct pmx_dev spear320_pmx_clcd;
|
||||
extern struct pmx_dev spear320_pmx_emi;
|
||||
extern struct pmx_dev spear320_pmx_fsmc;
|
||||
extern struct pmx_dev spear320_pmx_spp;
|
||||
extern struct pmx_dev spear320_pmx_sdhci;
|
||||
extern struct pmx_dev spear320_pmx_i2s;
|
||||
extern struct pmx_dev spear320_pmx_uart1;
|
||||
extern struct pmx_dev spear320_pmx_uart1_modem;
|
||||
extern struct pmx_dev spear320_pmx_uart2;
|
||||
extern struct pmx_dev spear320_pmx_touchscreen;
|
||||
extern struct pmx_dev spear320_pmx_can;
|
||||
extern struct pmx_dev spear320_pmx_sdhci_led;
|
||||
extern struct pmx_dev spear320_pmx_pwm0;
|
||||
extern struct pmx_dev spear320_pmx_pwm1;
|
||||
extern struct pmx_dev spear320_pmx_pwm2;
|
||||
extern struct pmx_dev spear320_pmx_pwm3;
|
||||
extern struct pmx_dev spear320_pmx_ssp1;
|
||||
extern struct pmx_dev spear320_pmx_ssp2;
|
||||
extern struct pmx_dev spear320_pmx_mii1;
|
||||
extern struct pmx_dev spear320_pmx_smii0;
|
||||
extern struct pmx_dev spear320_pmx_smii1;
|
||||
extern struct pmx_dev spear320_pmx_i2c1;
|
||||
|
||||
/* Add spear320 machine declarations here */
|
||||
void __init spear320_clk_init(void);
|
||||
|
||||
#endif /* CONFIG_MACH_SPEAR320 */
|
||||
|
|
|
|||
|
|
@ -60,357 +60,6 @@
|
|||
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
|
||||
#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
|
||||
|
||||
/* pad multiplexing support */
|
||||
/* muxing registers */
|
||||
#define PAD_MUX_CONFIG_REG 0x00
|
||||
#define MODE_CONFIG_REG 0x04
|
||||
|
||||
/* modes */
|
||||
#define NAND_MODE (1 << 0)
|
||||
#define NOR_MODE (1 << 1)
|
||||
#define PHOTO_FRAME_MODE (1 << 2)
|
||||
#define LEND_IP_PHONE_MODE (1 << 3)
|
||||
#define HEND_IP_PHONE_MODE (1 << 4)
|
||||
#define LEND_WIFI_PHONE_MODE (1 << 5)
|
||||
#define HEND_WIFI_PHONE_MODE (1 << 6)
|
||||
#define ATA_PABX_WI2S_MODE (1 << 7)
|
||||
#define ATA_PABX_I2S_MODE (1 << 8)
|
||||
#define CAML_LCDW_MODE (1 << 9)
|
||||
#define CAMU_LCD_MODE (1 << 10)
|
||||
#define CAMU_WLCD_MODE (1 << 11)
|
||||
#define CAML_LCD_MODE (1 << 12)
|
||||
#define ALL_MODES 0x1FFF
|
||||
|
||||
struct pmx_mode spear300_nand_mode = {
|
||||
.id = NAND_MODE,
|
||||
.name = "nand mode",
|
||||
.mask = 0x00,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_nor_mode = {
|
||||
.id = NOR_MODE,
|
||||
.name = "nor mode",
|
||||
.mask = 0x01,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_photo_frame_mode = {
|
||||
.id = PHOTO_FRAME_MODE,
|
||||
.name = "photo frame mode",
|
||||
.mask = 0x02,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_lend_ip_phone_mode = {
|
||||
.id = LEND_IP_PHONE_MODE,
|
||||
.name = "lend ip phone mode",
|
||||
.mask = 0x03,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_hend_ip_phone_mode = {
|
||||
.id = HEND_IP_PHONE_MODE,
|
||||
.name = "hend ip phone mode",
|
||||
.mask = 0x04,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_lend_wifi_phone_mode = {
|
||||
.id = LEND_WIFI_PHONE_MODE,
|
||||
.name = "lend wifi phone mode",
|
||||
.mask = 0x05,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_hend_wifi_phone_mode = {
|
||||
.id = HEND_WIFI_PHONE_MODE,
|
||||
.name = "hend wifi phone mode",
|
||||
.mask = 0x06,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_ata_pabx_wi2s_mode = {
|
||||
.id = ATA_PABX_WI2S_MODE,
|
||||
.name = "ata pabx wi2s mode",
|
||||
.mask = 0x07,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_ata_pabx_i2s_mode = {
|
||||
.id = ATA_PABX_I2S_MODE,
|
||||
.name = "ata pabx i2s mode",
|
||||
.mask = 0x08,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_caml_lcdw_mode = {
|
||||
.id = CAML_LCDW_MODE,
|
||||
.name = "caml lcdw mode",
|
||||
.mask = 0x0C,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_camu_lcd_mode = {
|
||||
.id = CAMU_LCD_MODE,
|
||||
.name = "camu lcd mode",
|
||||
.mask = 0x0D,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_camu_wlcd_mode = {
|
||||
.id = CAMU_WLCD_MODE,
|
||||
.name = "camu wlcd mode",
|
||||
.mask = 0x0E,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_caml_lcd_mode = {
|
||||
.id = CAML_LCD_MODE,
|
||||
.name = "caml lcd mode",
|
||||
.mask = 0x0F,
|
||||
};
|
||||
|
||||
/* devices */
|
||||
static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
|
||||
{
|
||||
.ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
|
||||
ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
|
||||
.mask = PMX_FIRDA_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_fsmc_2_chips = {
|
||||
.name = "fsmc_2_chips",
|
||||
.modes = pmx_fsmc_2_chips_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
|
||||
{
|
||||
.ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
|
||||
ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
|
||||
.mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_fsmc_4_chips = {
|
||||
.name = "fsmc_4_chips",
|
||||
.modes = pmx_fsmc_4_chips_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_keyboard_modes[] = {
|
||||
{
|
||||
.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
|
||||
LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
|
||||
CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
|
||||
CAML_LCD_MODE,
|
||||
.mask = 0x0,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_keyboard = {
|
||||
.name = "keyboard",
|
||||
.modes = pmx_keyboard_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_keyboard_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_clcd_modes[] = {
|
||||
{
|
||||
.ids = PHOTO_FRAME_MODE,
|
||||
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
|
||||
}, {
|
||||
.ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
|
||||
CAMU_LCD_MODE | CAML_LCD_MODE,
|
||||
.mask = PMX_TIMER_3_4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_clcd = {
|
||||
.name = "clcd",
|
||||
.modes = pmx_clcd_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_clcd_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
|
||||
{
|
||||
.ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
}, {
|
||||
.ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
|
||||
.mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
|
||||
}, {
|
||||
.ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
|
||||
.mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
|
||||
}, {
|
||||
.ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
|
||||
.mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
|
||||
}, {
|
||||
.ids = ATA_PABX_WI2S_MODE,
|
||||
.mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
|
||||
| PMX_UART0_MODEM_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_telecom_gpio = {
|
||||
.name = "telecom_gpio",
|
||||
.modes = pmx_telecom_gpio_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
|
||||
{
|
||||
.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
|
||||
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
|
||||
| HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
|
||||
| ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
|
||||
| CAMU_WLCD_MODE | CAML_LCD_MODE,
|
||||
.mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_telecom_tdm = {
|
||||
.name = "telecom_tdm",
|
||||
.modes = pmx_telecom_tdm_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
|
||||
{
|
||||
.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
|
||||
LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
|
||||
| ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
|
||||
CAML_LCDW_MODE | CAML_LCD_MODE,
|
||||
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
|
||||
.name = "telecom_spi_cs_i2c_clk",
|
||||
.modes = pmx_telecom_spi_cs_i2c_clk_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
|
||||
{
|
||||
.ids = CAML_LCDW_MODE | CAML_LCD_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
}, {
|
||||
.ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
|
||||
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_telecom_camera = {
|
||||
.name = "telecom_camera",
|
||||
.modes = pmx_telecom_camera_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
|
||||
{
|
||||
.ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
|
||||
| CAMU_WLCD_MODE | CAML_LCD_MODE,
|
||||
.mask = PMX_TIMER_1_2_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_telecom_dac = {
|
||||
.name = "telecom_dac",
|
||||
.modes = pmx_telecom_dac_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
|
||||
{
|
||||
.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
|
||||
| LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
|
||||
ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
|
||||
| CAMU_WLCD_MODE | CAML_LCD_MODE,
|
||||
.mask = PMX_UART0_MODEM_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_telecom_i2s = {
|
||||
.name = "telecom_i2s",
|
||||
.modes = pmx_telecom_i2s_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
|
||||
{
|
||||
.ids = NAND_MODE | NOR_MODE,
|
||||
.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
|
||||
PMX_TIMER_3_4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_telecom_boot_pins = {
|
||||
.name = "telecom_boot_pins",
|
||||
.modes = pmx_telecom_boot_pins_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
|
||||
{
|
||||
.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
|
||||
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
|
||||
HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
|
||||
CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
|
||||
ATA_PABX_I2S_MODE,
|
||||
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
|
||||
PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
|
||||
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
|
||||
.name = "telecom_sdhci_4bit",
|
||||
.modes = pmx_telecom_sdhci_4bit_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
|
||||
{
|
||||
.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
|
||||
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
|
||||
HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
|
||||
CAMU_WLCD_MODE | CAML_LCD_MODE,
|
||||
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
|
||||
PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
|
||||
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
|
||||
.name = "telecom_sdhci_8bit",
|
||||
.modes = pmx_telecom_sdhci_8bit_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_gpio1_modes[] = {
|
||||
{
|
||||
.ids = PHOTO_FRAME_MODE,
|
||||
.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
|
||||
PMX_TIMER_3_4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_gpio1 = {
|
||||
.name = "arm gpio1",
|
||||
.modes = pmx_gpio1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_gpio1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
/* pmx driver structure */
|
||||
static struct pmx_driver pmx_driver = {
|
||||
.mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
|
||||
.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
|
||||
};
|
||||
|
||||
/* spear3xx shared irq */
|
||||
static struct shirq_dev_config shirq_ras1_config[] = {
|
||||
{
|
||||
|
|
@ -464,22 +113,6 @@ static struct spear_shirq shirq_ras1 = {
|
|||
},
|
||||
};
|
||||
|
||||
/* padmux devices to enable */
|
||||
static struct pmx_dev *spear300_evb_pmx_devs[] = {
|
||||
/* spear3xx specific devices */
|
||||
&spear3xx_pmx_i2c,
|
||||
&spear3xx_pmx_ssp_cs,
|
||||
&spear3xx_pmx_ssp,
|
||||
&spear3xx_pmx_mii,
|
||||
&spear3xx_pmx_uart0,
|
||||
|
||||
/* spear300 specific devices */
|
||||
&spear300_pmx_fsmc_2_chips,
|
||||
&spear300_pmx_clcd,
|
||||
&spear300_pmx_telecom_sdhci_4bit,
|
||||
&spear300_pmx_gpio1,
|
||||
};
|
||||
|
||||
/* DMAC platform data's slave info */
|
||||
struct pl08x_channel_data spear300_dma_info[] = {
|
||||
{
|
||||
|
|
@ -678,7 +311,7 @@ static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
|
|||
|
||||
static void __init spear300_dt_init(void)
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
int ret;
|
||||
|
||||
pl080_plat_data.slave_channels = spear300_dma_info;
|
||||
pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
|
||||
|
|
@ -693,26 +326,6 @@ static void __init spear300_dt_init(void)
|
|||
if (ret)
|
||||
pr_err("Error registering Shared IRQ\n");
|
||||
}
|
||||
|
||||
if (of_machine_is_compatible("st,spear300-evb")) {
|
||||
/* pmx initialization */
|
||||
pmx_driver.mode = &spear300_photo_frame_mode;
|
||||
pmx_driver.devs = spear300_evb_pmx_devs;
|
||||
pmx_driver.devs_count = ARRAY_SIZE(spear300_evb_pmx_devs);
|
||||
|
||||
pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
|
||||
if (pmx_driver.base) {
|
||||
ret = pmx_register(&pmx_driver);
|
||||
if (ret)
|
||||
pr_err("padmux: registration failed. err no: %d\n",
|
||||
ret);
|
||||
/* Free Mapping, device selection already done */
|
||||
iounmap(pmx_driver.base);
|
||||
}
|
||||
|
||||
if (ret)
|
||||
pr_err("Initialization Failed");
|
||||
}
|
||||
}
|
||||
|
||||
static const char * const spear300_dt_board_compat[] = {
|
||||
|
|
|
|||
|
|
@ -82,128 +82,6 @@
|
|||
#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
|
||||
|
||||
|
||||
/* pad multiplexing support */
|
||||
/* muxing registers */
|
||||
#define PAD_MUX_CONFIG_REG 0x08
|
||||
|
||||
/* devices */
|
||||
static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_TIMER_3_4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
|
||||
.name = "emi_cs_0_1_4_5",
|
||||
.modes = pmx_emi_cs_0_1_4_5_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_TIMER_1_2_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear310_pmx_emi_cs_2_3 = {
|
||||
.name = "emi_cs_2_3",
|
||||
.modes = pmx_emi_cs_2_3_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_uart1_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_FIRDA_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear310_pmx_uart1 = {
|
||||
.name = "uart1",
|
||||
.modes = pmx_uart1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_uart1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_uart2_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_TIMER_1_2_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear310_pmx_uart2 = {
|
||||
.name = "uart2",
|
||||
.modes = pmx_uart2_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_uart2_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_UART0_MODEM_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear310_pmx_uart3_4_5 = {
|
||||
.name = "uart3_4_5",
|
||||
.modes = pmx_uart3_4_5_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_fsmc_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_SSP_CS_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear310_pmx_fsmc = {
|
||||
.name = "fsmc",
|
||||
.modes = pmx_fsmc_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear310_pmx_rs485_0_1 = {
|
||||
.name = "rs485_0_1",
|
||||
.modes = pmx_rs485_0_1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_tdm0_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear310_pmx_tdm0 = {
|
||||
.name = "tdm0",
|
||||
.modes = pmx_tdm0_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_tdm0_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
/* pmx driver structure */
|
||||
static struct pmx_driver pmx_driver = {
|
||||
.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
|
||||
};
|
||||
|
||||
/* spear3xx shared irq */
|
||||
static struct shirq_dev_config shirq_ras1_config[] = {
|
||||
{
|
||||
|
|
@ -320,30 +198,6 @@ static struct spear_shirq shirq_intrcomm_ras = {
|
|||
},
|
||||
};
|
||||
|
||||
/* padmux devices to enable */
|
||||
static struct pmx_dev *spear310_evb_pmx_devs[] = {
|
||||
/* spear3xx specific devices */
|
||||
&spear3xx_pmx_i2c,
|
||||
&spear3xx_pmx_ssp,
|
||||
&spear3xx_pmx_gpio_pin0,
|
||||
&spear3xx_pmx_gpio_pin1,
|
||||
&spear3xx_pmx_gpio_pin2,
|
||||
&spear3xx_pmx_gpio_pin3,
|
||||
&spear3xx_pmx_gpio_pin4,
|
||||
&spear3xx_pmx_gpio_pin5,
|
||||
&spear3xx_pmx_uart0,
|
||||
|
||||
/* spear310 specific devices */
|
||||
&spear310_pmx_emi_cs_0_1_4_5,
|
||||
&spear310_pmx_emi_cs_2_3,
|
||||
&spear310_pmx_uart1,
|
||||
&spear310_pmx_uart2,
|
||||
&spear310_pmx_uart3_4_5,
|
||||
&spear310_pmx_fsmc,
|
||||
&spear310_pmx_rs485_0_1,
|
||||
&spear310_pmx_tdm0,
|
||||
};
|
||||
|
||||
/* DMAC platform data's slave info */
|
||||
struct pl08x_channel_data spear310_dma_info[] = {
|
||||
{
|
||||
|
|
@ -578,7 +432,7 @@ static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
|
|||
static void __init spear310_dt_init(void)
|
||||
{
|
||||
void __iomem *base;
|
||||
int ret = 0;
|
||||
int ret;
|
||||
|
||||
pl080_plat_data.slave_channels = spear310_dma_info;
|
||||
pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
|
||||
|
|
@ -613,19 +467,6 @@ static void __init spear310_dt_init(void)
|
|||
if (ret)
|
||||
pr_err("Error registering Shared IRQ 4\n");
|
||||
}
|
||||
|
||||
if (of_machine_is_compatible("st,spear310-evb")) {
|
||||
/* pmx initialization */
|
||||
pmx_driver.base = base;
|
||||
pmx_driver.mode = NULL;
|
||||
pmx_driver.devs = spear310_evb_pmx_devs;
|
||||
pmx_driver.devs_count = ARRAY_SIZE(spear310_evb_pmx_devs);
|
||||
|
||||
ret = pmx_register(&pmx_driver);
|
||||
if (ret)
|
||||
pr_err("padmux: registration failed. err no: %d\n",
|
||||
ret);
|
||||
}
|
||||
}
|
||||
|
||||
static const char * const spear310_dt_board_compat[] = {
|
||||
|
|
|
|||
|
|
@ -83,373 +83,6 @@
|
|||
#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
|
||||
#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
|
||||
|
||||
/* pad multiplexing support */
|
||||
/* muxing registers */
|
||||
#define PAD_MUX_CONFIG_REG 0x0C
|
||||
#define MODE_CONFIG_REG 0x10
|
||||
|
||||
/* modes */
|
||||
#define AUTO_NET_SMII_MODE (1 << 0)
|
||||
#define AUTO_NET_MII_MODE (1 << 1)
|
||||
#define AUTO_EXP_MODE (1 << 2)
|
||||
#define SMALL_PRINTERS_MODE (1 << 3)
|
||||
#define ALL_MODES 0xF
|
||||
|
||||
struct pmx_mode spear320_auto_net_smii_mode = {
|
||||
.id = AUTO_NET_SMII_MODE,
|
||||
.name = "Automation Networking SMII Mode",
|
||||
.mask = 0x00,
|
||||
};
|
||||
|
||||
struct pmx_mode spear320_auto_net_mii_mode = {
|
||||
.id = AUTO_NET_MII_MODE,
|
||||
.name = "Automation Networking MII Mode",
|
||||
.mask = 0x01,
|
||||
};
|
||||
|
||||
struct pmx_mode spear320_auto_exp_mode = {
|
||||
.id = AUTO_EXP_MODE,
|
||||
.name = "Automation Expanded Mode",
|
||||
.mask = 0x02,
|
||||
};
|
||||
|
||||
struct pmx_mode spear320_small_printers_mode = {
|
||||
.id = SMALL_PRINTERS_MODE,
|
||||
.name = "Small Printers Mode",
|
||||
.mask = 0x03,
|
||||
};
|
||||
|
||||
/* devices */
|
||||
static struct pmx_dev_mode pmx_clcd_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE,
|
||||
.mask = 0x0,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_clcd = {
|
||||
.name = "clcd",
|
||||
.modes = pmx_clcd_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_clcd_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_emi_modes[] = {
|
||||
{
|
||||
.ids = AUTO_EXP_MODE,
|
||||
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_emi = {
|
||||
.name = "emi",
|
||||
.modes = pmx_emi_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_emi_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_fsmc_modes[] = {
|
||||
{
|
||||
.ids = ALL_MODES,
|
||||
.mask = 0x0,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_fsmc = {
|
||||
.name = "fsmc",
|
||||
.modes = pmx_fsmc_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_spp_modes[] = {
|
||||
{
|
||||
.ids = SMALL_PRINTERS_MODE,
|
||||
.mask = 0x0,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_spp = {
|
||||
.name = "spp",
|
||||
.modes = pmx_spp_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_spp_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_sdhci_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
|
||||
SMALL_PRINTERS_MODE,
|
||||
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_sdhci = {
|
||||
.name = "sdhci",
|
||||
.modes = pmx_sdhci_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_sdhci_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_i2s_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
|
||||
.mask = PMX_UART0_MODEM_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_i2s = {
|
||||
.name = "i2s",
|
||||
.modes = pmx_i2s_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_i2s_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_uart1_modes[] = {
|
||||
{
|
||||
.ids = ALL_MODES,
|
||||
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_uart1 = {
|
||||
.name = "uart1",
|
||||
.modes = pmx_uart1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_uart1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
|
||||
{
|
||||
.ids = AUTO_EXP_MODE,
|
||||
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
|
||||
PMX_SSP_CS_MASK,
|
||||
}, {
|
||||
.ids = SMALL_PRINTERS_MODE,
|
||||
.mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
|
||||
PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_uart1_modem = {
|
||||
.name = "uart1_modem",
|
||||
.modes = pmx_uart1_modem_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_uart2_modes[] = {
|
||||
{
|
||||
.ids = ALL_MODES,
|
||||
.mask = PMX_FIRDA_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_uart2 = {
|
||||
.name = "uart2",
|
||||
.modes = pmx_uart2_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_uart2_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_touchscreen_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE,
|
||||
.mask = PMX_SSP_CS_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_touchscreen = {
|
||||
.name = "touchscreen",
|
||||
.modes = pmx_touchscreen_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_can_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
|
||||
.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
|
||||
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_can = {
|
||||
.name = "can",
|
||||
.modes = pmx_can_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_can_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
|
||||
.mask = PMX_SSP_CS_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_sdhci_led = {
|
||||
.name = "sdhci_led",
|
||||
.modes = pmx_sdhci_led_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_pwm0_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
|
||||
.mask = PMX_UART0_MODEM_MASK,
|
||||
}, {
|
||||
.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_pwm0 = {
|
||||
.name = "pwm0",
|
||||
.modes = pmx_pwm0_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_pwm0_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_pwm1_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
|
||||
.mask = PMX_UART0_MODEM_MASK,
|
||||
}, {
|
||||
.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_pwm1 = {
|
||||
.name = "pwm1",
|
||||
.modes = pmx_pwm1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_pwm1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_pwm2_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
|
||||
.mask = PMX_SSP_CS_MASK,
|
||||
}, {
|
||||
.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_pwm2 = {
|
||||
.name = "pwm2",
|
||||
.modes = pmx_pwm2_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_pwm2_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_pwm3_modes[] = {
|
||||
{
|
||||
.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_pwm3 = {
|
||||
.name = "pwm3",
|
||||
.modes = pmx_pwm3_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_pwm3_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_ssp1_modes[] = {
|
||||
{
|
||||
.ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_ssp1 = {
|
||||
.name = "ssp1",
|
||||
.modes = pmx_ssp1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_ssp1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_ssp2_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_ssp2 = {
|
||||
.name = "ssp2",
|
||||
.modes = pmx_ssp2_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_ssp2_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_mii1_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_MII_MODE,
|
||||
.mask = 0x0,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_mii1 = {
|
||||
.name = "mii1",
|
||||
.modes = pmx_mii1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_mii1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_smii0_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_smii0 = {
|
||||
.name = "smii0",
|
||||
.modes = pmx_smii0_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_smii0_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_smii1_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_smii1 = {
|
||||
.name = "smii1",
|
||||
.modes = pmx_smii1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_smii1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_i2c1_modes[] = {
|
||||
{
|
||||
.ids = AUTO_EXP_MODE,
|
||||
.mask = 0x0,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_i2c1 = {
|
||||
.name = "i2c1",
|
||||
.modes = pmx_i2c1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_i2c1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
/* pmx driver structure */
|
||||
static struct pmx_driver pmx_driver = {
|
||||
.mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
|
||||
.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
|
||||
};
|
||||
|
||||
/* spear3xx shared irq */
|
||||
static struct shirq_dev_config shirq_ras1_config[] = {
|
||||
{
|
||||
|
|
@ -574,27 +207,6 @@ static struct spear_shirq shirq_intrcomm_ras = {
|
|||
},
|
||||
};
|
||||
|
||||
/* padmux devices to enable */
|
||||
static struct pmx_dev *spear320_evb_pmx_devs[] = {
|
||||
/* spear3xx specific devices */
|
||||
&spear3xx_pmx_i2c,
|
||||
&spear3xx_pmx_ssp,
|
||||
&spear3xx_pmx_mii,
|
||||
&spear3xx_pmx_uart0,
|
||||
|
||||
/* spear320 specific devices */
|
||||
&spear320_pmx_fsmc,
|
||||
&spear320_pmx_sdhci,
|
||||
&spear320_pmx_i2s,
|
||||
&spear320_pmx_uart1,
|
||||
&spear320_pmx_uart2,
|
||||
&spear320_pmx_can,
|
||||
&spear320_pmx_pwm0,
|
||||
&spear320_pmx_pwm1,
|
||||
&spear320_pmx_pwm2,
|
||||
&spear320_pmx_mii1,
|
||||
};
|
||||
|
||||
/* DMAC platform data's slave info */
|
||||
struct pl08x_channel_data spear320_dma_info[] = {
|
||||
{
|
||||
|
|
@ -832,7 +444,7 @@ static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
|
|||
static void __init spear320_dt_init(void)
|
||||
{
|
||||
void __iomem *base;
|
||||
int ret = 0;
|
||||
int ret;
|
||||
|
||||
pl080_plat_data.slave_channels = spear320_dma_info;
|
||||
pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
|
||||
|
|
@ -861,19 +473,6 @@ static void __init spear320_dt_init(void)
|
|||
if (ret)
|
||||
pr_err("Error registering Shared IRQ 4\n");
|
||||
}
|
||||
|
||||
if (of_machine_is_compatible("st,spear320-evb")) {
|
||||
/* pmx initialization */
|
||||
pmx_driver.base = base;
|
||||
pmx_driver.mode = &spear320_auto_net_mii_mode;
|
||||
pmx_driver.devs = spear320_evb_pmx_devs;
|
||||
pmx_driver.devs_count = ARRAY_SIZE(spear320_evb_pmx_devs);
|
||||
|
||||
ret = pmx_register(&pmx_driver);
|
||||
if (ret)
|
||||
pr_err("padmux: registration failed. err no: %d\n",
|
||||
ret);
|
||||
}
|
||||
}
|
||||
|
||||
static const char * const spear320_dt_board_compat[] = {
|
||||
|
|
|
|||
|
|
@ -23,431 +23,6 @@
|
|||
#include <mach/generic.h>
|
||||
#include <mach/spear.h>
|
||||
|
||||
/* pad multiplexing support */
|
||||
/* devices */
|
||||
static struct pmx_dev_mode pmx_firda_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_FIRDA_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_firda = {
|
||||
.name = "firda",
|
||||
.modes = pmx_firda_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_firda_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_i2c_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_I2C_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_i2c = {
|
||||
.name = "i2c",
|
||||
.modes = pmx_i2c_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_i2c_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_SSP_CS_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_ssp_cs = {
|
||||
.name = "ssp_chip_selects",
|
||||
.modes = pmx_ssp_cs_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_ssp_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_SSP_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_ssp = {
|
||||
.name = "ssp",
|
||||
.modes = pmx_ssp_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_ssp_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_mii_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_mii = {
|
||||
.name = "mii",
|
||||
.modes = pmx_mii_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_mii_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_GPIO_PIN0_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_gpio_pin0 = {
|
||||
.name = "gpio_pin0",
|
||||
.modes = pmx_gpio_pin0_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_GPIO_PIN1_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_gpio_pin1 = {
|
||||
.name = "gpio_pin1",
|
||||
.modes = pmx_gpio_pin1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_GPIO_PIN2_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_gpio_pin2 = {
|
||||
.name = "gpio_pin2",
|
||||
.modes = pmx_gpio_pin2_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_GPIO_PIN3_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_gpio_pin3 = {
|
||||
.name = "gpio_pin3",
|
||||
.modes = pmx_gpio_pin3_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_GPIO_PIN4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_gpio_pin4 = {
|
||||
.name = "gpio_pin4",
|
||||
.modes = pmx_gpio_pin4_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_GPIO_PIN5_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_gpio_pin5 = {
|
||||
.name = "gpio_pin5",
|
||||
.modes = pmx_gpio_pin5_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_UART0_MODEM_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_uart0_modem = {
|
||||
.name = "uart0_modem",
|
||||
.modes = pmx_uart0_modem_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_uart0_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_UART0_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_uart0 = {
|
||||
.name = "uart0",
|
||||
.modes = pmx_uart0_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_uart0_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_TIMER_3_4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_timer_3_4 = {
|
||||
.name = "timer_3_4",
|
||||
.modes = pmx_timer_3_4_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_TIMER_1_2_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_timer_1_2 = {
|
||||
.name = "timer_1_2",
|
||||
.modes = pmx_timer_1_2_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
|
||||
/* plgpios devices */
|
||||
static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_FIRDA_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
|
||||
.name = "plgpio 0 and 1",
|
||||
.modes = pmx_plgpio_0_1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_UART0_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
|
||||
.name = "plgpio 2 and 3",
|
||||
.modes = pmx_plgpio_2_3_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_I2C_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
|
||||
.name = "plgpio 4 and 5",
|
||||
.modes = pmx_plgpio_4_5_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_SSP_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
|
||||
.name = "plgpio 6 to 9",
|
||||
.modes = pmx_plgpio_6_9_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
|
||||
.name = "plgpio 10 to 27",
|
||||
.modes = pmx_plgpio_10_27_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_GPIO_PIN0_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_28 = {
|
||||
.name = "plgpio 28",
|
||||
.modes = pmx_plgpio_28_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_GPIO_PIN1_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_29 = {
|
||||
.name = "plgpio 29",
|
||||
.modes = pmx_plgpio_29_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_GPIO_PIN2_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_30 = {
|
||||
.name = "plgpio 30",
|
||||
.modes = pmx_plgpio_30_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_GPIO_PIN3_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_31 = {
|
||||
.name = "plgpio 31",
|
||||
.modes = pmx_plgpio_31_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_GPIO_PIN4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_32 = {
|
||||
.name = "plgpio 32",
|
||||
.modes = pmx_plgpio_32_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_GPIO_PIN5_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_33 = {
|
||||
.name = "plgpio 33",
|
||||
.modes = pmx_plgpio_33_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_SSP_CS_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
|
||||
.name = "plgpio 34 to 36",
|
||||
.modes = pmx_plgpio_34_36_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_UART0_MODEM_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
|
||||
.name = "plgpio 37 to 42",
|
||||
.modes = pmx_plgpio_37_42_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_TIMER_1_2_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
|
||||
.name = "plgpio 43, 44, 47 and 48",
|
||||
.modes = pmx_plgpio_43_44_47_48_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_TIMER_3_4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
|
||||
.name = "plgpio 45, 46, 49 and 50",
|
||||
.modes = pmx_plgpio_45_46_49_50_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
|
||||
|
||||
/* ssp device registration */
|
||||
struct pl022_ssp_controller pl022_plat_data = {
|
||||
.bus_id = 0,
|
||||
|
|
|
|||
|
|
@ -5,7 +5,6 @@ obj-y += io.o
|
|||
obj-y += irq.o
|
||||
obj-y += clock.o
|
||||
obj-y += timer.o
|
||||
obj-y += pinmux.o
|
||||
obj-y += fuse.o
|
||||
obj-y += pmc.o
|
||||
obj-y += flowctrl.o
|
||||
|
|
@ -14,8 +13,6 @@ obj-$(CONFIG_CPU_IDLE) += sleep.o
|
|||
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
|
||||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
|
|
|
|||
|
|
@ -46,15 +46,7 @@
|
|||
#include "clock.h"
|
||||
#include "devices.h"
|
||||
|
||||
void harmony_pinmux_init(void);
|
||||
void paz00_pinmux_init(void);
|
||||
void seaboard_pinmux_init(void);
|
||||
void trimslice_pinmux_init(void);
|
||||
void ventana_pinmux_init(void);
|
||||
|
||||
struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-gpio", TEGRA_GPIO_BASE, "tegra-gpio", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
|
||||
|
|
@ -94,33 +86,10 @@ static struct of_device_id tegra_dt_match_table[] __initdata = {
|
|||
{}
|
||||
};
|
||||
|
||||
static struct {
|
||||
char *machine;
|
||||
void (*init)(void);
|
||||
} pinmux_configs[] = {
|
||||
{ "compulab,trimslice", trimslice_pinmux_init },
|
||||
{ "nvidia,harmony", harmony_pinmux_init },
|
||||
{ "compal,paz00", paz00_pinmux_init },
|
||||
{ "nvidia,seaboard", seaboard_pinmux_init },
|
||||
{ "nvidia,ventana", ventana_pinmux_init },
|
||||
};
|
||||
|
||||
static void __init tegra_dt_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
tegra_clk_init_from_table(tegra_dt_clk_init_table);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
|
||||
if (of_machine_is_compatible(pinmux_configs[i].machine)) {
|
||||
pinmux_configs[i].init();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
WARN(i == ARRAY_SIZE(pinmux_configs),
|
||||
"Unknown platform! Pinmuxing not initialized\n");
|
||||
|
||||
/*
|
||||
* Finished with the static registrations now; fill in the missing
|
||||
* devices
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
* arch/arm/mach-tegra/board-harmony-pinmux.c
|
||||
*
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
|
|
@ -15,153 +16,138 @@
|
|||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <mach/pinmux.h>
|
||||
#include <mach/pinmux-tegra20.h>
|
||||
|
||||
#include "gpio-names.h"
|
||||
#include "board-harmony.h"
|
||||
#include "board-pinmux.h"
|
||||
|
||||
static struct tegra_pingroup_config harmony_pinmux[] = {
|
||||
{TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTA, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPU, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
};
|
||||
|
||||
static struct tegra_gpio_table gpio_table[] = {
|
||||
{ .gpio = TEGRA_GPIO_SD2_CD, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_SD2_WP, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_SD2_POWER, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_SD4_CD, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_SD4_WP, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_SD4_POWER, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_HP_DET, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_INT_MIC_EN, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_EXT_MIC_EN, .enable = true },
|
||||
static struct pinctrl_map harmony_map[] = {
|
||||
TEGRA_MAP_MUXCONF("ata", "ide", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atc", "nand", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("ate", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
|
||||
TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
|
||||
TEGRA_MAP_MUXCONF("dta", "sdio2", up, driven),
|
||||
TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtd", "sdio2", up, driven),
|
||||
TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtf", "i2c3", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpu", "gmi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
|
||||
TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
|
||||
TEGRA_MAP_MUXCONF("irrx", "uarta", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("irtx", "uarta", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("owc", "rsvd2", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
|
||||
TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven),
|
||||
TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven),
|
||||
TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxd", "spdif", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spia", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spib", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spic", "gmi", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uac", "rsvd2", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("uad", "irda", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate),
|
||||
TEGRA_MAP_CONF("ck32", none, na),
|
||||
TEGRA_MAP_CONF("ddrc", none, na),
|
||||
TEGRA_MAP_CONF("pmca", none, na),
|
||||
TEGRA_MAP_CONF("pmcb", none, na),
|
||||
TEGRA_MAP_CONF("pmcc", none, na),
|
||||
TEGRA_MAP_CONF("pmcd", none, na),
|
||||
TEGRA_MAP_CONF("pmce", none, na),
|
||||
TEGRA_MAP_CONF("xm2c", none, na),
|
||||
TEGRA_MAP_CONF("xm2d", none, na),
|
||||
TEGRA_MAP_CONF("ls", up, na),
|
||||
TEGRA_MAP_CONF("lc", up, na),
|
||||
TEGRA_MAP_CONF("ld17_0", down, na),
|
||||
TEGRA_MAP_CONF("ld19_18", down, na),
|
||||
TEGRA_MAP_CONF("ld21_20", down, na),
|
||||
TEGRA_MAP_CONF("ld23_22", down, na),
|
||||
};
|
||||
|
||||
static struct tegra_board_pinmux_conf conf = {
|
||||
.pgs = harmony_pinmux,
|
||||
.pg_count = ARRAY_SIZE(harmony_pinmux),
|
||||
.gpios = gpio_table,
|
||||
.gpio_count = ARRAY_SIZE(gpio_table),
|
||||
.maps = harmony_map,
|
||||
.map_count = ARRAY_SIZE(harmony_map),
|
||||
};
|
||||
|
||||
void harmony_pinmux_init(void)
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
* arch/arm/mach-tegra/board-paz00-pinmux.c
|
||||
*
|
||||
* Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de>
|
||||
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
|
|
@ -15,150 +16,138 @@
|
|||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <mach/pinmux.h>
|
||||
#include <mach/pinmux-tegra20.h>
|
||||
|
||||
#include "gpio-names.h"
|
||||
#include "board-paz00.h"
|
||||
#include "board-pinmux.h"
|
||||
|
||||
static struct tegra_pingroup_config paz00_pinmux[] = {
|
||||
{TEGRA_PINGROUP_ATA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CSUS, TEGRA_MUX_PLLC_OUT1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DAP2, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTA, TEGRA_MUX_RSVD1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTD, TEGRA_MUX_RSVD1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCB, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_OWC, TEGRA_MUX_OWR, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SDC, TEGRA_MUX_TWC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPID, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIE, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIF, TEGRA_MUX_RSVD4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UAD, TEGRA_MUX_SPDIF, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
};
|
||||
|
||||
static struct tegra_gpio_table gpio_table[] = {
|
||||
{ .gpio = TEGRA_GPIO_SD1_CD, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_SD1_WP, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_SD1_POWER, .enable = true },
|
||||
{ .gpio = TEGRA_ULPI_RST, .enable = true },
|
||||
{ .gpio = TEGRA_WIFI_PWRN, .enable = true },
|
||||
{ .gpio = TEGRA_WIFI_RST, .enable = true },
|
||||
{ .gpio = TEGRA_WIFI_LED, .enable = true },
|
||||
static struct pinctrl_map paz00_map[] = {
|
||||
TEGRA_MAP_MUXCONF("ata", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atc", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("ate", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
|
||||
TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, driven),
|
||||
TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("csus", "pllc_out1", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("dap2", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
|
||||
TEGRA_MAP_MUXCONF("dta", "rsvd1", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtd", "rsvd1", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmc", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
|
||||
TEGRA_MAP_MUXCONF("hdint", "hdmi", na, driven),
|
||||
TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
|
||||
TEGRA_MAP_MUXCONF("irrx", "uarta", up, driven),
|
||||
TEGRA_MAP_MUXCONF("irtx", "uarta", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcb", "sdio2", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcd", "sdio2", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ldc", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp0", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lhp1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lhp2", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lm0", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpp", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpw0", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpw2", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lvp1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("owc", "owr", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
|
||||
TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("sdc", "twc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("slxa", "pcie", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxc", "spi4", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxd", "spi4", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spia", "gmi", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spib", "gmi", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spic", "gmi", up, driven),
|
||||
TEGRA_MAP_MUXCONF("spid", "gmi", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spie", "gmi", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("spif", "rsvd4", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, driven),
|
||||
TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven),
|
||||
TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven),
|
||||
TEGRA_MAP_MUXCONF("uac", "rsvd4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("uad", "spdif", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven),
|
||||
TEGRA_MAP_CONF("ck32", none, na),
|
||||
TEGRA_MAP_CONF("ddrc", none, na),
|
||||
TEGRA_MAP_CONF("pmca", none, na),
|
||||
TEGRA_MAP_CONF("pmcb", none, na),
|
||||
TEGRA_MAP_CONF("pmcc", none, na),
|
||||
TEGRA_MAP_CONF("pmcd", none, na),
|
||||
TEGRA_MAP_CONF("pmce", none, na),
|
||||
TEGRA_MAP_CONF("xm2c", none, na),
|
||||
TEGRA_MAP_CONF("xm2d", none, na),
|
||||
TEGRA_MAP_CONF("ls", up, na),
|
||||
TEGRA_MAP_CONF("lc", up, na),
|
||||
TEGRA_MAP_CONF("ld17_0", down, na),
|
||||
TEGRA_MAP_CONF("ld19_18", down, na),
|
||||
TEGRA_MAP_CONF("ld21_20", down, na),
|
||||
TEGRA_MAP_CONF("ld23_22", down, na),
|
||||
};
|
||||
|
||||
static struct tegra_board_pinmux_conf conf = {
|
||||
.pgs = paz00_pinmux,
|
||||
.pg_count = ARRAY_SIZE(paz00_pinmux),
|
||||
.gpios = gpio_table,
|
||||
.gpio_count = ARRAY_SIZE(gpio_table),
|
||||
.maps = paz00_map,
|
||||
.map_count = ARRAY_SIZE(paz00_map),
|
||||
};
|
||||
|
||||
void paz00_pinmux_init(void)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
|
|
@ -15,75 +15,59 @@
|
|||
#include <linux/device.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#include <mach/gpio-tegra.h>
|
||||
#include <mach/pinmux.h>
|
||||
|
||||
#include "board-pinmux.h"
|
||||
#include "devices.h"
|
||||
|
||||
struct tegra_board_pinmux_conf *confs[2];
|
||||
unsigned long tegra_pincfg_pullnone_driven[2] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
|
||||
};
|
||||
|
||||
static void tegra_board_pinmux_setup_gpios(void)
|
||||
{
|
||||
int i;
|
||||
unsigned long tegra_pincfg_pullnone_tristate[2] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
|
||||
};
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(confs); i++) {
|
||||
if (!confs[i])
|
||||
continue;
|
||||
unsigned long tegra_pincfg_pullnone_na[1] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
|
||||
};
|
||||
|
||||
tegra_gpio_config(confs[i]->gpios, confs[i]->gpio_count);
|
||||
}
|
||||
}
|
||||
unsigned long tegra_pincfg_pullup_driven[2] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
|
||||
};
|
||||
|
||||
static void tegra_board_pinmux_setup_pinmux(void)
|
||||
{
|
||||
int i;
|
||||
unsigned long tegra_pincfg_pullup_tristate[2] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
|
||||
};
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(confs); i++) {
|
||||
if (!confs[i])
|
||||
continue;
|
||||
unsigned long tegra_pincfg_pullup_na[1] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
|
||||
};
|
||||
|
||||
tegra_pinmux_config_table(confs[i]->pgs, confs[i]->pg_count);
|
||||
unsigned long tegra_pincfg_pulldown_driven[2] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
|
||||
};
|
||||
|
||||
if (confs[i]->drives)
|
||||
tegra_drive_pinmux_config_table(confs[i]->drives,
|
||||
confs[i]->drive_count);
|
||||
}
|
||||
}
|
||||
unsigned long tegra_pincfg_pulldown_tristate[2] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
|
||||
};
|
||||
|
||||
static int tegra_board_pinmux_bus_notify(struct notifier_block *nb,
|
||||
unsigned long event, void *vdev)
|
||||
{
|
||||
static bool had_gpio;
|
||||
static bool had_pinmux;
|
||||
unsigned long tegra_pincfg_pulldown_na[1] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
|
||||
};
|
||||
|
||||
struct device *dev = vdev;
|
||||
const char *devname;
|
||||
unsigned long tegra_pincfg_pullna_driven[1] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
|
||||
};
|
||||
|
||||
if (event != BUS_NOTIFY_BOUND_DRIVER)
|
||||
return NOTIFY_DONE;
|
||||
|
||||
devname = dev_name(dev);
|
||||
|
||||
if (!had_gpio && !strcmp(devname, GPIO_DEV)) {
|
||||
tegra_board_pinmux_setup_gpios();
|
||||
had_gpio = true;
|
||||
} else if (!had_pinmux && !strcmp(devname, PINMUX_DEV)) {
|
||||
tegra_board_pinmux_setup_pinmux();
|
||||
had_pinmux = true;
|
||||
}
|
||||
|
||||
if (had_gpio && had_pinmux)
|
||||
return NOTIFY_STOP_MASK;
|
||||
else
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static struct notifier_block nb = {
|
||||
.notifier_call = tegra_board_pinmux_bus_notify,
|
||||
unsigned long tegra_pincfg_pullna_tristate[1] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
|
||||
};
|
||||
|
||||
static struct platform_device *devices[] = {
|
||||
|
|
@ -94,11 +78,10 @@ static struct platform_device *devices[] = {
|
|||
void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
|
||||
struct tegra_board_pinmux_conf *conf_b)
|
||||
{
|
||||
confs[0] = conf_a;
|
||||
confs[1] = conf_b;
|
||||
if (conf_a)
|
||||
pinctrl_register_mappings(conf_a->maps, conf_a->map_count);
|
||||
if (conf_b)
|
||||
pinctrl_register_mappings(conf_b->maps, conf_b->map_count);
|
||||
|
||||
bus_register_notifier(&platform_bus_type, &nb);
|
||||
|
||||
if (!of_machine_is_compatible("nvidia,tegra20"))
|
||||
platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
|
|
@ -15,21 +15,37 @@
|
|||
#ifndef __MACH_TEGRA_BOARD_PINMUX_H
|
||||
#define __MACH_TEGRA_BOARD_PINMUX_H
|
||||
|
||||
#define GPIO_DEV "tegra-gpio"
|
||||
#define PINMUX_DEV "tegra-pinmux"
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
struct tegra_pingroup_config;
|
||||
struct tegra_gpio_table;
|
||||
#include <mach/pinconf-tegra.h>
|
||||
|
||||
#define PINMUX_DEV "tegra20-pinctrl"
|
||||
|
||||
#define TEGRA_MAP_MUX(_group_, _function_) \
|
||||
PIN_MAP_MUX_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, _function_)
|
||||
|
||||
#define TEGRA_MAP_CONF(_group_, _pull_, _drive_) \
|
||||
PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, tegra_pincfg_pull##_pull_##_##_drive_)
|
||||
|
||||
#define TEGRA_MAP_MUXCONF(_group_, _function_, _pull_, _drive_) \
|
||||
TEGRA_MAP_MUX(_group_, _function_), \
|
||||
TEGRA_MAP_CONF(_group_, _pull_, _drive_)
|
||||
|
||||
extern unsigned long tegra_pincfg_pullnone_driven[2];
|
||||
extern unsigned long tegra_pincfg_pullnone_tristate[2];
|
||||
extern unsigned long tegra_pincfg_pullnone_na[1];
|
||||
extern unsigned long tegra_pincfg_pullup_driven[2];
|
||||
extern unsigned long tegra_pincfg_pullup_tristate[2];
|
||||
extern unsigned long tegra_pincfg_pullup_na[1];
|
||||
extern unsigned long tegra_pincfg_pulldown_driven[2];
|
||||
extern unsigned long tegra_pincfg_pulldown_tristate[2];
|
||||
extern unsigned long tegra_pincfg_pulldown_na[1];
|
||||
extern unsigned long tegra_pincfg_pullna_driven[1];
|
||||
extern unsigned long tegra_pincfg_pullna_tristate[1];
|
||||
|
||||
struct tegra_board_pinmux_conf {
|
||||
struct tegra_pingroup_config *pgs;
|
||||
int pg_count;
|
||||
|
||||
struct tegra_drive_pingroup_config *drives;
|
||||
int drive_count;
|
||||
|
||||
struct tegra_gpio_table *gpios;
|
||||
int gpio_count;
|
||||
struct pinctrl_map *maps;
|
||||
int map_count;
|
||||
};
|
||||
|
||||
void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (C) 2010,2011 NVIDIA Corporation
|
||||
* Copyright (C) 2010-2012 NVIDIA Corporation
|
||||
* Copyright (C) 2011 Google, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
|
|
@ -14,216 +14,176 @@
|
|||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <mach/pinmux.h>
|
||||
#include <mach/pinmux-tegra20.h>
|
||||
|
||||
#include "gpio-names.h"
|
||||
#include "board-pinmux.h"
|
||||
#include "board-seaboard.h"
|
||||
#include "board-pinmux.h"
|
||||
|
||||
#define DEFAULT_DRIVE(_name) \
|
||||
{ \
|
||||
.pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
|
||||
.hsm = TEGRA_HSM_DISABLE, \
|
||||
.schmitt = TEGRA_SCHMITT_ENABLE, \
|
||||
.drive = TEGRA_DRIVE_DIV_1, \
|
||||
.pull_down = TEGRA_PULL_31, \
|
||||
.pull_up = TEGRA_PULL_31, \
|
||||
.slew_rising = TEGRA_SLEW_SLOWEST, \
|
||||
.slew_falling = TEGRA_SLEW_SLOWEST, \
|
||||
}
|
||||
|
||||
static struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
|
||||
DEFAULT_DRIVE(SDIO1),
|
||||
static unsigned long seaboard_pincfg_drive_sdio1[] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, 0),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SCHMITT, 0),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_LOW_POWER_MODE, 3),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, 31),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, 31),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, 3),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, 3),
|
||||
};
|
||||
|
||||
static struct tegra_pingroup_config common_pinmux[] = {
|
||||
{TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LCSN, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LDC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LM0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LM1, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LPW1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LSDI, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LVP0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDB, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
static struct pinctrl_map common_map[] = {
|
||||
TEGRA_MAP_MUXCONF("ata", "ide", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atc", "nand", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
|
||||
TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("crtp", "crt", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("dap2", "dap2", none, driven),
|
||||
TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap4", "dap4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("dta", "vi", down, driven),
|
||||
TEGRA_MAP_MUXCONF("dtb", "vi", down, driven),
|
||||
TEGRA_MAP_MUXCONF("dtc", "vi", down, driven),
|
||||
TEGRA_MAP_MUXCONF("dtd", "vi", down, driven),
|
||||
TEGRA_MAP_MUXCONF("dte", "vi", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmb", "gmi", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpv", "pcie", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
|
||||
TEGRA_MAP_MUXCONF("irrx", "uartb", none, driven),
|
||||
TEGRA_MAP_MUXCONF("irtx", "uartb", none, driven),
|
||||
TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("lcsn", "rsvd4", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ldc", "rsvd4", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lm0", "rsvd4", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lm1", "crt", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lpw1", "rsvd4", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lsdi", "rsvd4", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lvp0", "rsvd4", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("owc", "rsvd2", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
|
||||
TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("sdb", "sdio3", na, driven),
|
||||
TEGRA_MAP_MUXCONF("sdc", "sdio3", none, driven),
|
||||
TEGRA_MAP_MUXCONF("sdd", "sdio3", none, driven),
|
||||
TEGRA_MAP_MUXCONF("sdio1", "sdio1", up, driven),
|
||||
TEGRA_MAP_MUXCONF("slxa", "pcie", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxd", "spdif", none, driven),
|
||||
TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spib", "gmi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spid", "spi1", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spie", "spi1", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven),
|
||||
TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven),
|
||||
TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven),
|
||||
TEGRA_MAP_MUXCONF("uad", "irda", none, driven),
|
||||
TEGRA_MAP_MUXCONF("uca", "uartc", none, driven),
|
||||
TEGRA_MAP_MUXCONF("ucb", "uartc", none, driven),
|
||||
TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven),
|
||||
TEGRA_MAP_CONF("ck32", none, na),
|
||||
TEGRA_MAP_CONF("ddrc", none, na),
|
||||
TEGRA_MAP_CONF("pmca", none, na),
|
||||
TEGRA_MAP_CONF("pmcb", none, na),
|
||||
TEGRA_MAP_CONF("pmcc", none, na),
|
||||
TEGRA_MAP_CONF("pmcd", none, na),
|
||||
TEGRA_MAP_CONF("pmce", none, na),
|
||||
TEGRA_MAP_CONF("xm2c", none, na),
|
||||
TEGRA_MAP_CONF("xm2d", none, na),
|
||||
TEGRA_MAP_CONF("ls", up, na),
|
||||
TEGRA_MAP_CONF("lc", up, na),
|
||||
TEGRA_MAP_CONF("ld17_0", down, na),
|
||||
TEGRA_MAP_CONF("ld19_18", down, na),
|
||||
TEGRA_MAP_CONF("ld21_20", down, na),
|
||||
TEGRA_MAP_CONF("ld23_22", down, na),
|
||||
};
|
||||
|
||||
static struct tegra_pingroup_config seaboard_pinmux[] = {
|
||||
{TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LPW0, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LPW2, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LSC1, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSCK, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSDA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
static struct pinctrl_map seaboard_map[] = {
|
||||
TEGRA_MAP_MUXCONF("ddc", "rsvd2", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven),
|
||||
TEGRA_MAP_MUXCONF("lpw0", "hdmi", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lpw2", "hdmi", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lsc1", "hdmi", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsck", "hdmi", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsda", "hdmi", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spia", "gmi", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("spic", "gmi", up, driven),
|
||||
TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate),
|
||||
PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, "drive_sdio1", seaboard_pincfg_drive_sdio1),
|
||||
};
|
||||
|
||||
static struct tegra_pingroup_config ventana_pinmux[] = {
|
||||
{TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LSC1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LSCK, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSDA, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_PTA, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SLXK, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
};
|
||||
|
||||
static struct tegra_gpio_table common_gpio_table[] = {
|
||||
{ .gpio = TEGRA_GPIO_SD2_CD, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_SD2_WP, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_SD2_POWER, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true },
|
||||
};
|
||||
|
||||
static struct tegra_gpio_table seaboard_gpio_table[] = {
|
||||
{ .gpio = TEGRA_GPIO_LIDSWITCH, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_POWERKEY, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_HP_DET, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_ISL29018_IRQ, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_USB1, .enable = true },
|
||||
};
|
||||
|
||||
static struct tegra_gpio_table ventana_gpio_table[] = {
|
||||
/* hp_det */
|
||||
{ .gpio = TEGRA_GPIO_PW2, .enable = true },
|
||||
/* int_mic_en */
|
||||
{ .gpio = TEGRA_GPIO_PX0, .enable = true },
|
||||
/* ext_mic_en */
|
||||
{ .gpio = TEGRA_GPIO_PX1, .enable = true },
|
||||
static struct pinctrl_map ventana_map[] = {
|
||||
TEGRA_MAP_MUXCONF("ddc", "rsvd2", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmd", "sflash", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lsc1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxc", "sdio3", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spia", "gmi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spic", "gmi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate),
|
||||
};
|
||||
|
||||
static struct tegra_board_pinmux_conf common_conf = {
|
||||
.pgs = common_pinmux,
|
||||
.pg_count = ARRAY_SIZE(common_pinmux),
|
||||
.gpios = common_gpio_table,
|
||||
.gpio_count = ARRAY_SIZE(common_gpio_table),
|
||||
.maps = common_map,
|
||||
.map_count = ARRAY_SIZE(common_map),
|
||||
};
|
||||
|
||||
static struct tegra_board_pinmux_conf seaboard_conf = {
|
||||
.pgs = seaboard_pinmux,
|
||||
.pg_count = ARRAY_SIZE(seaboard_pinmux),
|
||||
.drives = seaboard_drive_pinmux,
|
||||
.drive_count = ARRAY_SIZE(seaboard_drive_pinmux),
|
||||
.gpios = seaboard_gpio_table,
|
||||
.gpio_count = ARRAY_SIZE(seaboard_gpio_table),
|
||||
.maps = seaboard_map,
|
||||
.map_count = ARRAY_SIZE(seaboard_map),
|
||||
};
|
||||
|
||||
static struct tegra_board_pinmux_conf ventana_conf = {
|
||||
.pgs = ventana_pinmux,
|
||||
.pg_count = ARRAY_SIZE(ventana_pinmux),
|
||||
.gpios = ventana_gpio_table,
|
||||
.gpio_count = ARRAY_SIZE(ventana_gpio_table),
|
||||
.maps = ventana_map,
|
||||
.map_count = ARRAY_SIZE(ventana_map),
|
||||
};
|
||||
|
||||
void seaboard_pinmux_init(void)
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/platform_data/tegra_usb.h>
|
||||
|
||||
#include <sound/wm8903.h>
|
||||
|
||||
|
|
@ -186,20 +187,10 @@ static struct i2c_board_info __initdata wm8903_device = {
|
|||
|
||||
static int seaboard_ehci_init(void)
|
||||
{
|
||||
int gpio_status;
|
||||
struct tegra_ehci_platform_data *pdata;
|
||||
|
||||
gpio_status = gpio_request(TEGRA_GPIO_USB1, "VBUS_USB1");
|
||||
if (gpio_status < 0) {
|
||||
pr_err("VBUS_USB1 request GPIO FAILED\n");
|
||||
WARN_ON(1);
|
||||
}
|
||||
|
||||
gpio_status = gpio_direction_output(TEGRA_GPIO_USB1, 1);
|
||||
if (gpio_status < 0) {
|
||||
pr_err("VBUS_USB1 request GPIO DIRECTION FAILED\n");
|
||||
WARN_ON(1);
|
||||
}
|
||||
gpio_set_value(TEGRA_GPIO_USB1, 1);
|
||||
pdata = tegra_ehci1_device.dev.platform_data;
|
||||
pdata->vbus_gpio = TEGRA_GPIO_USB1;
|
||||
|
||||
platform_device_register(&tegra_ehci1_device);
|
||||
platform_device_register(&tegra_ehci3_device);
|
||||
|
|
@ -209,9 +200,6 @@ static int seaboard_ehci_init(void)
|
|||
|
||||
static void __init seaboard_i2c_init(void)
|
||||
{
|
||||
gpio_request(TEGRA_GPIO_ISL29018_IRQ, "isl29018");
|
||||
gpio_direction_input(TEGRA_GPIO_ISL29018_IRQ);
|
||||
|
||||
isl29018_device.irq = gpio_to_irq(TEGRA_GPIO_ISL29018_IRQ);
|
||||
i2c_register_board_info(0, &isl29018_device, 1);
|
||||
|
||||
|
|
@ -261,7 +249,6 @@ static void __init tegra_kaen_init(void)
|
|||
debug_uart_platform_data[0].irq = INT_UARTB;
|
||||
|
||||
seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE;
|
||||
tegra_gpio_enable(TEGRA_GPIO_KAEN_HP_MUTE);
|
||||
|
||||
seaboard_common_init();
|
||||
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
* arch/arm/mach-tegra/board-trimslice-pinmux.c
|
||||
*
|
||||
* Copyright (C) 2011 CompuLab, Ltd.
|
||||
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
|
|
@ -13,150 +14,139 @@
|
|||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <mach/pinmux.h>
|
||||
#include <mach/pinmux-tegra20.h>
|
||||
|
||||
#include "gpio-names.h"
|
||||
#include "board-pinmux.h"
|
||||
#include "board-trimslice.h"
|
||||
#include "board-pinmux.h"
|
||||
|
||||
static struct tegra_pingroup_config trimslice_pinmux[] = {
|
||||
{TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMB, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_GMC, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GME, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_GPU, TEGRA_MUX_UARTA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_PTA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPDI, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPDO, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIA, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIB, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIC, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
};
|
||||
|
||||
static struct tegra_gpio_table gpio_table[] = {
|
||||
{ .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */
|
||||
{ .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */
|
||||
|
||||
{ .gpio = TRIMSLICE_GPIO_USB1_MODE, .enable = true }, /* USB1 mode */
|
||||
{ .gpio = TRIMSLICE_GPIO_USB2_RST, .enable = true }, /* USB2 PHY rst */
|
||||
static struct pinctrl_map trimslice_map[] = {
|
||||
TEGRA_MAP_MUXCONF("ata", "ide", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atc", "nand", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("atd", "gmi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
|
||||
TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
|
||||
TEGRA_MAP_MUXCONF("dta", "vi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtb", "vi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtc", "vi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtd", "vi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dte", "vi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtf", "i2c3", up, driven),
|
||||
TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmb", "nand", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("gmc", "sflash", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gme", "gmi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("gpu", "uarta", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
|
||||
TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("irrx", "uartb", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("irtx", "uartb", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("kbca", "kbc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("kbcb", "kbc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("kbcc", "kbc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("kbcd", "kbc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("kbce", "kbc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("kbcf", "kbc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("owc", "rsvd2", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("pta", "gmi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("rm", "i2c1", up, driven),
|
||||
TEGRA_MAP_MUXCONF("sdb", "pwm", na, driven),
|
||||
TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven),
|
||||
TEGRA_MAP_MUXCONF("sdd", "pwm", up, driven),
|
||||
TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven),
|
||||
TEGRA_MAP_MUXCONF("slxc", "sdio3", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxd", "sdio3", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spdi", "spdif", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spdo", "spdif", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spia", "spi2", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spib", "spi2", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spic", "spi2", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven),
|
||||
TEGRA_MAP_MUXCONF("uad", "irda", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate),
|
||||
TEGRA_MAP_CONF("ck32", none, na),
|
||||
TEGRA_MAP_CONF("ddrc", none, na),
|
||||
TEGRA_MAP_CONF("pmca", none, na),
|
||||
TEGRA_MAP_CONF("pmcb", none, na),
|
||||
TEGRA_MAP_CONF("pmcc", none, na),
|
||||
TEGRA_MAP_CONF("pmcd", none, na),
|
||||
TEGRA_MAP_CONF("pmce", none, na),
|
||||
TEGRA_MAP_CONF("xm2c", none, na),
|
||||
TEGRA_MAP_CONF("xm2d", none, na),
|
||||
TEGRA_MAP_CONF("ls", up, na),
|
||||
TEGRA_MAP_CONF("lc", up, na),
|
||||
TEGRA_MAP_CONF("ld17_0", down, na),
|
||||
TEGRA_MAP_CONF("ld19_18", down, na),
|
||||
TEGRA_MAP_CONF("ld21_20", down, na),
|
||||
TEGRA_MAP_CONF("ld23_22", down, na),
|
||||
};
|
||||
|
||||
static struct tegra_board_pinmux_conf conf = {
|
||||
.pgs = trimslice_pinmux,
|
||||
.pg_count = ARRAY_SIZE(trimslice_pinmux),
|
||||
.gpios = gpio_table,
|
||||
.gpio_count = ARRAY_SIZE(gpio_table),
|
||||
.maps = trimslice_map,
|
||||
.map_count = ARRAY_SIZE(trimslice_map),
|
||||
};
|
||||
|
||||
void trimslice_pinmux_init(void)
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/platform_data/tegra_usb.h>
|
||||
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
|
@ -111,19 +112,13 @@ static void trimslice_i2c_init(void)
|
|||
|
||||
static void trimslice_usb_init(void)
|
||||
{
|
||||
int err;
|
||||
struct tegra_ehci_platform_data *pdata;
|
||||
|
||||
pdata = tegra_ehci1_device.dev.platform_data;
|
||||
pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE;
|
||||
|
||||
platform_device_register(&tegra_ehci3_device);
|
||||
|
||||
platform_device_register(&tegra_ehci2_device);
|
||||
|
||||
err = gpio_request_one(TRIMSLICE_GPIO_USB1_MODE, GPIOF_OUT_INIT_HIGH,
|
||||
"usb1mode");
|
||||
if (err) {
|
||||
pr_err("TrimSlice: failed to obtain USB1 mode gpio: %d\n", err);
|
||||
return;
|
||||
}
|
||||
|
||||
platform_device_register(&tegra_ehci1_device);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -110,7 +110,7 @@ static struct resource pinmux_resource[] = {
|
|||
};
|
||||
|
||||
struct platform_device tegra_pinmux_device = {
|
||||
.name = "tegra-pinmux",
|
||||
.name = "tegra20-pinctrl",
|
||||
.id = -1,
|
||||
.resource = pinmux_resource,
|
||||
.num_resources = ARRAY_SIZE(pinmux_resource),
|
||||
|
|
@ -448,17 +448,20 @@ static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
|
|||
struct tegra_ehci_platform_data tegra_ehci1_pdata = {
|
||||
.operating_mode = TEGRA_USB_OTG,
|
||||
.power_down_on_bus_suspend = 1,
|
||||
.vbus_gpio = -1,
|
||||
};
|
||||
|
||||
struct tegra_ehci_platform_data tegra_ehci2_pdata = {
|
||||
.phy_config = &tegra_ehci2_ulpi_phy_config,
|
||||
.operating_mode = TEGRA_USB_HOST,
|
||||
.power_down_on_bus_suspend = 1,
|
||||
.vbus_gpio = -1,
|
||||
};
|
||||
|
||||
struct tegra_ehci_platform_data tegra_ehci3_pdata = {
|
||||
.operating_mode = TEGRA_USB_HOST,
|
||||
.power_down_on_bus_suspend = 1,
|
||||
.vbus_gpio = -1,
|
||||
};
|
||||
|
||||
static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
|
||||
|
|
|
|||
|
|
@ -25,13 +25,4 @@
|
|||
|
||||
#define TEGRA_NR_GPIOS INT_GPIO_NR
|
||||
|
||||
struct tegra_gpio_table {
|
||||
int gpio; /* GPIO number */
|
||||
bool enable; /* Enable for GPIO at init? */
|
||||
};
|
||||
|
||||
void tegra_gpio_config(struct tegra_gpio_table *table, int num);
|
||||
void tegra_gpio_enable(int gpio);
|
||||
void tegra_gpio_disable(int gpio);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,184 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
|
||||
*
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H
|
||||
#define __MACH_TEGRA_PINMUX_TEGRA20_H
|
||||
|
||||
enum tegra_pingroup {
|
||||
TEGRA_PINGROUP_ATA = 0,
|
||||
TEGRA_PINGROUP_ATB,
|
||||
TEGRA_PINGROUP_ATC,
|
||||
TEGRA_PINGROUP_ATD,
|
||||
TEGRA_PINGROUP_ATE,
|
||||
TEGRA_PINGROUP_CDEV1,
|
||||
TEGRA_PINGROUP_CDEV2,
|
||||
TEGRA_PINGROUP_CRTP,
|
||||
TEGRA_PINGROUP_CSUS,
|
||||
TEGRA_PINGROUP_DAP1,
|
||||
TEGRA_PINGROUP_DAP2,
|
||||
TEGRA_PINGROUP_DAP3,
|
||||
TEGRA_PINGROUP_DAP4,
|
||||
TEGRA_PINGROUP_DDC,
|
||||
TEGRA_PINGROUP_DTA,
|
||||
TEGRA_PINGROUP_DTB,
|
||||
TEGRA_PINGROUP_DTC,
|
||||
TEGRA_PINGROUP_DTD,
|
||||
TEGRA_PINGROUP_DTE,
|
||||
TEGRA_PINGROUP_DTF,
|
||||
TEGRA_PINGROUP_GMA,
|
||||
TEGRA_PINGROUP_GMB,
|
||||
TEGRA_PINGROUP_GMC,
|
||||
TEGRA_PINGROUP_GMD,
|
||||
TEGRA_PINGROUP_GME,
|
||||
TEGRA_PINGROUP_GPU,
|
||||
TEGRA_PINGROUP_GPU7,
|
||||
TEGRA_PINGROUP_GPV,
|
||||
TEGRA_PINGROUP_HDINT,
|
||||
TEGRA_PINGROUP_I2CP,
|
||||
TEGRA_PINGROUP_IRRX,
|
||||
TEGRA_PINGROUP_IRTX,
|
||||
TEGRA_PINGROUP_KBCA,
|
||||
TEGRA_PINGROUP_KBCB,
|
||||
TEGRA_PINGROUP_KBCC,
|
||||
TEGRA_PINGROUP_KBCD,
|
||||
TEGRA_PINGROUP_KBCE,
|
||||
TEGRA_PINGROUP_KBCF,
|
||||
TEGRA_PINGROUP_LCSN,
|
||||
TEGRA_PINGROUP_LD0,
|
||||
TEGRA_PINGROUP_LD1,
|
||||
TEGRA_PINGROUP_LD10,
|
||||
TEGRA_PINGROUP_LD11,
|
||||
TEGRA_PINGROUP_LD12,
|
||||
TEGRA_PINGROUP_LD13,
|
||||
TEGRA_PINGROUP_LD14,
|
||||
TEGRA_PINGROUP_LD15,
|
||||
TEGRA_PINGROUP_LD16,
|
||||
TEGRA_PINGROUP_LD17,
|
||||
TEGRA_PINGROUP_LD2,
|
||||
TEGRA_PINGROUP_LD3,
|
||||
TEGRA_PINGROUP_LD4,
|
||||
TEGRA_PINGROUP_LD5,
|
||||
TEGRA_PINGROUP_LD6,
|
||||
TEGRA_PINGROUP_LD7,
|
||||
TEGRA_PINGROUP_LD8,
|
||||
TEGRA_PINGROUP_LD9,
|
||||
TEGRA_PINGROUP_LDC,
|
||||
TEGRA_PINGROUP_LDI,
|
||||
TEGRA_PINGROUP_LHP0,
|
||||
TEGRA_PINGROUP_LHP1,
|
||||
TEGRA_PINGROUP_LHP2,
|
||||
TEGRA_PINGROUP_LHS,
|
||||
TEGRA_PINGROUP_LM0,
|
||||
TEGRA_PINGROUP_LM1,
|
||||
TEGRA_PINGROUP_LPP,
|
||||
TEGRA_PINGROUP_LPW0,
|
||||
TEGRA_PINGROUP_LPW1,
|
||||
TEGRA_PINGROUP_LPW2,
|
||||
TEGRA_PINGROUP_LSC0,
|
||||
TEGRA_PINGROUP_LSC1,
|
||||
TEGRA_PINGROUP_LSCK,
|
||||
TEGRA_PINGROUP_LSDA,
|
||||
TEGRA_PINGROUP_LSDI,
|
||||
TEGRA_PINGROUP_LSPI,
|
||||
TEGRA_PINGROUP_LVP0,
|
||||
TEGRA_PINGROUP_LVP1,
|
||||
TEGRA_PINGROUP_LVS,
|
||||
TEGRA_PINGROUP_OWC,
|
||||
TEGRA_PINGROUP_PMC,
|
||||
TEGRA_PINGROUP_PTA,
|
||||
TEGRA_PINGROUP_RM,
|
||||
TEGRA_PINGROUP_SDB,
|
||||
TEGRA_PINGROUP_SDC,
|
||||
TEGRA_PINGROUP_SDD,
|
||||
TEGRA_PINGROUP_SDIO1,
|
||||
TEGRA_PINGROUP_SLXA,
|
||||
TEGRA_PINGROUP_SLXC,
|
||||
TEGRA_PINGROUP_SLXD,
|
||||
TEGRA_PINGROUP_SLXK,
|
||||
TEGRA_PINGROUP_SPDI,
|
||||
TEGRA_PINGROUP_SPDO,
|
||||
TEGRA_PINGROUP_SPIA,
|
||||
TEGRA_PINGROUP_SPIB,
|
||||
TEGRA_PINGROUP_SPIC,
|
||||
TEGRA_PINGROUP_SPID,
|
||||
TEGRA_PINGROUP_SPIE,
|
||||
TEGRA_PINGROUP_SPIF,
|
||||
TEGRA_PINGROUP_SPIG,
|
||||
TEGRA_PINGROUP_SPIH,
|
||||
TEGRA_PINGROUP_UAA,
|
||||
TEGRA_PINGROUP_UAB,
|
||||
TEGRA_PINGROUP_UAC,
|
||||
TEGRA_PINGROUP_UAD,
|
||||
TEGRA_PINGROUP_UCA,
|
||||
TEGRA_PINGROUP_UCB,
|
||||
TEGRA_PINGROUP_UDA,
|
||||
/* these pin groups only have pullup and pull down control */
|
||||
TEGRA_PINGROUP_CK32,
|
||||
TEGRA_PINGROUP_DDRC,
|
||||
TEGRA_PINGROUP_PMCA,
|
||||
TEGRA_PINGROUP_PMCB,
|
||||
TEGRA_PINGROUP_PMCC,
|
||||
TEGRA_PINGROUP_PMCD,
|
||||
TEGRA_PINGROUP_PMCE,
|
||||
TEGRA_PINGROUP_XM2C,
|
||||
TEGRA_PINGROUP_XM2D,
|
||||
TEGRA_MAX_PINGROUP,
|
||||
};
|
||||
|
||||
enum tegra_drive_pingroup {
|
||||
TEGRA_DRIVE_PINGROUP_AO1 = 0,
|
||||
TEGRA_DRIVE_PINGROUP_AO2,
|
||||
TEGRA_DRIVE_PINGROUP_AT1,
|
||||
TEGRA_DRIVE_PINGROUP_AT2,
|
||||
TEGRA_DRIVE_PINGROUP_CDEV1,
|
||||
TEGRA_DRIVE_PINGROUP_CDEV2,
|
||||
TEGRA_DRIVE_PINGROUP_CSUS,
|
||||
TEGRA_DRIVE_PINGROUP_DAP1,
|
||||
TEGRA_DRIVE_PINGROUP_DAP2,
|
||||
TEGRA_DRIVE_PINGROUP_DAP3,
|
||||
TEGRA_DRIVE_PINGROUP_DAP4,
|
||||
TEGRA_DRIVE_PINGROUP_DBG,
|
||||
TEGRA_DRIVE_PINGROUP_LCD1,
|
||||
TEGRA_DRIVE_PINGROUP_LCD2,
|
||||
TEGRA_DRIVE_PINGROUP_SDMMC2,
|
||||
TEGRA_DRIVE_PINGROUP_SDMMC3,
|
||||
TEGRA_DRIVE_PINGROUP_SPI,
|
||||
TEGRA_DRIVE_PINGROUP_UAA,
|
||||
TEGRA_DRIVE_PINGROUP_UAB,
|
||||
TEGRA_DRIVE_PINGROUP_UART2,
|
||||
TEGRA_DRIVE_PINGROUP_UART3,
|
||||
TEGRA_DRIVE_PINGROUP_VI1,
|
||||
TEGRA_DRIVE_PINGROUP_VI2,
|
||||
TEGRA_DRIVE_PINGROUP_XM2A,
|
||||
TEGRA_DRIVE_PINGROUP_XM2C,
|
||||
TEGRA_DRIVE_PINGROUP_XM2D,
|
||||
TEGRA_DRIVE_PINGROUP_XM2CLK,
|
||||
TEGRA_DRIVE_PINGROUP_MEMCOMP,
|
||||
TEGRA_DRIVE_PINGROUP_SDIO1,
|
||||
TEGRA_DRIVE_PINGROUP_CRT,
|
||||
TEGRA_DRIVE_PINGROUP_DDC,
|
||||
TEGRA_DRIVE_PINGROUP_GMA,
|
||||
TEGRA_DRIVE_PINGROUP_GMB,
|
||||
TEGRA_DRIVE_PINGROUP_GMC,
|
||||
TEGRA_DRIVE_PINGROUP_GMD,
|
||||
TEGRA_DRIVE_PINGROUP_GME,
|
||||
TEGRA_DRIVE_PINGROUP_OWR,
|
||||
TEGRA_DRIVE_PINGROUP_UAD,
|
||||
TEGRA_MAX_DRIVE_PINGROUP,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -1,320 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
|
||||
*
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
* Copyright (C) 2010,2011 Nvidia, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H
|
||||
#define __MACH_TEGRA_PINMUX_TEGRA30_H
|
||||
|
||||
enum tegra_pingroup {
|
||||
TEGRA_PINGROUP_ULPI_DATA0 = 0,
|
||||
TEGRA_PINGROUP_ULPI_DATA1,
|
||||
TEGRA_PINGROUP_ULPI_DATA2,
|
||||
TEGRA_PINGROUP_ULPI_DATA3,
|
||||
TEGRA_PINGROUP_ULPI_DATA4,
|
||||
TEGRA_PINGROUP_ULPI_DATA5,
|
||||
TEGRA_PINGROUP_ULPI_DATA6,
|
||||
TEGRA_PINGROUP_ULPI_DATA7,
|
||||
TEGRA_PINGROUP_ULPI_CLK,
|
||||
TEGRA_PINGROUP_ULPI_DIR,
|
||||
TEGRA_PINGROUP_ULPI_NXT,
|
||||
TEGRA_PINGROUP_ULPI_STP,
|
||||
TEGRA_PINGROUP_DAP3_FS,
|
||||
TEGRA_PINGROUP_DAP3_DIN,
|
||||
TEGRA_PINGROUP_DAP3_DOUT,
|
||||
TEGRA_PINGROUP_DAP3_SCLK,
|
||||
TEGRA_PINGROUP_GPIO_PV0,
|
||||
TEGRA_PINGROUP_GPIO_PV1,
|
||||
TEGRA_PINGROUP_SDMMC1_CLK,
|
||||
TEGRA_PINGROUP_SDMMC1_CMD,
|
||||
TEGRA_PINGROUP_SDMMC1_DAT3,
|
||||
TEGRA_PINGROUP_SDMMC1_DAT2,
|
||||
TEGRA_PINGROUP_SDMMC1_DAT1,
|
||||
TEGRA_PINGROUP_SDMMC1_DAT0,
|
||||
TEGRA_PINGROUP_GPIO_PV2,
|
||||
TEGRA_PINGROUP_GPIO_PV3,
|
||||
TEGRA_PINGROUP_CLK2_OUT,
|
||||
TEGRA_PINGROUP_CLK2_REQ,
|
||||
TEGRA_PINGROUP_LCD_PWR1,
|
||||
TEGRA_PINGROUP_LCD_PWR2,
|
||||
TEGRA_PINGROUP_LCD_SDIN,
|
||||
TEGRA_PINGROUP_LCD_SDOUT,
|
||||
TEGRA_PINGROUP_LCD_WR_N,
|
||||
TEGRA_PINGROUP_LCD_CS0_N,
|
||||
TEGRA_PINGROUP_LCD_DC0,
|
||||
TEGRA_PINGROUP_LCD_SCK,
|
||||
TEGRA_PINGROUP_LCD_PWR0,
|
||||
TEGRA_PINGROUP_LCD_PCLK,
|
||||
TEGRA_PINGROUP_LCD_DE,
|
||||
TEGRA_PINGROUP_LCD_HSYNC,
|
||||
TEGRA_PINGROUP_LCD_VSYNC,
|
||||
TEGRA_PINGROUP_LCD_D0,
|
||||
TEGRA_PINGROUP_LCD_D1,
|
||||
TEGRA_PINGROUP_LCD_D2,
|
||||
TEGRA_PINGROUP_LCD_D3,
|
||||
TEGRA_PINGROUP_LCD_D4,
|
||||
TEGRA_PINGROUP_LCD_D5,
|
||||
TEGRA_PINGROUP_LCD_D6,
|
||||
TEGRA_PINGROUP_LCD_D7,
|
||||
TEGRA_PINGROUP_LCD_D8,
|
||||
TEGRA_PINGROUP_LCD_D9,
|
||||
TEGRA_PINGROUP_LCD_D10,
|
||||
TEGRA_PINGROUP_LCD_D11,
|
||||
TEGRA_PINGROUP_LCD_D12,
|
||||
TEGRA_PINGROUP_LCD_D13,
|
||||
TEGRA_PINGROUP_LCD_D14,
|
||||
TEGRA_PINGROUP_LCD_D15,
|
||||
TEGRA_PINGROUP_LCD_D16,
|
||||
TEGRA_PINGROUP_LCD_D17,
|
||||
TEGRA_PINGROUP_LCD_D18,
|
||||
TEGRA_PINGROUP_LCD_D19,
|
||||
TEGRA_PINGROUP_LCD_D20,
|
||||
TEGRA_PINGROUP_LCD_D21,
|
||||
TEGRA_PINGROUP_LCD_D22,
|
||||
TEGRA_PINGROUP_LCD_D23,
|
||||
TEGRA_PINGROUP_LCD_CS1_N,
|
||||
TEGRA_PINGROUP_LCD_M1,
|
||||
TEGRA_PINGROUP_LCD_DC1,
|
||||
TEGRA_PINGROUP_HDMI_INT,
|
||||
TEGRA_PINGROUP_DDC_SCL,
|
||||
TEGRA_PINGROUP_DDC_SDA,
|
||||
TEGRA_PINGROUP_CRT_HSYNC,
|
||||
TEGRA_PINGROUP_CRT_VSYNC,
|
||||
TEGRA_PINGROUP_VI_D0,
|
||||
TEGRA_PINGROUP_VI_D1,
|
||||
TEGRA_PINGROUP_VI_D2,
|
||||
TEGRA_PINGROUP_VI_D3,
|
||||
TEGRA_PINGROUP_VI_D4,
|
||||
TEGRA_PINGROUP_VI_D5,
|
||||
TEGRA_PINGROUP_VI_D6,
|
||||
TEGRA_PINGROUP_VI_D7,
|
||||
TEGRA_PINGROUP_VI_D8,
|
||||
TEGRA_PINGROUP_VI_D9,
|
||||
TEGRA_PINGROUP_VI_D10,
|
||||
TEGRA_PINGROUP_VI_D11,
|
||||
TEGRA_PINGROUP_VI_PCLK,
|
||||
TEGRA_PINGROUP_VI_MCLK,
|
||||
TEGRA_PINGROUP_VI_VSYNC,
|
||||
TEGRA_PINGROUP_VI_HSYNC,
|
||||
TEGRA_PINGROUP_UART2_RXD,
|
||||
TEGRA_PINGROUP_UART2_TXD,
|
||||
TEGRA_PINGROUP_UART2_RTS_N,
|
||||
TEGRA_PINGROUP_UART2_CTS_N,
|
||||
TEGRA_PINGROUP_UART3_TXD,
|
||||
TEGRA_PINGROUP_UART3_RXD,
|
||||
TEGRA_PINGROUP_UART3_CTS_N,
|
||||
TEGRA_PINGROUP_UART3_RTS_N,
|
||||
TEGRA_PINGROUP_GPIO_PU0,
|
||||
TEGRA_PINGROUP_GPIO_PU1,
|
||||
TEGRA_PINGROUP_GPIO_PU2,
|
||||
TEGRA_PINGROUP_GPIO_PU3,
|
||||
TEGRA_PINGROUP_GPIO_PU4,
|
||||
TEGRA_PINGROUP_GPIO_PU5,
|
||||
TEGRA_PINGROUP_GPIO_PU6,
|
||||
TEGRA_PINGROUP_GEN1_I2C_SDA,
|
||||
TEGRA_PINGROUP_GEN1_I2C_SCL,
|
||||
TEGRA_PINGROUP_DAP4_FS,
|
||||
TEGRA_PINGROUP_DAP4_DIN,
|
||||
TEGRA_PINGROUP_DAP4_DOUT,
|
||||
TEGRA_PINGROUP_DAP4_SCLK,
|
||||
TEGRA_PINGROUP_CLK3_OUT,
|
||||
TEGRA_PINGROUP_CLK3_REQ,
|
||||
TEGRA_PINGROUP_GMI_WP_N,
|
||||
TEGRA_PINGROUP_GMI_IORDY,
|
||||
TEGRA_PINGROUP_GMI_WAIT,
|
||||
TEGRA_PINGROUP_GMI_ADV_N,
|
||||
TEGRA_PINGROUP_GMI_CLK,
|
||||
TEGRA_PINGROUP_GMI_CS0_N,
|
||||
TEGRA_PINGROUP_GMI_CS1_N,
|
||||
TEGRA_PINGROUP_GMI_CS2_N,
|
||||
TEGRA_PINGROUP_GMI_CS3_N,
|
||||
TEGRA_PINGROUP_GMI_CS4_N,
|
||||
TEGRA_PINGROUP_GMI_CS6_N,
|
||||
TEGRA_PINGROUP_GMI_CS7_N,
|
||||
TEGRA_PINGROUP_GMI_AD0,
|
||||
TEGRA_PINGROUP_GMI_AD1,
|
||||
TEGRA_PINGROUP_GMI_AD2,
|
||||
TEGRA_PINGROUP_GMI_AD3,
|
||||
TEGRA_PINGROUP_GMI_AD4,
|
||||
TEGRA_PINGROUP_GMI_AD5,
|
||||
TEGRA_PINGROUP_GMI_AD6,
|
||||
TEGRA_PINGROUP_GMI_AD7,
|
||||
TEGRA_PINGROUP_GMI_AD8,
|
||||
TEGRA_PINGROUP_GMI_AD9,
|
||||
TEGRA_PINGROUP_GMI_AD10,
|
||||
TEGRA_PINGROUP_GMI_AD11,
|
||||
TEGRA_PINGROUP_GMI_AD12,
|
||||
TEGRA_PINGROUP_GMI_AD13,
|
||||
TEGRA_PINGROUP_GMI_AD14,
|
||||
TEGRA_PINGROUP_GMI_AD15,
|
||||
TEGRA_PINGROUP_GMI_A16,
|
||||
TEGRA_PINGROUP_GMI_A17,
|
||||
TEGRA_PINGROUP_GMI_A18,
|
||||
TEGRA_PINGROUP_GMI_A19,
|
||||
TEGRA_PINGROUP_GMI_WR_N,
|
||||
TEGRA_PINGROUP_GMI_OE_N,
|
||||
TEGRA_PINGROUP_GMI_DQS,
|
||||
TEGRA_PINGROUP_GMI_RST_N,
|
||||
TEGRA_PINGROUP_GEN2_I2C_SCL,
|
||||
TEGRA_PINGROUP_GEN2_I2C_SDA,
|
||||
TEGRA_PINGROUP_SDMMC4_CLK,
|
||||
TEGRA_PINGROUP_SDMMC4_CMD,
|
||||
TEGRA_PINGROUP_SDMMC4_DAT0,
|
||||
TEGRA_PINGROUP_SDMMC4_DAT1,
|
||||
TEGRA_PINGROUP_SDMMC4_DAT2,
|
||||
TEGRA_PINGROUP_SDMMC4_DAT3,
|
||||
TEGRA_PINGROUP_SDMMC4_DAT4,
|
||||
TEGRA_PINGROUP_SDMMC4_DAT5,
|
||||
TEGRA_PINGROUP_SDMMC4_DAT6,
|
||||
TEGRA_PINGROUP_SDMMC4_DAT7,
|
||||
TEGRA_PINGROUP_SDMMC4_RST_N,
|
||||
TEGRA_PINGROUP_CAM_MCLK,
|
||||
TEGRA_PINGROUP_GPIO_PCC1,
|
||||
TEGRA_PINGROUP_GPIO_PBB0,
|
||||
TEGRA_PINGROUP_CAM_I2C_SCL,
|
||||
TEGRA_PINGROUP_CAM_I2C_SDA,
|
||||
TEGRA_PINGROUP_GPIO_PBB3,
|
||||
TEGRA_PINGROUP_GPIO_PBB4,
|
||||
TEGRA_PINGROUP_GPIO_PBB5,
|
||||
TEGRA_PINGROUP_GPIO_PBB6,
|
||||
TEGRA_PINGROUP_GPIO_PBB7,
|
||||
TEGRA_PINGROUP_GPIO_PCC2,
|
||||
TEGRA_PINGROUP_JTAG_RTCK,
|
||||
TEGRA_PINGROUP_PWR_I2C_SCL,
|
||||
TEGRA_PINGROUP_PWR_I2C_SDA,
|
||||
TEGRA_PINGROUP_KB_ROW0,
|
||||
TEGRA_PINGROUP_KB_ROW1,
|
||||
TEGRA_PINGROUP_KB_ROW2,
|
||||
TEGRA_PINGROUP_KB_ROW3,
|
||||
TEGRA_PINGROUP_KB_ROW4,
|
||||
TEGRA_PINGROUP_KB_ROW5,
|
||||
TEGRA_PINGROUP_KB_ROW6,
|
||||
TEGRA_PINGROUP_KB_ROW7,
|
||||
TEGRA_PINGROUP_KB_ROW8,
|
||||
TEGRA_PINGROUP_KB_ROW9,
|
||||
TEGRA_PINGROUP_KB_ROW10,
|
||||
TEGRA_PINGROUP_KB_ROW11,
|
||||
TEGRA_PINGROUP_KB_ROW12,
|
||||
TEGRA_PINGROUP_KB_ROW13,
|
||||
TEGRA_PINGROUP_KB_ROW14,
|
||||
TEGRA_PINGROUP_KB_ROW15,
|
||||
TEGRA_PINGROUP_KB_COL0,
|
||||
TEGRA_PINGROUP_KB_COL1,
|
||||
TEGRA_PINGROUP_KB_COL2,
|
||||
TEGRA_PINGROUP_KB_COL3,
|
||||
TEGRA_PINGROUP_KB_COL4,
|
||||
TEGRA_PINGROUP_KB_COL5,
|
||||
TEGRA_PINGROUP_KB_COL6,
|
||||
TEGRA_PINGROUP_KB_COL7,
|
||||
TEGRA_PINGROUP_CLK_32K_OUT,
|
||||
TEGRA_PINGROUP_SYS_CLK_REQ,
|
||||
TEGRA_PINGROUP_CORE_PWR_REQ,
|
||||
TEGRA_PINGROUP_CPU_PWR_REQ,
|
||||
TEGRA_PINGROUP_PWR_INT_N,
|
||||
TEGRA_PINGROUP_CLK_32K_IN,
|
||||
TEGRA_PINGROUP_OWR,
|
||||
TEGRA_PINGROUP_DAP1_FS,
|
||||
TEGRA_PINGROUP_DAP1_DIN,
|
||||
TEGRA_PINGROUP_DAP1_DOUT,
|
||||
TEGRA_PINGROUP_DAP1_SCLK,
|
||||
TEGRA_PINGROUP_CLK1_REQ,
|
||||
TEGRA_PINGROUP_CLK1_OUT,
|
||||
TEGRA_PINGROUP_SPDIF_IN,
|
||||
TEGRA_PINGROUP_SPDIF_OUT,
|
||||
TEGRA_PINGROUP_DAP2_FS,
|
||||
TEGRA_PINGROUP_DAP2_DIN,
|
||||
TEGRA_PINGROUP_DAP2_DOUT,
|
||||
TEGRA_PINGROUP_DAP2_SCLK,
|
||||
TEGRA_PINGROUP_SPI2_MOSI,
|
||||
TEGRA_PINGROUP_SPI2_MISO,
|
||||
TEGRA_PINGROUP_SPI2_CS0_N,
|
||||
TEGRA_PINGROUP_SPI2_SCK,
|
||||
TEGRA_PINGROUP_SPI1_MOSI,
|
||||
TEGRA_PINGROUP_SPI1_SCK,
|
||||
TEGRA_PINGROUP_SPI1_CS0_N,
|
||||
TEGRA_PINGROUP_SPI1_MISO,
|
||||
TEGRA_PINGROUP_SPI2_CS1_N,
|
||||
TEGRA_PINGROUP_SPI2_CS2_N,
|
||||
TEGRA_PINGROUP_SDMMC3_CLK,
|
||||
TEGRA_PINGROUP_SDMMC3_CMD,
|
||||
TEGRA_PINGROUP_SDMMC3_DAT0,
|
||||
TEGRA_PINGROUP_SDMMC3_DAT1,
|
||||
TEGRA_PINGROUP_SDMMC3_DAT2,
|
||||
TEGRA_PINGROUP_SDMMC3_DAT3,
|
||||
TEGRA_PINGROUP_SDMMC3_DAT4,
|
||||
TEGRA_PINGROUP_SDMMC3_DAT5,
|
||||
TEGRA_PINGROUP_SDMMC3_DAT6,
|
||||
TEGRA_PINGROUP_SDMMC3_DAT7,
|
||||
TEGRA_PINGROUP_PEX_L0_PRSNT_N,
|
||||
TEGRA_PINGROUP_PEX_L0_RST_N,
|
||||
TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
|
||||
TEGRA_PINGROUP_PEX_WAKE_N,
|
||||
TEGRA_PINGROUP_PEX_L1_PRSNT_N,
|
||||
TEGRA_PINGROUP_PEX_L1_RST_N,
|
||||
TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
|
||||
TEGRA_PINGROUP_PEX_L2_PRSNT_N,
|
||||
TEGRA_PINGROUP_PEX_L2_RST_N,
|
||||
TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
|
||||
TEGRA_PINGROUP_HDMI_CEC,
|
||||
TEGRA_MAX_PINGROUP,
|
||||
};
|
||||
|
||||
enum tegra_drive_pingroup {
|
||||
TEGRA_DRIVE_PINGROUP_AO1 = 0,
|
||||
TEGRA_DRIVE_PINGROUP_AO2,
|
||||
TEGRA_DRIVE_PINGROUP_AT1,
|
||||
TEGRA_DRIVE_PINGROUP_AT2,
|
||||
TEGRA_DRIVE_PINGROUP_AT3,
|
||||
TEGRA_DRIVE_PINGROUP_AT4,
|
||||
TEGRA_DRIVE_PINGROUP_AT5,
|
||||
TEGRA_DRIVE_PINGROUP_CDEV1,
|
||||
TEGRA_DRIVE_PINGROUP_CDEV2,
|
||||
TEGRA_DRIVE_PINGROUP_CSUS,
|
||||
TEGRA_DRIVE_PINGROUP_DAP1,
|
||||
TEGRA_DRIVE_PINGROUP_DAP2,
|
||||
TEGRA_DRIVE_PINGROUP_DAP3,
|
||||
TEGRA_DRIVE_PINGROUP_DAP4,
|
||||
TEGRA_DRIVE_PINGROUP_DBG,
|
||||
TEGRA_DRIVE_PINGROUP_LCD1,
|
||||
TEGRA_DRIVE_PINGROUP_LCD2,
|
||||
TEGRA_DRIVE_PINGROUP_SDIO2,
|
||||
TEGRA_DRIVE_PINGROUP_SDIO3,
|
||||
TEGRA_DRIVE_PINGROUP_SPI,
|
||||
TEGRA_DRIVE_PINGROUP_UAA,
|
||||
TEGRA_DRIVE_PINGROUP_UAB,
|
||||
TEGRA_DRIVE_PINGROUP_UART2,
|
||||
TEGRA_DRIVE_PINGROUP_UART3,
|
||||
TEGRA_DRIVE_PINGROUP_VI1,
|
||||
TEGRA_DRIVE_PINGROUP_SDIO1,
|
||||
TEGRA_DRIVE_PINGROUP_CRT,
|
||||
TEGRA_DRIVE_PINGROUP_DDC,
|
||||
TEGRA_DRIVE_PINGROUP_GMA,
|
||||
TEGRA_DRIVE_PINGROUP_GMB,
|
||||
TEGRA_DRIVE_PINGROUP_GMC,
|
||||
TEGRA_DRIVE_PINGROUP_GMD,
|
||||
TEGRA_DRIVE_PINGROUP_GME,
|
||||
TEGRA_DRIVE_PINGROUP_GMF,
|
||||
TEGRA_DRIVE_PINGROUP_GMG,
|
||||
TEGRA_DRIVE_PINGROUP_GMH,
|
||||
TEGRA_DRIVE_PINGROUP_OWR,
|
||||
TEGRA_DRIVE_PINGROUP_UAD,
|
||||
TEGRA_DRIVE_PINGROUP_GPV,
|
||||
TEGRA_DRIVE_PINGROUP_DEV3,
|
||||
TEGRA_DRIVE_PINGROUP_CEC,
|
||||
TEGRA_MAX_DRIVE_PINGROUP,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -1,302 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-tegra/include/mach/pinmux.h
|
||||
*
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
* Copyright (C) 2010,2011 Nvidia, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MACH_TEGRA_PINMUX_H
|
||||
#define __MACH_TEGRA_PINMUX_H
|
||||
|
||||
enum tegra_mux_func {
|
||||
TEGRA_MUX_RSVD = 0x8000,
|
||||
TEGRA_MUX_RSVD1 = 0x8000,
|
||||
TEGRA_MUX_RSVD2 = 0x8001,
|
||||
TEGRA_MUX_RSVD3 = 0x8002,
|
||||
TEGRA_MUX_RSVD4 = 0x8003,
|
||||
TEGRA_MUX_INVALID = 0x4000,
|
||||
TEGRA_MUX_NONE = -1,
|
||||
TEGRA_MUX_AHB_CLK,
|
||||
TEGRA_MUX_APB_CLK,
|
||||
TEGRA_MUX_AUDIO_SYNC,
|
||||
TEGRA_MUX_CRT,
|
||||
TEGRA_MUX_DAP1,
|
||||
TEGRA_MUX_DAP2,
|
||||
TEGRA_MUX_DAP3,
|
||||
TEGRA_MUX_DAP4,
|
||||
TEGRA_MUX_DAP5,
|
||||
TEGRA_MUX_DISPLAYA,
|
||||
TEGRA_MUX_DISPLAYB,
|
||||
TEGRA_MUX_EMC_TEST0_DLL,
|
||||
TEGRA_MUX_EMC_TEST1_DLL,
|
||||
TEGRA_MUX_GMI,
|
||||
TEGRA_MUX_GMI_INT,
|
||||
TEGRA_MUX_HDMI,
|
||||
TEGRA_MUX_I2C,
|
||||
TEGRA_MUX_I2C2,
|
||||
TEGRA_MUX_I2C3,
|
||||
TEGRA_MUX_IDE,
|
||||
TEGRA_MUX_IRDA,
|
||||
TEGRA_MUX_KBC,
|
||||
TEGRA_MUX_MIO,
|
||||
TEGRA_MUX_MIPI_HS,
|
||||
TEGRA_MUX_NAND,
|
||||
TEGRA_MUX_OSC,
|
||||
TEGRA_MUX_OWR,
|
||||
TEGRA_MUX_PCIE,
|
||||
TEGRA_MUX_PLLA_OUT,
|
||||
TEGRA_MUX_PLLC_OUT1,
|
||||
TEGRA_MUX_PLLM_OUT1,
|
||||
TEGRA_MUX_PLLP_OUT2,
|
||||
TEGRA_MUX_PLLP_OUT3,
|
||||
TEGRA_MUX_PLLP_OUT4,
|
||||
TEGRA_MUX_PWM,
|
||||
TEGRA_MUX_PWR_INTR,
|
||||
TEGRA_MUX_PWR_ON,
|
||||
TEGRA_MUX_RTCK,
|
||||
TEGRA_MUX_SDIO1,
|
||||
TEGRA_MUX_SDIO2,
|
||||
TEGRA_MUX_SDIO3,
|
||||
TEGRA_MUX_SDIO4,
|
||||
TEGRA_MUX_SFLASH,
|
||||
TEGRA_MUX_SPDIF,
|
||||
TEGRA_MUX_SPI1,
|
||||
TEGRA_MUX_SPI2,
|
||||
TEGRA_MUX_SPI2_ALT,
|
||||
TEGRA_MUX_SPI3,
|
||||
TEGRA_MUX_SPI4,
|
||||
TEGRA_MUX_TRACE,
|
||||
TEGRA_MUX_TWC,
|
||||
TEGRA_MUX_UARTA,
|
||||
TEGRA_MUX_UARTB,
|
||||
TEGRA_MUX_UARTC,
|
||||
TEGRA_MUX_UARTD,
|
||||
TEGRA_MUX_UARTE,
|
||||
TEGRA_MUX_ULPI,
|
||||
TEGRA_MUX_VI,
|
||||
TEGRA_MUX_VI_SENSOR_CLK,
|
||||
TEGRA_MUX_XIO,
|
||||
TEGRA_MUX_BLINK,
|
||||
TEGRA_MUX_CEC,
|
||||
TEGRA_MUX_CLK12,
|
||||
TEGRA_MUX_DAP,
|
||||
TEGRA_MUX_DAPSDMMC2,
|
||||
TEGRA_MUX_DDR,
|
||||
TEGRA_MUX_DEV3,
|
||||
TEGRA_MUX_DTV,
|
||||
TEGRA_MUX_VI_ALT1,
|
||||
TEGRA_MUX_VI_ALT2,
|
||||
TEGRA_MUX_VI_ALT3,
|
||||
TEGRA_MUX_EMC_DLL,
|
||||
TEGRA_MUX_EXTPERIPH1,
|
||||
TEGRA_MUX_EXTPERIPH2,
|
||||
TEGRA_MUX_EXTPERIPH3,
|
||||
TEGRA_MUX_GMI_ALT,
|
||||
TEGRA_MUX_HDA,
|
||||
TEGRA_MUX_HSI,
|
||||
TEGRA_MUX_I2C4,
|
||||
TEGRA_MUX_I2C5,
|
||||
TEGRA_MUX_I2CPWR,
|
||||
TEGRA_MUX_I2S0,
|
||||
TEGRA_MUX_I2S1,
|
||||
TEGRA_MUX_I2S2,
|
||||
TEGRA_MUX_I2S3,
|
||||
TEGRA_MUX_I2S4,
|
||||
TEGRA_MUX_NAND_ALT,
|
||||
TEGRA_MUX_POPSDIO4,
|
||||
TEGRA_MUX_POPSDMMC4,
|
||||
TEGRA_MUX_PWM0,
|
||||
TEGRA_MUX_PWM1,
|
||||
TEGRA_MUX_PWM2,
|
||||
TEGRA_MUX_PWM3,
|
||||
TEGRA_MUX_SATA,
|
||||
TEGRA_MUX_SPI5,
|
||||
TEGRA_MUX_SPI6,
|
||||
TEGRA_MUX_SYSCLK,
|
||||
TEGRA_MUX_VGP1,
|
||||
TEGRA_MUX_VGP2,
|
||||
TEGRA_MUX_VGP3,
|
||||
TEGRA_MUX_VGP4,
|
||||
TEGRA_MUX_VGP5,
|
||||
TEGRA_MUX_VGP6,
|
||||
TEGRA_MUX_SAFE,
|
||||
TEGRA_MAX_MUX,
|
||||
};
|
||||
|
||||
enum tegra_pullupdown {
|
||||
TEGRA_PUPD_NORMAL = 0,
|
||||
TEGRA_PUPD_PULL_DOWN,
|
||||
TEGRA_PUPD_PULL_UP,
|
||||
};
|
||||
|
||||
enum tegra_tristate {
|
||||
TEGRA_TRI_NORMAL = 0,
|
||||
TEGRA_TRI_TRISTATE = 1,
|
||||
};
|
||||
|
||||
enum tegra_pin_io {
|
||||
TEGRA_PIN_OUTPUT = 0,
|
||||
TEGRA_PIN_INPUT = 1,
|
||||
};
|
||||
|
||||
enum tegra_vddio {
|
||||
TEGRA_VDDIO_BB = 0,
|
||||
TEGRA_VDDIO_LCD,
|
||||
TEGRA_VDDIO_VI,
|
||||
TEGRA_VDDIO_UART,
|
||||
TEGRA_VDDIO_DDR,
|
||||
TEGRA_VDDIO_NAND,
|
||||
TEGRA_VDDIO_SYS,
|
||||
TEGRA_VDDIO_AUDIO,
|
||||
TEGRA_VDDIO_SD,
|
||||
TEGRA_VDDIO_CAM,
|
||||
TEGRA_VDDIO_GMI,
|
||||
TEGRA_VDDIO_PEXCTL,
|
||||
TEGRA_VDDIO_SDMMC1,
|
||||
TEGRA_VDDIO_SDMMC3,
|
||||
TEGRA_VDDIO_SDMMC4,
|
||||
};
|
||||
|
||||
struct tegra_pingroup_config {
|
||||
int pingroup;
|
||||
enum tegra_mux_func func;
|
||||
enum tegra_pullupdown pupd;
|
||||
enum tegra_tristate tristate;
|
||||
};
|
||||
|
||||
enum tegra_slew {
|
||||
TEGRA_SLEW_FASTEST = 0,
|
||||
TEGRA_SLEW_FAST,
|
||||
TEGRA_SLEW_SLOW,
|
||||
TEGRA_SLEW_SLOWEST,
|
||||
TEGRA_MAX_SLEW,
|
||||
};
|
||||
|
||||
enum tegra_pull_strength {
|
||||
TEGRA_PULL_0 = 0,
|
||||
TEGRA_PULL_1,
|
||||
TEGRA_PULL_2,
|
||||
TEGRA_PULL_3,
|
||||
TEGRA_PULL_4,
|
||||
TEGRA_PULL_5,
|
||||
TEGRA_PULL_6,
|
||||
TEGRA_PULL_7,
|
||||
TEGRA_PULL_8,
|
||||
TEGRA_PULL_9,
|
||||
TEGRA_PULL_10,
|
||||
TEGRA_PULL_11,
|
||||
TEGRA_PULL_12,
|
||||
TEGRA_PULL_13,
|
||||
TEGRA_PULL_14,
|
||||
TEGRA_PULL_15,
|
||||
TEGRA_PULL_16,
|
||||
TEGRA_PULL_17,
|
||||
TEGRA_PULL_18,
|
||||
TEGRA_PULL_19,
|
||||
TEGRA_PULL_20,
|
||||
TEGRA_PULL_21,
|
||||
TEGRA_PULL_22,
|
||||
TEGRA_PULL_23,
|
||||
TEGRA_PULL_24,
|
||||
TEGRA_PULL_25,
|
||||
TEGRA_PULL_26,
|
||||
TEGRA_PULL_27,
|
||||
TEGRA_PULL_28,
|
||||
TEGRA_PULL_29,
|
||||
TEGRA_PULL_30,
|
||||
TEGRA_PULL_31,
|
||||
TEGRA_MAX_PULL,
|
||||
};
|
||||
|
||||
enum tegra_drive {
|
||||
TEGRA_DRIVE_DIV_8 = 0,
|
||||
TEGRA_DRIVE_DIV_4,
|
||||
TEGRA_DRIVE_DIV_2,
|
||||
TEGRA_DRIVE_DIV_1,
|
||||
TEGRA_MAX_DRIVE,
|
||||
};
|
||||
|
||||
enum tegra_hsm {
|
||||
TEGRA_HSM_DISABLE = 0,
|
||||
TEGRA_HSM_ENABLE,
|
||||
};
|
||||
|
||||
enum tegra_schmitt {
|
||||
TEGRA_SCHMITT_DISABLE = 0,
|
||||
TEGRA_SCHMITT_ENABLE,
|
||||
};
|
||||
|
||||
struct tegra_drive_pingroup_config {
|
||||
int pingroup;
|
||||
enum tegra_hsm hsm;
|
||||
enum tegra_schmitt schmitt;
|
||||
enum tegra_drive drive;
|
||||
enum tegra_pull_strength pull_down;
|
||||
enum tegra_pull_strength pull_up;
|
||||
enum tegra_slew slew_rising;
|
||||
enum tegra_slew slew_falling;
|
||||
};
|
||||
|
||||
struct tegra_drive_pingroup_desc {
|
||||
const char *name;
|
||||
s16 reg_bank;
|
||||
s16 reg;
|
||||
};
|
||||
|
||||
struct tegra_pingroup_desc {
|
||||
const char *name;
|
||||
int funcs[4];
|
||||
int func_safe;
|
||||
int vddio;
|
||||
enum tegra_pin_io io_default;
|
||||
s16 tri_bank; /* Register bank the tri_reg exists within */
|
||||
s16 mux_bank; /* Register bank the mux_reg exists within */
|
||||
s16 pupd_bank; /* Register bank the pupd_reg exists within */
|
||||
s16 tri_reg; /* offset into the TRISTATE_REG_* register bank */
|
||||
s16 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */
|
||||
s16 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */
|
||||
s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */
|
||||
s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */
|
||||
s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */
|
||||
s8 lock_bit; /* offset of the LOCK bit into mux register bit */
|
||||
s8 od_bit; /* offset of the OD bit into mux register bit */
|
||||
s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
|
||||
};
|
||||
|
||||
typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
|
||||
int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
|
||||
int *pgdrive_max);
|
||||
|
||||
void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
|
||||
const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
|
||||
|
||||
void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
|
||||
const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
|
||||
|
||||
int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
|
||||
int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
|
||||
|
||||
void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
|
||||
int len);
|
||||
|
||||
void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
|
||||
int len);
|
||||
void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
|
||||
int len);
|
||||
void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
|
||||
int len);
|
||||
void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
|
||||
int len, enum tegra_tristate tristate);
|
||||
void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
|
||||
int len, enum tegra_pullupdown pupd);
|
||||
#endif
|
||||
|
|
@ -1,244 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c
|
||||
*
|
||||
* Common pinmux configurations for Tegra20 SoCs
|
||||
*
|
||||
* Copyright (C) 2010 NVIDIA Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
#include <mach/pinmux.h>
|
||||
#include <mach/pinmux-tegra20.h>
|
||||
#include <mach/suspend.h>
|
||||
|
||||
#define TRISTATE_REG_A 0x14
|
||||
#define PIN_MUX_CTL_REG_A 0x80
|
||||
#define PULLUPDOWN_REG_A 0xa0
|
||||
#define PINGROUP_REG_A 0x868
|
||||
|
||||
#define DRIVE_PINGROUP(pg_name, r) \
|
||||
[TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
|
||||
.name = #pg_name, \
|
||||
.reg_bank = 3, \
|
||||
.reg = ((r) - PINGROUP_REG_A) \
|
||||
}
|
||||
|
||||
static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
|
||||
DRIVE_PINGROUP(AO1, 0x868),
|
||||
DRIVE_PINGROUP(AO2, 0x86c),
|
||||
DRIVE_PINGROUP(AT1, 0x870),
|
||||
DRIVE_PINGROUP(AT2, 0x874),
|
||||
DRIVE_PINGROUP(CDEV1, 0x878),
|
||||
DRIVE_PINGROUP(CDEV2, 0x87c),
|
||||
DRIVE_PINGROUP(CSUS, 0x880),
|
||||
DRIVE_PINGROUP(DAP1, 0x884),
|
||||
DRIVE_PINGROUP(DAP2, 0x888),
|
||||
DRIVE_PINGROUP(DAP3, 0x88c),
|
||||
DRIVE_PINGROUP(DAP4, 0x890),
|
||||
DRIVE_PINGROUP(DBG, 0x894),
|
||||
DRIVE_PINGROUP(LCD1, 0x898),
|
||||
DRIVE_PINGROUP(LCD2, 0x89c),
|
||||
DRIVE_PINGROUP(SDMMC2, 0x8a0),
|
||||
DRIVE_PINGROUP(SDMMC3, 0x8a4),
|
||||
DRIVE_PINGROUP(SPI, 0x8a8),
|
||||
DRIVE_PINGROUP(UAA, 0x8ac),
|
||||
DRIVE_PINGROUP(UAB, 0x8b0),
|
||||
DRIVE_PINGROUP(UART2, 0x8b4),
|
||||
DRIVE_PINGROUP(UART3, 0x8b8),
|
||||
DRIVE_PINGROUP(VI1, 0x8bc),
|
||||
DRIVE_PINGROUP(VI2, 0x8c0),
|
||||
DRIVE_PINGROUP(XM2A, 0x8c4),
|
||||
DRIVE_PINGROUP(XM2C, 0x8c8),
|
||||
DRIVE_PINGROUP(XM2D, 0x8cc),
|
||||
DRIVE_PINGROUP(XM2CLK, 0x8d0),
|
||||
DRIVE_PINGROUP(MEMCOMP, 0x8d4),
|
||||
DRIVE_PINGROUP(SDIO1, 0x8e0),
|
||||
DRIVE_PINGROUP(CRT, 0x8ec),
|
||||
DRIVE_PINGROUP(DDC, 0x8f0),
|
||||
DRIVE_PINGROUP(GMA, 0x8f4),
|
||||
DRIVE_PINGROUP(GMB, 0x8f8),
|
||||
DRIVE_PINGROUP(GMC, 0x8fc),
|
||||
DRIVE_PINGROUP(GMD, 0x900),
|
||||
DRIVE_PINGROUP(GME, 0x904),
|
||||
DRIVE_PINGROUP(OWR, 0x908),
|
||||
DRIVE_PINGROUP(UAD, 0x90c),
|
||||
};
|
||||
|
||||
#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, f_safe, \
|
||||
tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \
|
||||
[TEGRA_PINGROUP_ ## pg_name] = { \
|
||||
.name = #pg_name, \
|
||||
.vddio = TEGRA_VDDIO_ ## vdd, \
|
||||
.funcs = { \
|
||||
TEGRA_MUX_ ## f0, \
|
||||
TEGRA_MUX_ ## f1, \
|
||||
TEGRA_MUX_ ## f2, \
|
||||
TEGRA_MUX_ ## f3, \
|
||||
}, \
|
||||
.func_safe = TEGRA_MUX_ ## f_safe, \
|
||||
.tri_bank = 0, \
|
||||
.tri_reg = ((tri_r) - TRISTATE_REG_A), \
|
||||
.tri_bit = tri_b, \
|
||||
.mux_bank = 1, \
|
||||
.mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
|
||||
.mux_bit = mux_b, \
|
||||
.pupd_bank = 2, \
|
||||
.pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
|
||||
.pupd_bit = pupd_b, \
|
||||
.lock_bit = -1, \
|
||||
.od_bit = -1, \
|
||||
.ioreset_bit = -1, \
|
||||
.io_default = -1, \
|
||||
}
|
||||
|
||||
static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
|
||||
PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0),
|
||||
PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2),
|
||||
PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4),
|
||||
PINGROUP(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 3, 0x80, 20, 0xA0, 6),
|
||||
PINGROUP(ATE, NAND, IDE, NAND, GMI, RSVD, IDE, 0x18, 25, 0x80, 12, 0xA0, 8),
|
||||
PINGROUP(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC, 0x14, 4, 0x88, 2, 0xA8, 0),
|
||||
PINGROUP(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC, 0x14, 5, 0x88, 4, 0xA8, 2),
|
||||
PINGROUP(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD, 0x20, 14, 0x98, 20, 0xA4, 24),
|
||||
PINGROUP(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6, 0x88, 6, 0xAC, 24),
|
||||
PINGROUP(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1, 0x14, 7, 0x88, 20, 0xA0, 10),
|
||||
PINGROUP(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2, 0x14, 8, 0x88, 22, 0xA0, 12),
|
||||
PINGROUP(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3, 0x14, 9, 0x88, 24, 0xA0, 14),
|
||||
PINGROUP(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4, 0x14, 10, 0x88, 26, 0xA0, 16),
|
||||
PINGROUP(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4, 0x18, 31, 0x88, 0, 0xB0, 28),
|
||||
PINGROUP(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4, 0x14, 11, 0x84, 20, 0xA0, 18),
|
||||
PINGROUP(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 12, 0x84, 22, 0xA0, 20),
|
||||
PINGROUP(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1, 0x14, 13, 0x84, 26, 0xA0, 22),
|
||||
PINGROUP(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1, 0x14, 14, 0x84, 28, 0xA0, 24),
|
||||
PINGROUP(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 15, 0x84, 30, 0xA0, 26),
|
||||
PINGROUP(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4, 0x20, 12, 0x98, 30, 0xA0, 28),
|
||||
PINGROUP(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3, 0x14, 28, 0x84, 0, 0xB0, 20),
|
||||
PINGROUP(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI, 0x18, 29, 0x88, 28, 0xB0, 22),
|
||||
PINGROUP(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4, 0x14, 29, 0x84, 2, 0xB0, 24),
|
||||
PINGROUP(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI, 0x18, 30, 0x88, 30, 0xB0, 26),
|
||||
PINGROUP(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI, 0x18, 0, 0x8C, 0, 0xA8, 24),
|
||||
PINGROUP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4, 0x14, 16, 0x8C, 4, 0xA4, 20),
|
||||
PINGROUP(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK, 0x20, 11, 0x98, 28, 0xA4, 6),
|
||||
PINGROUP(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE, 0x14, 17, 0x8C, 2, 0xA0, 30),
|
||||
PINGROUP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI, 0x1C, 23, 0x84, 4, 0xAC, 22),
|
||||
PINGROUP(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 18, 0x88, 8, 0xA4, 2),
|
||||
PINGROUP(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 20, 0x88, 18, 0xA8, 22),
|
||||
PINGROUP(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 19, 0x88, 16, 0xA8, 20),
|
||||
PINGROUP(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC, 0x14, 22, 0x88, 10, 0xA4, 8),
|
||||
PINGROUP(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x14, 21, 0x88, 12, 0xA4, 10),
|
||||
PINGROUP(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC, 0x18, 26, 0x88, 14, 0xA4, 12),
|
||||
PINGROUP(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x20, 10, 0x98, 26, 0xA4, 14),
|
||||
PINGROUP(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC, 0x14, 26, 0x80, 28, 0xB0, 2),
|
||||
PINGROUP(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC, 0x14, 27, 0x80, 26, 0xB0, 0),
|
||||
PINGROUP(LCSN, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 31, 0x90, 12, 0xAC, 20),
|
||||
PINGROUP(LD0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 0, 0x94, 0, 0xAC, 12),
|
||||
PINGROUP(LD1, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 1, 0x94, 2, 0xAC, 12),
|
||||
PINGROUP(LD10, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 10, 0x94, 20, 0xAC, 12),
|
||||
PINGROUP(LD11, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 11, 0x94, 22, 0xAC, 12),
|
||||
PINGROUP(LD12, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 12, 0x94, 24, 0xAC, 12),
|
||||
PINGROUP(LD13, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 13, 0x94, 26, 0xAC, 12),
|
||||
PINGROUP(LD14, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 14, 0x94, 28, 0xAC, 12),
|
||||
PINGROUP(LD15, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 15, 0x94, 30, 0xAC, 12),
|
||||
PINGROUP(LD16, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 16, 0x98, 0, 0xAC, 12),
|
||||
PINGROUP(LD17, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 17, 0x98, 2, 0xAC, 12),
|
||||
PINGROUP(LD2, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 2, 0x94, 4, 0xAC, 12),
|
||||
PINGROUP(LD3, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 3, 0x94, 6, 0xAC, 12),
|
||||
PINGROUP(LD4, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 4, 0x94, 8, 0xAC, 12),
|
||||
PINGROUP(LD5, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 5, 0x94, 10, 0xAC, 12),
|
||||
PINGROUP(LD6, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 6, 0x94, 12, 0xAC, 12),
|
||||
PINGROUP(LD7, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 7, 0x94, 14, 0xAC, 12),
|
||||
PINGROUP(LD8, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 8, 0x94, 16, 0xAC, 12),
|
||||
PINGROUP(LD9, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 9, 0x94, 18, 0xAC, 12),
|
||||
PINGROUP(LDC, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 30, 0x90, 14, 0xAC, 20),
|
||||
PINGROUP(LDI, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 6, 0x98, 16, 0xAC, 18),
|
||||
PINGROUP(LHP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 18, 0x98, 10, 0xAC, 16),
|
||||
PINGROUP(LHP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 19, 0x98, 4, 0xAC, 14),
|
||||
PINGROUP(LHP2, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 20, 0x98, 6, 0xAC, 14),
|
||||
PINGROUP(LHS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x20, 7, 0x90, 22, 0xAC, 22),
|
||||
PINGROUP(LM0, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 24, 0x90, 26, 0xAC, 22),
|
||||
PINGROUP(LM1, LCD, DISPLAYA, DISPLAYB, RSVD, CRT, RSVD3, 0x1C, 25, 0x90, 28, 0xAC, 22),
|
||||
PINGROUP(LPP, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 8, 0x98, 14, 0xAC, 18),
|
||||
PINGROUP(LPW0, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 3, 0x90, 0, 0xAC, 20),
|
||||
PINGROUP(LPW1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 4, 0x90, 2, 0xAC, 20),
|
||||
PINGROUP(LPW2, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 5, 0x90, 4, 0xAC, 20),
|
||||
PINGROUP(LSC0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 27, 0x90, 18, 0xAC, 22),
|
||||
PINGROUP(LSC1, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 28, 0x90, 20, 0xAC, 20),
|
||||
PINGROUP(LSCK, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 29, 0x90, 16, 0xAC, 20),
|
||||
PINGROUP(LSDA, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 1, 0x90, 8, 0xAC, 20),
|
||||
PINGROUP(LSDI, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, DISPLAYA, 0x20, 2, 0x90, 6, 0xAC, 20),
|
||||
PINGROUP(LSPI, LCD, DISPLAYA, DISPLAYB, XIO, HDMI, DISPLAYA, 0x20, 0, 0x90, 10, 0xAC, 22),
|
||||
PINGROUP(LVP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 21, 0x90, 30, 0xAC, 22),
|
||||
PINGROUP(LVP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 22, 0x98, 8, 0xAC, 16),
|
||||
PINGROUP(LVS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 26, 0x90, 24, 0xAC, 22),
|
||||
PINGROUP(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR, 0x14, 31, 0x84, 8, 0xB0, 30),
|
||||
PINGROUP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, 0x14, 23, 0x98, 18, -1, -1),
|
||||
PINGROUP(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4, 0x14, 24, 0x98, 22, 0xA4, 4),
|
||||
PINGROUP(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 25, 0x80, 14, 0xA4, 0),
|
||||
PINGROUP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, 0x20, 15, 0x8C, 10, -1, -1),
|
||||
PINGROUP(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC, 0x18, 1, 0x8C, 12, 0xAC, 28),
|
||||
PINGROUP(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM, 0x18, 2, 0x8C, 14, 0xAC, 30),
|
||||
PINGROUP(SDIO1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2, 0x14, 30, 0x80, 30, 0xB0, 18),
|
||||
PINGROUP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 3, 0x84, 6, 0xA4, 22),
|
||||
PINGROUP(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 5, 0x84, 10, 0xA4, 26),
|
||||
PINGROUP(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 6, 0x84, 12, 0xA4, 28),
|
||||
PINGROUP(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 7, 0x84, 14, 0xA4, 30),
|
||||
PINGROUP(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 8, 0x8C, 8, 0xA4, 16),
|
||||
PINGROUP(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 9, 0x8C, 6, 0xA4, 18),
|
||||
PINGROUP(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 10, 0x8C, 30, 0xA8, 4),
|
||||
PINGROUP(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 11, 0x8C, 28, 0xA8, 6),
|
||||
PINGROUP(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 12, 0x8C, 26, 0xA8, 8),
|
||||
PINGROUP(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 13, 0x8C, 24, 0xA8, 10),
|
||||
PINGROUP(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 14, 0x8C, 22, 0xA8, 12),
|
||||
PINGROUP(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4, 0x18, 15, 0x8C, 20, 0xA8, 14),
|
||||
PINGROUP(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 16, 0x8C, 18, 0xA8, 16),
|
||||
PINGROUP(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 17, 0x8C, 16, 0xA8, 18),
|
||||
PINGROUP(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 18, 0x80, 0, 0xAC, 0),
|
||||
PINGROUP(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 19, 0x80, 2, 0xAC, 2),
|
||||
PINGROUP(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4, 0x18, 20, 0x80, 4, 0xAC, 4),
|
||||
PINGROUP(UAD, UART, IRDA, SPDIF, UARTA, SPI4, SPDIF, 0x18, 21, 0x80, 6, 0xAC, 6),
|
||||
PINGROUP(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4, 0x18, 22, 0x84, 16, 0xAC, 8),
|
||||
PINGROUP(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4, 0x18, 23, 0x84, 18, 0xAC, 10),
|
||||
PINGROUP(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2, 0x20, 13, 0x80, 8, 0xB0, 16),
|
||||
/* these pin groups only have pullup and pull down control */
|
||||
PINGROUP(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 14),
|
||||
PINGROUP(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xAC, 26),
|
||||
PINGROUP(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 4),
|
||||
PINGROUP(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 6),
|
||||
PINGROUP(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 8),
|
||||
PINGROUP(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 10),
|
||||
PINGROUP(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 12),
|
||||
PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30),
|
||||
PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28),
|
||||
};
|
||||
|
||||
void __devinit tegra20_pinmux_init(const struct tegra_pingroup_desc **pg,
|
||||
int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
|
||||
int *pgdrive_max)
|
||||
{
|
||||
*pg = tegra_soc_pingroups;
|
||||
*pg_max = TEGRA_MAX_PINGROUP;
|
||||
*pgdrive = tegra_soc_drive_pingroups;
|
||||
*pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
|
||||
}
|
||||
|
||||
|
|
@ -1,376 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-tegra/pinmux-tegra30-tables.c
|
||||
*
|
||||
* Common pinmux configurations for Tegra30 SoCs
|
||||
*
|
||||
* Copyright (C) 2010,2011 NVIDIA Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
#include <mach/pinmux.h>
|
||||
#include <mach/pinmux-tegra30.h>
|
||||
#include <mach/suspend.h>
|
||||
|
||||
#define PINGROUP_REG_A 0x868
|
||||
#define MUXCTL_REG_A 0x3000
|
||||
|
||||
#define DRIVE_PINGROUP(pg_name, r) \
|
||||
[TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
|
||||
.name = #pg_name, \
|
||||
.reg_bank = 0, \
|
||||
.reg = ((r) - PINGROUP_REG_A) \
|
||||
}
|
||||
|
||||
static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
|
||||
DRIVE_PINGROUP(AO1, 0x868),
|
||||
DRIVE_PINGROUP(AO2, 0x86c),
|
||||
DRIVE_PINGROUP(AT1, 0x870),
|
||||
DRIVE_PINGROUP(AT2, 0x874),
|
||||
DRIVE_PINGROUP(AT3, 0x878),
|
||||
DRIVE_PINGROUP(AT4, 0x87c),
|
||||
DRIVE_PINGROUP(AT5, 0x880),
|
||||
DRIVE_PINGROUP(CDEV1, 0x884),
|
||||
DRIVE_PINGROUP(CDEV2, 0x888),
|
||||
DRIVE_PINGROUP(CSUS, 0x88c),
|
||||
DRIVE_PINGROUP(DAP1, 0x890),
|
||||
DRIVE_PINGROUP(DAP2, 0x894),
|
||||
DRIVE_PINGROUP(DAP3, 0x898),
|
||||
DRIVE_PINGROUP(DAP4, 0x89c),
|
||||
DRIVE_PINGROUP(DBG, 0x8a0),
|
||||
DRIVE_PINGROUP(LCD1, 0x8a4),
|
||||
DRIVE_PINGROUP(LCD2, 0x8a8),
|
||||
DRIVE_PINGROUP(SDIO2, 0x8ac),
|
||||
DRIVE_PINGROUP(SDIO3, 0x8b0),
|
||||
DRIVE_PINGROUP(SPI, 0x8b4),
|
||||
DRIVE_PINGROUP(UAA, 0x8b8),
|
||||
DRIVE_PINGROUP(UAB, 0x8bc),
|
||||
DRIVE_PINGROUP(UART2, 0x8c0),
|
||||
DRIVE_PINGROUP(UART3, 0x8c4),
|
||||
DRIVE_PINGROUP(VI1, 0x8c8),
|
||||
DRIVE_PINGROUP(SDIO1, 0x8ec),
|
||||
DRIVE_PINGROUP(CRT, 0x8f8),
|
||||
DRIVE_PINGROUP(DDC, 0x8fc),
|
||||
DRIVE_PINGROUP(GMA, 0x900),
|
||||
DRIVE_PINGROUP(GMB, 0x904),
|
||||
DRIVE_PINGROUP(GMC, 0x908),
|
||||
DRIVE_PINGROUP(GMD, 0x90c),
|
||||
DRIVE_PINGROUP(GME, 0x910),
|
||||
DRIVE_PINGROUP(GMF, 0x914),
|
||||
DRIVE_PINGROUP(GMG, 0x918),
|
||||
DRIVE_PINGROUP(GMH, 0x91c),
|
||||
DRIVE_PINGROUP(OWR, 0x920),
|
||||
DRIVE_PINGROUP(UAD, 0x924),
|
||||
DRIVE_PINGROUP(GPV, 0x928),
|
||||
DRIVE_PINGROUP(DEV3, 0x92c),
|
||||
DRIVE_PINGROUP(CEC, 0x938),
|
||||
};
|
||||
|
||||
#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, fs, iod, reg) \
|
||||
[TEGRA_PINGROUP_ ## pg_name] = { \
|
||||
.name = #pg_name, \
|
||||
.vddio = TEGRA_VDDIO_ ## vdd, \
|
||||
.funcs = { \
|
||||
TEGRA_MUX_ ## f0, \
|
||||
TEGRA_MUX_ ## f1, \
|
||||
TEGRA_MUX_ ## f2, \
|
||||
TEGRA_MUX_ ## f3, \
|
||||
}, \
|
||||
.func_safe = TEGRA_MUX_ ## fs, \
|
||||
.tri_bank = 1, \
|
||||
.tri_reg = ((reg) - MUXCTL_REG_A), \
|
||||
.tri_bit = 4, \
|
||||
.mux_bank = 1, \
|
||||
.mux_reg = ((reg) - MUXCTL_REG_A), \
|
||||
.mux_bit = 0, \
|
||||
.pupd_bank = 1, \
|
||||
.pupd_reg = ((reg) - MUXCTL_REG_A), \
|
||||
.pupd_bit = 2, \
|
||||
.io_default = TEGRA_PIN_ ## iod, \
|
||||
.od_bit = 6, \
|
||||
.lock_bit = 7, \
|
||||
.ioreset_bit = 8, \
|
||||
}
|
||||
|
||||
static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
|
||||
/* NAME VDD f0 f1 f2 f3 fSafe io reg */
|
||||
PINGROUP(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3000),
|
||||
PINGROUP(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3004),
|
||||
PINGROUP(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3008),
|
||||
PINGROUP(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x300c),
|
||||
PINGROUP(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3010),
|
||||
PINGROUP(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3014),
|
||||
PINGROUP(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3018),
|
||||
PINGROUP(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x301c),
|
||||
PINGROUP(ULPI_CLK, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3020),
|
||||
PINGROUP(ULPI_DIR, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3024),
|
||||
PINGROUP(ULPI_NXT, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3028),
|
||||
PINGROUP(ULPI_STP, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x302c),
|
||||
PINGROUP(DAP3_FS, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3030),
|
||||
PINGROUP(DAP3_DIN, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3034),
|
||||
PINGROUP(DAP3_DOUT, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3038),
|
||||
PINGROUP(DAP3_SCLK, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x303c),
|
||||
PINGROUP(GPIO_PV0, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3040),
|
||||
PINGROUP(GPIO_PV1, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3044),
|
||||
PINGROUP(SDMMC1_CLK, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x3048),
|
||||
PINGROUP(SDMMC1_CMD, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x304c),
|
||||
PINGROUP(SDMMC1_DAT3, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3050),
|
||||
PINGROUP(SDMMC1_DAT2, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3054),
|
||||
PINGROUP(SDMMC1_DAT1, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3058),
|
||||
PINGROUP(SDMMC1_DAT0, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x305c),
|
||||
PINGROUP(GPIO_PV2, SDMMC1, OWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3060),
|
||||
PINGROUP(GPIO_PV3, SDMMC1, INVALID, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3064),
|
||||
PINGROUP(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3068),
|
||||
PINGROUP(CLK2_REQ, SDMMC1, DAP, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x306c),
|
||||
PINGROUP(LCD_PWR1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3070),
|
||||
PINGROUP(LCD_PWR2, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3074),
|
||||
PINGROUP(LCD_SDIN, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3078),
|
||||
PINGROUP(LCD_SDOUT, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x307c),
|
||||
PINGROUP(LCD_WR_N, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3080),
|
||||
PINGROUP(LCD_CS0_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3084),
|
||||
PINGROUP(LCD_DC0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3088),
|
||||
PINGROUP(LCD_SCK, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x308c),
|
||||
PINGROUP(LCD_PWR0, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3090),
|
||||
PINGROUP(LCD_PCLK, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3094),
|
||||
PINGROUP(LCD_DE, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3098),
|
||||
PINGROUP(LCD_HSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x309c),
|
||||
PINGROUP(LCD_VSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a0),
|
||||
PINGROUP(LCD_D0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a4),
|
||||
PINGROUP(LCD_D1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a8),
|
||||
PINGROUP(LCD_D2, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ac),
|
||||
PINGROUP(LCD_D3, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b0),
|
||||
PINGROUP(LCD_D4, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b4),
|
||||
PINGROUP(LCD_D5, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b8),
|
||||
PINGROUP(LCD_D6, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30bc),
|
||||
PINGROUP(LCD_D7, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c0),
|
||||
PINGROUP(LCD_D8, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c4),
|
||||
PINGROUP(LCD_D9, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c8),
|
||||
PINGROUP(LCD_D10, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30cc),
|
||||
PINGROUP(LCD_D11, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d0),
|
||||
PINGROUP(LCD_D12, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d4),
|
||||
PINGROUP(LCD_D13, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d8),
|
||||
PINGROUP(LCD_D14, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30dc),
|
||||
PINGROUP(LCD_D15, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e0),
|
||||
PINGROUP(LCD_D16, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e4),
|
||||
PINGROUP(LCD_D17, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e8),
|
||||
PINGROUP(LCD_D18, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ec),
|
||||
PINGROUP(LCD_D19, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f0),
|
||||
PINGROUP(LCD_D20, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f4),
|
||||
PINGROUP(LCD_D21, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f8),
|
||||
PINGROUP(LCD_D22, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30fc),
|
||||
PINGROUP(LCD_D23, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3100),
|
||||
PINGROUP(LCD_CS1_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD2, RSVD, OUTPUT, 0x3104),
|
||||
PINGROUP(LCD_M1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3108),
|
||||
PINGROUP(LCD_DC1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x310c),
|
||||
PINGROUP(HDMI_INT, LCD, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3110),
|
||||
PINGROUP(DDC_SCL, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3114),
|
||||
PINGROUP(DDC_SDA, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3118),
|
||||
PINGROUP(CRT_HSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x311c),
|
||||
PINGROUP(CRT_VSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3120),
|
||||
PINGROUP(VI_D0, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3124),
|
||||
PINGROUP(VI_D1, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3128),
|
||||
PINGROUP(VI_D2, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x312c),
|
||||
PINGROUP(VI_D3, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3130),
|
||||
PINGROUP(VI_D4, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3134),
|
||||
PINGROUP(VI_D5, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3138),
|
||||
PINGROUP(VI_D6, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x313c),
|
||||
PINGROUP(VI_D7, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3140),
|
||||
PINGROUP(VI_D8, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3144),
|
||||
PINGROUP(VI_D9, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3148),
|
||||
PINGROUP(VI_D10, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x314c),
|
||||
PINGROUP(VI_D11, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3150),
|
||||
PINGROUP(VI_PCLK, VI, RSVD1, SDIO2, VI, RSVD2, RSVD, INPUT, 0x3154),
|
||||
PINGROUP(VI_MCLK, VI, VI, INVALID, INVALID, INVALID, RSVD, INPUT, 0x3158),
|
||||
PINGROUP(VI_VSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x315c),
|
||||
PINGROUP(VI_HSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3160),
|
||||
PINGROUP(UART2_RXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3164),
|
||||
PINGROUP(UART2_TXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3168),
|
||||
PINGROUP(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x316c),
|
||||
PINGROUP(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x3170),
|
||||
PINGROUP(UART3_TXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3174),
|
||||
PINGROUP(UART3_RXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3178),
|
||||
PINGROUP(UART3_CTS_N, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x317c),
|
||||
PINGROUP(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD2, RSVD, INPUT, 0x3180),
|
||||
PINGROUP(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3184),
|
||||
PINGROUP(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x3188),
|
||||
PINGROUP(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x318c),
|
||||
PINGROUP(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3190),
|
||||
PINGROUP(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3194),
|
||||
PINGROUP(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3198),
|
||||
PINGROUP(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD1, RSVD, INPUT, 0x319c),
|
||||
PINGROUP(GEN1_I2C_SDA, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a0),
|
||||
PINGROUP(GEN1_I2C_SCL, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a4),
|
||||
PINGROUP(DAP4_FS, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31a8),
|
||||
PINGROUP(DAP4_DIN, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31ac),
|
||||
PINGROUP(DAP4_DOUT, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b0),
|
||||
PINGROUP(DAP4_SCLK, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b4),
|
||||
PINGROUP(CLK3_OUT, UART, EXTPERIPH3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31b8),
|
||||
PINGROUP(CLK3_REQ, UART, DEV3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31bc),
|
||||
PINGROUP(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31c0),
|
||||
PINGROUP(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c4),
|
||||
PINGROUP(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c8),
|
||||
PINGROUP(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31cc),
|
||||
PINGROUP(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31d0),
|
||||
PINGROUP(GMI_CS0_N, GMI, RSVD1, NAND, GMI, INVALID, RSVD, INPUT, 0x31d4),
|
||||
PINGROUP(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV, RSVD, INPUT, 0x31d8),
|
||||
PINGROUP(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31dc),
|
||||
PINGROUP(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31e0),
|
||||
PINGROUP(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31e4),
|
||||
PINGROUP(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA, RSVD, INPUT, 0x31e8),
|
||||
PINGROUP(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT, RSVD, INPUT, 0x31ec),
|
||||
PINGROUP(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f0),
|
||||
PINGROUP(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f4),
|
||||
PINGROUP(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f8),
|
||||
PINGROUP(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31fc),
|
||||
PINGROUP(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3200),
|
||||
PINGROUP(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3204),
|
||||
PINGROUP(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3208),
|
||||
PINGROUP(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x320c),
|
||||
PINGROUP(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD2, RSVD, INPUT, 0x3210),
|
||||
PINGROUP(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3214),
|
||||
PINGROUP(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD2, RSVD, INPUT, 0x3218),
|
||||
PINGROUP(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD2, RSVD, INPUT, 0x321c),
|
||||
PINGROUP(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3220),
|
||||
PINGROUP(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3224),
|
||||
PINGROUP(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3228),
|
||||
PINGROUP(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x322c),
|
||||
PINGROUP(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT, RSVD, INPUT, 0x3230),
|
||||
PINGROUP(GMI_A17, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3234),
|
||||
PINGROUP(GMI_A18, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3238),
|
||||
PINGROUP(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD3, RSVD, INPUT, 0x323c),
|
||||
PINGROUP(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3240),
|
||||
PINGROUP(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3244),
|
||||
PINGROUP(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3248),
|
||||
PINGROUP(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD3, RSVD, INPUT, 0x324c),
|
||||
PINGROUP(GEN2_I2C_SCL, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3250),
|
||||
PINGROUP(GEN2_I2C_SDA, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3254),
|
||||
PINGROUP(SDMMC4_CLK, SDMMC4, INVALID, NAND, GMI, SDIO4, RSVD, INPUT, 0x3258),
|
||||
PINGROUP(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDIO4, RSVD, INPUT, 0x325c),
|
||||
PINGROUP(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3260),
|
||||
PINGROUP(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3264),
|
||||
PINGROUP(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3268),
|
||||
PINGROUP(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x326c),
|
||||
PINGROUP(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3270),
|
||||
PINGROUP(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3274),
|
||||
PINGROUP(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3278),
|
||||
PINGROUP(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDIO4, RSVD, INPUT, 0x327c),
|
||||
PINGROUP(SDMMC4_RST_N, SDMMC4, VGP6, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3280),
|
||||
PINGROUP(CAM_MCLK, CAM, VI, INVALID, VI_ALT2, POPSDMMC4, RSVD, INPUT, 0x3284),
|
||||
PINGROUP(GPIO_PCC1, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3288),
|
||||
PINGROUP(GPIO_PBB0, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x328c),
|
||||
PINGROUP(CAM_I2C_SCL, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3290),
|
||||
PINGROUP(CAM_I2C_SDA, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3294),
|
||||
PINGROUP(GPIO_PBB3, CAM, VGP3, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x3298),
|
||||
PINGROUP(GPIO_PBB4, CAM, VGP4, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x329c),
|
||||
PINGROUP(GPIO_PBB5, CAM, VGP5, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a0),
|
||||
PINGROUP(GPIO_PBB6, CAM, VGP6, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a4),
|
||||
PINGROUP(GPIO_PBB7, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x32a8),
|
||||
PINGROUP(GPIO_PCC2, CAM, I2S4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32ac),
|
||||
PINGROUP(JTAG_RTCK, SYS, RTCK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b0),
|
||||
PINGROUP(PWR_I2C_SCL, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b4),
|
||||
PINGROUP(PWR_I2C_SDA, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b8),
|
||||
PINGROUP(KB_ROW0, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32bc),
|
||||
PINGROUP(KB_ROW1, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c0),
|
||||
PINGROUP(KB_ROW2, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c4),
|
||||
PINGROUP(KB_ROW3, SYS, KBC, INVALID, RSVD2, INVALID, RSVD, INPUT, 0x32c8),
|
||||
PINGROUP(KB_ROW4, SYS, KBC, INVALID, TRACE, RSVD3, RSVD, INPUT, 0x32cc),
|
||||
PINGROUP(KB_ROW5, SYS, KBC, INVALID, TRACE, OWR, RSVD, INPUT, 0x32d0),
|
||||
PINGROUP(KB_ROW6, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d4),
|
||||
PINGROUP(KB_ROW7, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d8),
|
||||
PINGROUP(KB_ROW8, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32dc),
|
||||
PINGROUP(KB_ROW9, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e0),
|
||||
PINGROUP(KB_ROW10, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e4),
|
||||
PINGROUP(KB_ROW11, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e8),
|
||||
PINGROUP(KB_ROW12, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32ec),
|
||||
PINGROUP(KB_ROW13, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f0),
|
||||
PINGROUP(KB_ROW14, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f4),
|
||||
PINGROUP(KB_ROW15, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f8),
|
||||
PINGROUP(KB_COL0, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x32fc),
|
||||
PINGROUP(KB_COL1, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3300),
|
||||
PINGROUP(KB_COL2, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3304),
|
||||
PINGROUP(KB_COL3, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3308),
|
||||
PINGROUP(KB_COL4, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x330c),
|
||||
PINGROUP(KB_COL5, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3310),
|
||||
PINGROUP(KB_COL6, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3314),
|
||||
PINGROUP(KB_COL7, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3318),
|
||||
PINGROUP(CLK_32K_OUT, SYS, BLINK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x331c),
|
||||
PINGROUP(SYS_CLK_REQ, SYS, SYSCLK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3320),
|
||||
PINGROUP(CORE_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3324),
|
||||
PINGROUP(CPU_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3328),
|
||||
PINGROUP(PWR_INT_N, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x332c),
|
||||
PINGROUP(CLK_32K_IN, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3330),
|
||||
PINGROUP(OWR, SYS, OWR, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3334),
|
||||
PINGROUP(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3338),
|
||||
PINGROUP(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x333c),
|
||||
PINGROUP(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3340),
|
||||
PINGROUP(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3344),
|
||||
PINGROUP(CLK1_REQ, AUDIO, DAP, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x3348),
|
||||
PINGROUP(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x334c),
|
||||
PINGROUP(SPDIF_IN, AUDIO, SPDIF, HDA, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3350),
|
||||
PINGROUP(SPDIF_OUT, AUDIO, SPDIF, RSVD1, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3354),
|
||||
PINGROUP(DAP2_FS, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3358),
|
||||
PINGROUP(DAP2_DIN, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x335c),
|
||||
PINGROUP(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3360),
|
||||
PINGROUP(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3364),
|
||||
PINGROUP(SPI2_MOSI, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3368),
|
||||
PINGROUP(SPI2_MISO, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x336c),
|
||||
PINGROUP(SPI2_CS0_N, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3370),
|
||||
PINGROUP(SPI2_SCK, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3374),
|
||||
PINGROUP(SPI1_MOSI, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3378),
|
||||
PINGROUP(SPI1_SCK, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x337c),
|
||||
PINGROUP(SPI1_CS0_N, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3380),
|
||||
PINGROUP(SPI1_MISO, AUDIO, INVALID, SPI1, INVALID, RSVD3, RSVD, INPUT, 0x3384),
|
||||
PINGROUP(SPI2_CS1_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x3388),
|
||||
PINGROUP(SPI2_CS2_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x338c),
|
||||
PINGROUP(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDIO3, INVALID, RSVD, INPUT, 0x3390),
|
||||
PINGROUP(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDIO3, INVALID, RSVD, INPUT, 0x3394),
|
||||
PINGROUP(SDMMC3_DAT0, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x3398),
|
||||
PINGROUP(SDMMC3_DAT1, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x339c),
|
||||
PINGROUP(SDMMC3_DAT2, SDMMC3, RSVD, PWM1, SDIO3, INVALID, RSVD, INPUT, 0x33a0),
|
||||
PINGROUP(SDMMC3_DAT3, SDMMC3, RSVD, PWM0, SDIO3, INVALID, RSVD, INPUT, 0x33a4),
|
||||
PINGROUP(SDMMC3_DAT4, SDMMC3, PWM1, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33a8),
|
||||
PINGROUP(SDMMC3_DAT5, SDMMC3, PWM0, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33ac),
|
||||
PINGROUP(SDMMC3_DAT6, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b0),
|
||||
PINGROUP(SDMMC3_DAT7, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b4),
|
||||
PINGROUP(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33b8),
|
||||
PINGROUP(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33bc),
|
||||
PINGROUP(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c0),
|
||||
PINGROUP(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c4),
|
||||
PINGROUP(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c8),
|
||||
PINGROUP(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33cc),
|
||||
PINGROUP(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d0),
|
||||
PINGROUP(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d4),
|
||||
PINGROUP(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d8),
|
||||
PINGROUP(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33dc),
|
||||
PINGROUP(HDMI_CEC, SYS, CEC, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x33e0),
|
||||
};
|
||||
|
||||
void __devinit tegra30_pinmux_init(const struct tegra_pingroup_desc **pg,
|
||||
int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
|
||||
int *pgdrive_max)
|
||||
{
|
||||
*pg = tegra_soc_pingroups;
|
||||
*pg_max = TEGRA_MAX_PINGROUP;
|
||||
*pgdrive = tegra_soc_drive_pingroups;
|
||||
*pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
|
||||
}
|
||||
|
||||
|
|
@ -1,987 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-tegra/pinmux.c
|
||||
*
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of_device.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
#include <mach/pinmux.h>
|
||||
|
||||
#define HSM_EN(reg) (((reg) >> 2) & 0x1)
|
||||
#define SCHMT_EN(reg) (((reg) >> 3) & 0x1)
|
||||
#define LPMD(reg) (((reg) >> 4) & 0x3)
|
||||
#define DRVDN(reg) (((reg) >> 12) & 0x1f)
|
||||
#define DRVUP(reg) (((reg) >> 20) & 0x1f)
|
||||
#define SLWR(reg) (((reg) >> 28) & 0x3)
|
||||
#define SLWF(reg) (((reg) >> 30) & 0x3)
|
||||
|
||||
static const struct tegra_pingroup_desc *pingroups;
|
||||
static const struct tegra_drive_pingroup_desc *drive_pingroups;
|
||||
static int pingroup_max;
|
||||
static int drive_max;
|
||||
|
||||
static char *tegra_mux_names[TEGRA_MAX_MUX] = {
|
||||
[TEGRA_MUX_AHB_CLK] = "AHB_CLK",
|
||||
[TEGRA_MUX_APB_CLK] = "APB_CLK",
|
||||
[TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC",
|
||||
[TEGRA_MUX_CRT] = "CRT",
|
||||
[TEGRA_MUX_DAP1] = "DAP1",
|
||||
[TEGRA_MUX_DAP2] = "DAP2",
|
||||
[TEGRA_MUX_DAP3] = "DAP3",
|
||||
[TEGRA_MUX_DAP4] = "DAP4",
|
||||
[TEGRA_MUX_DAP5] = "DAP5",
|
||||
[TEGRA_MUX_DISPLAYA] = "DISPLAYA",
|
||||
[TEGRA_MUX_DISPLAYB] = "DISPLAYB",
|
||||
[TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL",
|
||||
[TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL",
|
||||
[TEGRA_MUX_GMI] = "GMI",
|
||||
[TEGRA_MUX_GMI_INT] = "GMI_INT",
|
||||
[TEGRA_MUX_HDMI] = "HDMI",
|
||||
[TEGRA_MUX_I2C] = "I2C",
|
||||
[TEGRA_MUX_I2C2] = "I2C2",
|
||||
[TEGRA_MUX_I2C3] = "I2C3",
|
||||
[TEGRA_MUX_IDE] = "IDE",
|
||||
[TEGRA_MUX_IRDA] = "IRDA",
|
||||
[TEGRA_MUX_KBC] = "KBC",
|
||||
[TEGRA_MUX_MIO] = "MIO",
|
||||
[TEGRA_MUX_MIPI_HS] = "MIPI_HS",
|
||||
[TEGRA_MUX_NAND] = "NAND",
|
||||
[TEGRA_MUX_OSC] = "OSC",
|
||||
[TEGRA_MUX_OWR] = "OWR",
|
||||
[TEGRA_MUX_PCIE] = "PCIE",
|
||||
[TEGRA_MUX_PLLA_OUT] = "PLLA_OUT",
|
||||
[TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1",
|
||||
[TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1",
|
||||
[TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2",
|
||||
[TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3",
|
||||
[TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4",
|
||||
[TEGRA_MUX_PWM] = "PWM",
|
||||
[TEGRA_MUX_PWR_INTR] = "PWR_INTR",
|
||||
[TEGRA_MUX_PWR_ON] = "PWR_ON",
|
||||
[TEGRA_MUX_RTCK] = "RTCK",
|
||||
[TEGRA_MUX_SDIO1] = "SDIO1",
|
||||
[TEGRA_MUX_SDIO2] = "SDIO2",
|
||||
[TEGRA_MUX_SDIO3] = "SDIO3",
|
||||
[TEGRA_MUX_SDIO4] = "SDIO4",
|
||||
[TEGRA_MUX_SFLASH] = "SFLASH",
|
||||
[TEGRA_MUX_SPDIF] = "SPDIF",
|
||||
[TEGRA_MUX_SPI1] = "SPI1",
|
||||
[TEGRA_MUX_SPI2] = "SPI2",
|
||||
[TEGRA_MUX_SPI2_ALT] = "SPI2_ALT",
|
||||
[TEGRA_MUX_SPI3] = "SPI3",
|
||||
[TEGRA_MUX_SPI4] = "SPI4",
|
||||
[TEGRA_MUX_TRACE] = "TRACE",
|
||||
[TEGRA_MUX_TWC] = "TWC",
|
||||
[TEGRA_MUX_UARTA] = "UARTA",
|
||||
[TEGRA_MUX_UARTB] = "UARTB",
|
||||
[TEGRA_MUX_UARTC] = "UARTC",
|
||||
[TEGRA_MUX_UARTD] = "UARTD",
|
||||
[TEGRA_MUX_UARTE] = "UARTE",
|
||||
[TEGRA_MUX_ULPI] = "ULPI",
|
||||
[TEGRA_MUX_VI] = "VI",
|
||||
[TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
|
||||
[TEGRA_MUX_XIO] = "XIO",
|
||||
[TEGRA_MUX_BLINK] = "BLINK",
|
||||
[TEGRA_MUX_CEC] = "CEC",
|
||||
[TEGRA_MUX_CLK12] = "CLK12",
|
||||
[TEGRA_MUX_DAP] = "DAP",
|
||||
[TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2",
|
||||
[TEGRA_MUX_DDR] = "DDR",
|
||||
[TEGRA_MUX_DEV3] = "DEV3",
|
||||
[TEGRA_MUX_DTV] = "DTV",
|
||||
[TEGRA_MUX_VI_ALT1] = "VI_ALT1",
|
||||
[TEGRA_MUX_VI_ALT2] = "VI_ALT2",
|
||||
[TEGRA_MUX_VI_ALT3] = "VI_ALT3",
|
||||
[TEGRA_MUX_EMC_DLL] = "EMC_DLL",
|
||||
[TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1",
|
||||
[TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2",
|
||||
[TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3",
|
||||
[TEGRA_MUX_GMI_ALT] = "GMI_ALT",
|
||||
[TEGRA_MUX_HDA] = "HDA",
|
||||
[TEGRA_MUX_HSI] = "HSI",
|
||||
[TEGRA_MUX_I2C4] = "I2C4",
|
||||
[TEGRA_MUX_I2C5] = "I2C5",
|
||||
[TEGRA_MUX_I2CPWR] = "I2CPWR",
|
||||
[TEGRA_MUX_I2S0] = "I2S0",
|
||||
[TEGRA_MUX_I2S1] = "I2S1",
|
||||
[TEGRA_MUX_I2S2] = "I2S2",
|
||||
[TEGRA_MUX_I2S3] = "I2S3",
|
||||
[TEGRA_MUX_I2S4] = "I2S4",
|
||||
[TEGRA_MUX_NAND_ALT] = "NAND_ALT",
|
||||
[TEGRA_MUX_POPSDIO4] = "POPSDIO4",
|
||||
[TEGRA_MUX_POPSDMMC4] = "POPSDMMC4",
|
||||
[TEGRA_MUX_PWM0] = "PWM0",
|
||||
[TEGRA_MUX_PWM1] = "PWM2",
|
||||
[TEGRA_MUX_PWM2] = "PWM2",
|
||||
[TEGRA_MUX_PWM3] = "PWM3",
|
||||
[TEGRA_MUX_SATA] = "SATA",
|
||||
[TEGRA_MUX_SPI5] = "SPI5",
|
||||
[TEGRA_MUX_SPI6] = "SPI6",
|
||||
[TEGRA_MUX_SYSCLK] = "SYSCLK",
|
||||
[TEGRA_MUX_VGP1] = "VGP1",
|
||||
[TEGRA_MUX_VGP2] = "VGP2",
|
||||
[TEGRA_MUX_VGP3] = "VGP3",
|
||||
[TEGRA_MUX_VGP4] = "VGP4",
|
||||
[TEGRA_MUX_VGP5] = "VGP5",
|
||||
[TEGRA_MUX_VGP6] = "VGP6",
|
||||
[TEGRA_MUX_SAFE] = "<safe>",
|
||||
};
|
||||
|
||||
static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
|
||||
[TEGRA_DRIVE_DIV_8] = "DIV_8",
|
||||
[TEGRA_DRIVE_DIV_4] = "DIV_4",
|
||||
[TEGRA_DRIVE_DIV_2] = "DIV_2",
|
||||
[TEGRA_DRIVE_DIV_1] = "DIV_1",
|
||||
};
|
||||
|
||||
static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
|
||||
[TEGRA_SLEW_FASTEST] = "FASTEST",
|
||||
[TEGRA_SLEW_FAST] = "FAST",
|
||||
[TEGRA_SLEW_SLOW] = "SLOW",
|
||||
[TEGRA_SLEW_SLOWEST] = "SLOWEST",
|
||||
};
|
||||
|
||||
static DEFINE_SPINLOCK(mux_lock);
|
||||
|
||||
static const char *pingroup_name(int pg)
|
||||
{
|
||||
if (pg < 0 || pg >= pingroup_max)
|
||||
return "<UNKNOWN>";
|
||||
|
||||
return pingroups[pg].name;
|
||||
}
|
||||
|
||||
static const char *func_name(enum tegra_mux_func func)
|
||||
{
|
||||
if (func == TEGRA_MUX_RSVD1)
|
||||
return "RSVD1";
|
||||
|
||||
if (func == TEGRA_MUX_RSVD2)
|
||||
return "RSVD2";
|
||||
|
||||
if (func == TEGRA_MUX_RSVD3)
|
||||
return "RSVD3";
|
||||
|
||||
if (func == TEGRA_MUX_RSVD4)
|
||||
return "RSVD4";
|
||||
|
||||
if (func == TEGRA_MUX_NONE)
|
||||
return "NONE";
|
||||
|
||||
if (func < 0 || func >= TEGRA_MAX_MUX)
|
||||
return "<UNKNOWN>";
|
||||
|
||||
return tegra_mux_names[func];
|
||||
}
|
||||
|
||||
|
||||
static const char *tri_name(unsigned long val)
|
||||
{
|
||||
return val ? "TRISTATE" : "NORMAL";
|
||||
}
|
||||
|
||||
static const char *pupd_name(unsigned long val)
|
||||
{
|
||||
switch (val) {
|
||||
case 0:
|
||||
return "NORMAL";
|
||||
|
||||
case 1:
|
||||
return "PULL_DOWN";
|
||||
|
||||
case 2:
|
||||
return "PULL_UP";
|
||||
|
||||
default:
|
||||
return "RSVD";
|
||||
}
|
||||
}
|
||||
|
||||
static int nbanks;
|
||||
static void __iomem **regs;
|
||||
|
||||
static inline u32 pg_readl(u32 bank, u32 reg)
|
||||
{
|
||||
return readl(regs[bank] + reg);
|
||||
}
|
||||
|
||||
static inline void pg_writel(u32 val, u32 bank, u32 reg)
|
||||
{
|
||||
writel(val, regs[bank] + reg);
|
||||
}
|
||||
|
||||
static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
|
||||
{
|
||||
int mux = -1;
|
||||
int i;
|
||||
unsigned long reg;
|
||||
unsigned long flags;
|
||||
int pg = config->pingroup;
|
||||
enum tegra_mux_func func = config->func;
|
||||
|
||||
if (pg < 0 || pg >= pingroup_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (pingroups[pg].mux_reg < 0)
|
||||
return -EINVAL;
|
||||
|
||||
if (func < 0)
|
||||
return -ERANGE;
|
||||
|
||||
if (func == TEGRA_MUX_SAFE)
|
||||
func = pingroups[pg].func_safe;
|
||||
|
||||
if (func & TEGRA_MUX_RSVD) {
|
||||
mux = func & 0x3;
|
||||
} else {
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (pingroups[pg].funcs[i] == func) {
|
||||
mux = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (mux < 0)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
|
||||
reg &= ~(0x3 << pingroups[pg].mux_bit);
|
||||
reg |= mux << pingroups[pg].mux_bit;
|
||||
pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
|
||||
{
|
||||
unsigned long reg;
|
||||
unsigned long flags;
|
||||
|
||||
if (pg < 0 || pg >= pingroup_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (pingroups[pg].tri_reg < 0)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg);
|
||||
reg &= ~(0x1 << pingroups[pg].tri_bit);
|
||||
if (tristate)
|
||||
reg |= 1 << pingroups[pg].tri_bit;
|
||||
pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
|
||||
{
|
||||
unsigned long reg;
|
||||
unsigned long flags;
|
||||
|
||||
if (pg < 0 || pg >= pingroup_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (pingroups[pg].pupd_reg < 0)
|
||||
return -EINVAL;
|
||||
|
||||
if (pupd != TEGRA_PUPD_NORMAL &&
|
||||
pupd != TEGRA_PUPD_PULL_DOWN &&
|
||||
pupd != TEGRA_PUPD_PULL_UP)
|
||||
return -EINVAL;
|
||||
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
|
||||
reg &= ~(0x3 << pingroups[pg].pupd_bit);
|
||||
reg |= pupd << pingroups[pg].pupd_bit;
|
||||
pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
|
||||
{
|
||||
int pingroup = config->pingroup;
|
||||
enum tegra_mux_func func = config->func;
|
||||
enum tegra_pullupdown pupd = config->pupd;
|
||||
enum tegra_tristate tristate = config->tristate;
|
||||
int err;
|
||||
|
||||
if (pingroups[pingroup].mux_reg >= 0) {
|
||||
err = tegra_pinmux_set_func(config);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
|
||||
pingroup_name(pingroup), func_name(func), err);
|
||||
}
|
||||
|
||||
if (pingroups[pingroup].pupd_reg >= 0) {
|
||||
err = tegra_pinmux_set_pullupdown(pingroup, pupd);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
|
||||
pingroup_name(pingroup), pupd_name(pupd), err);
|
||||
}
|
||||
|
||||
if (pingroups[pingroup].tri_reg >= 0) {
|
||||
err = tegra_pinmux_set_tristate(pingroup, tristate);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
|
||||
pingroup_name(pingroup), tri_name(func), err);
|
||||
}
|
||||
}
|
||||
|
||||
void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
tegra_pinmux_config_pingroup(&config[i]);
|
||||
}
|
||||
|
||||
static const char *drive_pinmux_name(int pg)
|
||||
{
|
||||
if (pg < 0 || pg >= drive_max)
|
||||
return "<UNKNOWN>";
|
||||
|
||||
return drive_pingroups[pg].name;
|
||||
}
|
||||
|
||||
static const char *enable_name(unsigned long val)
|
||||
{
|
||||
return val ? "ENABLE" : "DISABLE";
|
||||
}
|
||||
|
||||
static const char *drive_name(unsigned long val)
|
||||
{
|
||||
if (val >= TEGRA_MAX_DRIVE)
|
||||
return "<UNKNOWN>";
|
||||
|
||||
return tegra_drive_names[val];
|
||||
}
|
||||
|
||||
static const char *slew_name(unsigned long val)
|
||||
{
|
||||
if (val >= TEGRA_MAX_SLEW)
|
||||
return "<UNKNOWN>";
|
||||
|
||||
return tegra_slew_names[val];
|
||||
}
|
||||
|
||||
static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
if (pg < 0 || pg >= drive_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
if (hsm == TEGRA_HSM_ENABLE)
|
||||
reg |= (1 << 2);
|
||||
else
|
||||
reg &= ~(1 << 2);
|
||||
pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
if (pg < 0 || pg >= drive_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
if (schmitt == TEGRA_SCHMITT_ENABLE)
|
||||
reg |= (1 << 3);
|
||||
else
|
||||
reg &= ~(1 << 3);
|
||||
pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
if (pg < 0 || pg >= drive_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
reg &= ~(0x3 << 4);
|
||||
reg |= drive << 4;
|
||||
pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_drive_pinmux_set_pull_down(int pg,
|
||||
enum tegra_pull_strength pull_down)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
if (pg < 0 || pg >= drive_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
reg &= ~(0x1f << 12);
|
||||
reg |= pull_down << 12;
|
||||
pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_drive_pinmux_set_pull_up(int pg,
|
||||
enum tegra_pull_strength pull_up)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
if (pg < 0 || pg >= drive_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
reg &= ~(0x1f << 12);
|
||||
reg |= pull_up << 12;
|
||||
pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_drive_pinmux_set_slew_rising(int pg,
|
||||
enum tegra_slew slew_rising)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
if (pg < 0 || pg >= drive_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
reg &= ~(0x3 << 28);
|
||||
reg |= slew_rising << 28;
|
||||
pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_drive_pinmux_set_slew_falling(int pg,
|
||||
enum tegra_slew slew_falling)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
if (pg < 0 || pg >= drive_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
reg &= ~(0x3 << 30);
|
||||
reg |= slew_falling << 30;
|
||||
pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tegra_drive_pinmux_config_pingroup(int pingroup,
|
||||
enum tegra_hsm hsm,
|
||||
enum tegra_schmitt schmitt,
|
||||
enum tegra_drive drive,
|
||||
enum tegra_pull_strength pull_down,
|
||||
enum tegra_pull_strength pull_up,
|
||||
enum tegra_slew slew_rising,
|
||||
enum tegra_slew slew_falling)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
|
||||
drive_pinmux_name(pingroup),
|
||||
enable_name(hsm), err);
|
||||
|
||||
err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
|
||||
drive_pinmux_name(pingroup),
|
||||
enable_name(schmitt), err);
|
||||
|
||||
err = tegra_drive_pinmux_set_drive(pingroup, drive);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
|
||||
drive_pinmux_name(pingroup),
|
||||
drive_name(drive), err);
|
||||
|
||||
err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
|
||||
drive_pinmux_name(pingroup),
|
||||
pull_down, err);
|
||||
|
||||
err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
|
||||
drive_pinmux_name(pingroup),
|
||||
pull_up, err);
|
||||
|
||||
err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
|
||||
drive_pinmux_name(pingroup),
|
||||
slew_name(slew_rising), err);
|
||||
|
||||
err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
|
||||
drive_pinmux_name(pingroup),
|
||||
slew_name(slew_falling), err);
|
||||
}
|
||||
|
||||
void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
|
||||
int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
tegra_drive_pinmux_config_pingroup(config[i].pingroup,
|
||||
config[i].hsm,
|
||||
config[i].schmitt,
|
||||
config[i].drive,
|
||||
config[i].pull_down,
|
||||
config[i].pull_up,
|
||||
config[i].slew_rising,
|
||||
config[i].slew_falling);
|
||||
}
|
||||
|
||||
void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
|
||||
int len)
|
||||
{
|
||||
int i;
|
||||
struct tegra_pingroup_config c;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
int err;
|
||||
c = config[i];
|
||||
if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
|
||||
WARN_ON(1);
|
||||
continue;
|
||||
}
|
||||
c.func = pingroups[c.pingroup].func_safe;
|
||||
err = tegra_pinmux_set_func(&c);
|
||||
if (err < 0)
|
||||
pr_err("%s: tegra_pinmux_set_func returned %d setting "
|
||||
"%s to %s\n", __func__, err,
|
||||
pingroup_name(c.pingroup), func_name(c.func));
|
||||
}
|
||||
}
|
||||
|
||||
void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
|
||||
int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
int err;
|
||||
if (config[i].pingroup < 0 ||
|
||||
config[i].pingroup >= pingroup_max) {
|
||||
WARN_ON(1);
|
||||
continue;
|
||||
}
|
||||
err = tegra_pinmux_set_func(&config[i]);
|
||||
if (err < 0)
|
||||
pr_err("%s: tegra_pinmux_set_func returned %d setting "
|
||||
"%s to %s\n", __func__, err,
|
||||
pingroup_name(config[i].pingroup),
|
||||
func_name(config[i].func));
|
||||
}
|
||||
}
|
||||
|
||||
void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
|
||||
int len, enum tegra_tristate tristate)
|
||||
{
|
||||
int i;
|
||||
int err;
|
||||
int pingroup;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
pingroup = config[i].pingroup;
|
||||
if (pingroups[pingroup].tri_reg >= 0) {
|
||||
err = tegra_pinmux_set_tristate(pingroup, tristate);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s tristate"
|
||||
" to %s: %d\n", pingroup_name(pingroup),
|
||||
tri_name(tristate), err);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
|
||||
int len, enum tegra_pullupdown pupd)
|
||||
{
|
||||
int i;
|
||||
int err;
|
||||
int pingroup;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
pingroup = config[i].pingroup;
|
||||
if (pingroups[pingroup].pupd_reg >= 0) {
|
||||
err = tegra_pinmux_set_pullupdown(pingroup, pupd);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s pullupdown"
|
||||
" to %s: %d\n", pingroup_name(pingroup),
|
||||
pupd_name(pupd), err);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
|
||||
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
|
||||
{ .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
|
||||
{ .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init },
|
||||
#endif
|
||||
{ },
|
||||
};
|
||||
|
||||
static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
int i;
|
||||
int config_bad = 0;
|
||||
const struct of_device_id *match;
|
||||
|
||||
match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
|
||||
|
||||
if (match)
|
||||
((pinmux_init)(match->data))(&pingroups, &pingroup_max,
|
||||
&drive_pingroups, &drive_max);
|
||||
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
|
||||
else
|
||||
/* no device tree available, so we must be on tegra20 */
|
||||
tegra20_pinmux_init(&pingroups, &pingroup_max,
|
||||
&drive_pingroups, &drive_max);
|
||||
#else
|
||||
pr_warn("non Tegra20 platform requires pinmux devicetree node\n");
|
||||
#endif
|
||||
|
||||
for (i = 0; ; i++) {
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
||||
if (!res)
|
||||
break;
|
||||
}
|
||||
nbanks = i;
|
||||
|
||||
for (i = 0; i < pingroup_max; i++) {
|
||||
if (pingroups[i].tri_bank >= nbanks) {
|
||||
dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
|
||||
config_bad = 1;
|
||||
}
|
||||
|
||||
if (pingroups[i].mux_bank >= nbanks) {
|
||||
dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i);
|
||||
config_bad = 1;
|
||||
}
|
||||
|
||||
if (pingroups[i].pupd_bank >= nbanks) {
|
||||
dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i);
|
||||
config_bad = 1;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < drive_max; i++) {
|
||||
if (drive_pingroups[i].reg_bank >= nbanks) {
|
||||
dev_err(&pdev->dev,
|
||||
"drive pingroup %d: bad reg_bank\n", i);
|
||||
config_bad = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (config_bad)
|
||||
return -ENODEV;
|
||||
|
||||
regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL);
|
||||
if (!regs) {
|
||||
dev_err(&pdev->dev, "Can't alloc regs pointer\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
for (i = 0; i < nbanks; i++) {
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "Missing MEM resource\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (!devm_request_mem_region(&pdev->dev, res->start,
|
||||
resource_size(res),
|
||||
dev_name(&pdev->dev))) {
|
||||
dev_err(&pdev->dev,
|
||||
"Couldn't request MEM resource %d\n", i);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
regs[i] = devm_ioremap(&pdev->dev, res->start,
|
||||
resource_size(res));
|
||||
if (!regs) {
|
||||
dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver tegra_pinmux_driver = {
|
||||
.driver = {
|
||||
.name = "tegra-pinmux",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = tegra_pinmux_of_match,
|
||||
},
|
||||
.probe = tegra_pinmux_probe,
|
||||
};
|
||||
|
||||
static int __init tegra_pinmux_init(void)
|
||||
{
|
||||
return platform_driver_register(&tegra_pinmux_driver);
|
||||
}
|
||||
postcore_initcall(tegra_pinmux_init);
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/seq_file.h>
|
||||
|
||||
static void dbg_pad_field(struct seq_file *s, int len)
|
||||
{
|
||||
seq_putc(s, ',');
|
||||
|
||||
while (len-- > -1)
|
||||
seq_putc(s, ' ');
|
||||
}
|
||||
|
||||
static int dbg_pinmux_show(struct seq_file *s, void *unused)
|
||||
{
|
||||
int i;
|
||||
int len;
|
||||
|
||||
for (i = 0; i < pingroup_max; i++) {
|
||||
unsigned long reg;
|
||||
unsigned long tri;
|
||||
unsigned long mux;
|
||||
unsigned long pupd;
|
||||
|
||||
seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
|
||||
len = strlen(pingroups[i].name);
|
||||
dbg_pad_field(s, 5 - len);
|
||||
|
||||
if (pingroups[i].mux_reg < 0) {
|
||||
seq_printf(s, "TEGRA_MUX_NONE");
|
||||
len = strlen("NONE");
|
||||
} else {
|
||||
reg = pg_readl(pingroups[i].mux_bank,
|
||||
pingroups[i].mux_reg);
|
||||
mux = (reg >> pingroups[i].mux_bit) & 0x3;
|
||||
if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
|
||||
seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
|
||||
len = 5;
|
||||
} else {
|
||||
seq_printf(s, "TEGRA_MUX_%s",
|
||||
tegra_mux_names[pingroups[i].funcs[mux]]);
|
||||
len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
|
||||
}
|
||||
}
|
||||
dbg_pad_field(s, 13-len);
|
||||
|
||||
if (pingroups[i].pupd_reg < 0) {
|
||||
seq_printf(s, "TEGRA_PUPD_NORMAL");
|
||||
len = strlen("NORMAL");
|
||||
} else {
|
||||
reg = pg_readl(pingroups[i].pupd_bank,
|
||||
pingroups[i].pupd_reg);
|
||||
pupd = (reg >> pingroups[i].pupd_bit) & 0x3;
|
||||
seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
|
||||
len = strlen(pupd_name(pupd));
|
||||
}
|
||||
dbg_pad_field(s, 9 - len);
|
||||
|
||||
if (pingroups[i].tri_reg < 0) {
|
||||
seq_printf(s, "TEGRA_TRI_NORMAL");
|
||||
} else {
|
||||
reg = pg_readl(pingroups[i].tri_bank,
|
||||
pingroups[i].tri_reg);
|
||||
tri = (reg >> pingroups[i].tri_bit) & 0x1;
|
||||
|
||||
seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
|
||||
}
|
||||
seq_printf(s, "},\n");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dbg_pinmux_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, dbg_pinmux_show, &inode->i_private);
|
||||
}
|
||||
|
||||
static const struct file_operations debug_fops = {
|
||||
.open = dbg_pinmux_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
|
||||
{
|
||||
int i;
|
||||
int len;
|
||||
|
||||
for (i = 0; i < drive_max; i++) {
|
||||
u32 reg;
|
||||
|
||||
seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
|
||||
drive_pingroups[i].name);
|
||||
len = strlen(drive_pingroups[i].name);
|
||||
dbg_pad_field(s, 7 - len);
|
||||
|
||||
|
||||
reg = pg_readl(drive_pingroups[i].reg_bank,
|
||||
drive_pingroups[i].reg);
|
||||
if (HSM_EN(reg)) {
|
||||
seq_printf(s, "TEGRA_HSM_ENABLE");
|
||||
len = 16;
|
||||
} else {
|
||||
seq_printf(s, "TEGRA_HSM_DISABLE");
|
||||
len = 17;
|
||||
}
|
||||
dbg_pad_field(s, 17 - len);
|
||||
|
||||
if (SCHMT_EN(reg)) {
|
||||
seq_printf(s, "TEGRA_SCHMITT_ENABLE");
|
||||
len = 21;
|
||||
} else {
|
||||
seq_printf(s, "TEGRA_SCHMITT_DISABLE");
|
||||
len = 22;
|
||||
}
|
||||
dbg_pad_field(s, 22 - len);
|
||||
|
||||
seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
|
||||
len = strlen(drive_name(LPMD(reg)));
|
||||
dbg_pad_field(s, 5 - len);
|
||||
|
||||
seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg));
|
||||
len = DRVDN(reg) < 10 ? 1 : 2;
|
||||
dbg_pad_field(s, 2 - len);
|
||||
|
||||
seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg));
|
||||
len = DRVUP(reg) < 10 ? 1 : 2;
|
||||
dbg_pad_field(s, 2 - len);
|
||||
|
||||
seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg)));
|
||||
len = strlen(slew_name(SLWR(reg)));
|
||||
dbg_pad_field(s, 7 - len);
|
||||
|
||||
seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg)));
|
||||
|
||||
seq_printf(s, "},\n");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
|
||||
}
|
||||
|
||||
static const struct file_operations debug_drive_fops = {
|
||||
.open = dbg_drive_pinmux_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static int __init tegra_pinmux_debuginit(void)
|
||||
{
|
||||
(void) debugfs_create_file("tegra_pinmux", S_IRUGO,
|
||||
NULL, NULL, &debug_fops);
|
||||
(void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
|
||||
NULL, NULL, &debug_drive_fops);
|
||||
return 0;
|
||||
}
|
||||
late_initcall(tegra_pinmux_debuginit);
|
||||
#endif
|
||||
|
|
@ -711,7 +711,6 @@ struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
|
|||
err = -ENXIO;
|
||||
goto err1;
|
||||
}
|
||||
tegra_gpio_enable(ulpi_config->reset_gpio);
|
||||
gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
|
||||
gpio_direction_output(ulpi_config->reset_gpio, 0);
|
||||
phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
|
||||
|
|
|
|||
|
|
@ -9,6 +9,8 @@ config UX500_SOC_COMMON
|
|||
select ARM_ERRATA_754322
|
||||
select ARM_ERRATA_764369
|
||||
select CACHE_L2X0
|
||||
select PINCTRL
|
||||
select PINCTRL_NOMADIK
|
||||
|
||||
config UX500_SOC_DB8500
|
||||
bool
|
||||
|
|
@ -16,6 +18,7 @@ config UX500_SOC_DB8500
|
|||
select REGULATOR
|
||||
select REGULATOR_DB8500_PRCMU
|
||||
select CPU_FREQ_TABLE if CPU_FREQ
|
||||
select PINCTRL_DB8500
|
||||
|
||||
menu "Ux500 target platform (boards)"
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \
|
|||
board-mop500-regulators.o \
|
||||
board-mop500-uib.o board-mop500-stuib.o \
|
||||
board-mop500-u8500uib.o \
|
||||
board-mop500-pins.o
|
||||
board-mop500-pins.o \
|
||||
board-mop500-msp.o
|
||||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,267 @@
|
|||
/*
|
||||
* Copyright (C) ST-Ericsson SA 2010
|
||||
*
|
||||
* License terms: GNU General Public License (GPL), version 2
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
#include <plat/gpio-nomadik.h>
|
||||
#include <plat/pincfg.h>
|
||||
#include <plat/ste_dma40.h>
|
||||
|
||||
#include <mach/devices.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/msp.h>
|
||||
|
||||
#include "ste-dma40-db8500.h"
|
||||
#include "board-mop500.h"
|
||||
#include "devices-db8500.h"
|
||||
#include "pins-db8500.h"
|
||||
|
||||
/* MSP1/3 Tx/Rx usage protection */
|
||||
static DEFINE_SPINLOCK(msp_rxtx_lock);
|
||||
|
||||
/* Reference Count */
|
||||
static int msp_rxtx_ref;
|
||||
|
||||
/* Pin modes */
|
||||
struct pinctrl *msp1_p;
|
||||
struct pinctrl_state *msp1_def;
|
||||
struct pinctrl_state *msp1_sleep;
|
||||
|
||||
int msp13_i2s_init(void)
|
||||
{
|
||||
int retval = 0;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&msp_rxtx_lock, flags);
|
||||
if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_def))) {
|
||||
retval = pinctrl_select_state(msp1_p, msp1_def);
|
||||
if (retval)
|
||||
pr_err("could not set MSP1 defstate\n");
|
||||
}
|
||||
if (!retval)
|
||||
msp_rxtx_ref++;
|
||||
spin_unlock_irqrestore(&msp_rxtx_lock, flags);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
int msp13_i2s_exit(void)
|
||||
{
|
||||
int retval = 0;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&msp_rxtx_lock, flags);
|
||||
WARN_ON(!msp_rxtx_ref);
|
||||
msp_rxtx_ref--;
|
||||
if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_sleep))) {
|
||||
retval = pinctrl_select_state(msp1_p, msp1_sleep);
|
||||
if (retval)
|
||||
pr_err("could not set MSP1 sleepstate\n");
|
||||
}
|
||||
spin_unlock_irqrestore(&msp_rxtx_lock, flags);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static struct stedma40_chan_cfg msp0_dma_rx = {
|
||||
.high_priority = true,
|
||||
.dir = STEDMA40_PERIPH_TO_MEM,
|
||||
|
||||
.src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,
|
||||
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
|
||||
|
||||
.src_info.psize = STEDMA40_PSIZE_LOG_4,
|
||||
.dst_info.psize = STEDMA40_PSIZE_LOG_4,
|
||||
|
||||
/* data_width is set during configuration */
|
||||
};
|
||||
|
||||
static struct stedma40_chan_cfg msp0_dma_tx = {
|
||||
.high_priority = true,
|
||||
.dir = STEDMA40_MEM_TO_PERIPH,
|
||||
|
||||
.src_dev_type = STEDMA40_DEV_DST_MEMORY,
|
||||
.dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,
|
||||
|
||||
.src_info.psize = STEDMA40_PSIZE_LOG_4,
|
||||
.dst_info.psize = STEDMA40_PSIZE_LOG_4,
|
||||
|
||||
/* data_width is set during configuration */
|
||||
};
|
||||
|
||||
static struct msp_i2s_platform_data msp0_platform_data = {
|
||||
.id = MSP_I2S_0,
|
||||
.msp_i2s_dma_rx = &msp0_dma_rx,
|
||||
.msp_i2s_dma_tx = &msp0_dma_tx,
|
||||
};
|
||||
|
||||
static struct stedma40_chan_cfg msp1_dma_rx = {
|
||||
.high_priority = true,
|
||||
.dir = STEDMA40_PERIPH_TO_MEM,
|
||||
|
||||
.src_dev_type = DB8500_DMA_DEV30_MSP3_RX,
|
||||
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
|
||||
|
||||
.src_info.psize = STEDMA40_PSIZE_LOG_4,
|
||||
.dst_info.psize = STEDMA40_PSIZE_LOG_4,
|
||||
|
||||
/* data_width is set during configuration */
|
||||
};
|
||||
|
||||
static struct stedma40_chan_cfg msp1_dma_tx = {
|
||||
.high_priority = true,
|
||||
.dir = STEDMA40_MEM_TO_PERIPH,
|
||||
|
||||
.src_dev_type = STEDMA40_DEV_DST_MEMORY,
|
||||
.dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,
|
||||
|
||||
.src_info.psize = STEDMA40_PSIZE_LOG_4,
|
||||
.dst_info.psize = STEDMA40_PSIZE_LOG_4,
|
||||
|
||||
/* data_width is set during configuration */
|
||||
};
|
||||
|
||||
static struct msp_i2s_platform_data msp1_platform_data = {
|
||||
.id = MSP_I2S_1,
|
||||
.msp_i2s_dma_rx = NULL,
|
||||
.msp_i2s_dma_tx = &msp1_dma_tx,
|
||||
.msp_i2s_init = msp13_i2s_init,
|
||||
.msp_i2s_exit = msp13_i2s_exit,
|
||||
};
|
||||
|
||||
static struct stedma40_chan_cfg msp2_dma_rx = {
|
||||
.high_priority = true,
|
||||
.dir = STEDMA40_PERIPH_TO_MEM,
|
||||
|
||||
.src_dev_type = DB8500_DMA_DEV14_MSP2_RX,
|
||||
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
|
||||
|
||||
/* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
|
||||
.src_info.psize = STEDMA40_PSIZE_LOG_1,
|
||||
.dst_info.psize = STEDMA40_PSIZE_LOG_1,
|
||||
|
||||
/* data_width is set during configuration */
|
||||
};
|
||||
|
||||
static struct stedma40_chan_cfg msp2_dma_tx = {
|
||||
.high_priority = true,
|
||||
.dir = STEDMA40_MEM_TO_PERIPH,
|
||||
|
||||
.src_dev_type = STEDMA40_DEV_DST_MEMORY,
|
||||
.dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,
|
||||
|
||||
.src_info.psize = STEDMA40_PSIZE_LOG_4,
|
||||
.dst_info.psize = STEDMA40_PSIZE_LOG_4,
|
||||
|
||||
.use_fixed_channel = true,
|
||||
.phy_channel = 1,
|
||||
|
||||
/* data_width is set during configuration */
|
||||
};
|
||||
|
||||
static struct platform_device *db8500_add_msp_i2s(struct device *parent,
|
||||
int id,
|
||||
resource_size_t base, int irq,
|
||||
struct msp_i2s_platform_data *pdata)
|
||||
{
|
||||
struct platform_device *pdev;
|
||||
struct resource res[] = {
|
||||
DEFINE_RES_MEM(base, SZ_4K),
|
||||
DEFINE_RES_IRQ(irq),
|
||||
};
|
||||
|
||||
pr_info("Register platform-device 'ux500-msp-i2s', id %d, irq %d\n",
|
||||
id, irq);
|
||||
pdev = platform_device_register_resndata(parent, "ux500-msp-i2s", id,
|
||||
res, ARRAY_SIZE(res),
|
||||
pdata, sizeof(*pdata));
|
||||
if (!pdev) {
|
||||
pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n",
|
||||
id);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return pdev;
|
||||
}
|
||||
|
||||
/* Platform device for ASoC U8500 machine */
|
||||
static struct platform_device snd_soc_u8500 = {
|
||||
.name = "snd-soc-u8500",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = NULL,
|
||||
},
|
||||
};
|
||||
|
||||
/* Platform device for Ux500-PCM */
|
||||
static struct platform_device ux500_pcm = {
|
||||
.name = "ux500-pcm",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = NULL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msp_i2s_platform_data msp2_platform_data = {
|
||||
.id = MSP_I2S_2,
|
||||
.msp_i2s_dma_rx = &msp2_dma_rx,
|
||||
.msp_i2s_dma_tx = &msp2_dma_tx,
|
||||
};
|
||||
|
||||
static struct msp_i2s_platform_data msp3_platform_data = {
|
||||
.id = MSP_I2S_3,
|
||||
.msp_i2s_dma_rx = &msp1_dma_rx,
|
||||
.msp_i2s_dma_tx = NULL,
|
||||
.msp_i2s_init = msp13_i2s_init,
|
||||
.msp_i2s_exit = msp13_i2s_exit,
|
||||
};
|
||||
|
||||
int mop500_msp_init(struct device *parent)
|
||||
{
|
||||
struct platform_device *msp1;
|
||||
|
||||
pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__);
|
||||
platform_device_register(&snd_soc_u8500);
|
||||
|
||||
pr_info("Initialize MSP I2S-devices.\n");
|
||||
db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
|
||||
&msp0_platform_data);
|
||||
msp1 = db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
|
||||
&msp1_platform_data);
|
||||
db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
|
||||
&msp2_platform_data);
|
||||
db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
|
||||
&msp3_platform_data);
|
||||
|
||||
/* Get the pinctrl handle for MSP1 */
|
||||
if (msp1) {
|
||||
msp1_p = pinctrl_get(&msp1->dev);
|
||||
if (IS_ERR(msp1_p))
|
||||
dev_err(&msp1->dev, "could not get MSP1 pinctrl\n");
|
||||
else {
|
||||
msp1_def = pinctrl_lookup_state(msp1_p,
|
||||
PINCTRL_STATE_DEFAULT);
|
||||
if (IS_ERR(msp1_def)) {
|
||||
dev_err(&msp1->dev,
|
||||
"could not get MSP1 defstate\n");
|
||||
}
|
||||
msp1_sleep = pinctrl_lookup_state(msp1_p,
|
||||
PINCTRL_STATE_SLEEP);
|
||||
if (IS_ERR(msp1_sleep))
|
||||
dev_err(&msp1->dev,
|
||||
"could not get MSP1 idlestate\n");
|
||||
}
|
||||
}
|
||||
|
||||
pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
|
||||
platform_device_register(&ux500_pcm);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* Copyright (C) ST-Ericsson SA 2012
|
||||
*
|
||||
* Author: Ola Lilja <ola.o.lilja@stericsson.com>,
|
||||
* for ST-Ericsson.
|
||||
*
|
||||
* License terms:
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
void mop500_msp_init(struct device *parent);
|
||||
|
|
@ -7,299 +7,508 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/bug.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <plat/pincfg.h>
|
||||
#include <plat/gpio-nomadik.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#include "pins-db8500.h"
|
||||
#include "board-mop500.h"
|
||||
|
||||
static pin_cfg_t mop500_pins_common[] = {
|
||||
/* I2C */
|
||||
GPIO147_I2C0_SCL,
|
||||
GPIO148_I2C0_SDA,
|
||||
GPIO16_I2C1_SCL,
|
||||
GPIO17_I2C1_SDA,
|
||||
GPIO10_I2C2_SDA,
|
||||
GPIO11_I2C2_SCL,
|
||||
GPIO229_I2C3_SDA,
|
||||
GPIO230_I2C3_SCL,
|
||||
enum custom_pin_cfg_t {
|
||||
PINS_FOR_DEFAULT,
|
||||
PINS_FOR_U9500,
|
||||
};
|
||||
|
||||
/* MSP0 */
|
||||
GPIO12_MSP0_TXD,
|
||||
GPIO13_MSP0_TFS,
|
||||
GPIO14_MSP0_TCK,
|
||||
GPIO15_MSP0_RXD,
|
||||
static enum custom_pin_cfg_t pinsfor;
|
||||
|
||||
/* MSP2: HDMI */
|
||||
GPIO193_MSP2_TXD,
|
||||
GPIO194_MSP2_TCK,
|
||||
GPIO195_MSP2_TFS,
|
||||
GPIO196_MSP2_RXD | PIN_OUTPUT_LOW,
|
||||
/* These simply sets bias for pins */
|
||||
#define BIAS(a,b) static unsigned long a[] = { b }
|
||||
|
||||
/* Touch screen INTERFACE */
|
||||
GPIO84_GPIO | PIN_INPUT_PULLUP, /* TOUCH_INT1 */
|
||||
BIAS(pd, PIN_PULL_DOWN);
|
||||
BIAS(slpm_gpio_nopull, PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
|
||||
BIAS(in_nopull, PIN_INPUT_NOPULL);
|
||||
BIAS(in_nopull_sleep_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
|
||||
BIAS(in_pu, PIN_INPUT_PULLUP);
|
||||
BIAS(in_pd, PIN_INPUT_PULLDOWN);
|
||||
BIAS(in_pd_slpm_in_pu, PIN_INPUT_PULLDOWN|PIN_SLPM_INPUT_PULLUP);
|
||||
BIAS(in_pu_slpm_out_lo, PIN_INPUT_PULLUP|PIN_SLPM_OUTPUT_LOW);
|
||||
BIAS(out_hi, PIN_OUTPUT_HIGH);
|
||||
BIAS(out_lo, PIN_OUTPUT_LOW);
|
||||
BIAS(out_lo_sleep_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
|
||||
/* These also force them into GPIO mode */
|
||||
BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
|
||||
BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
|
||||
BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
|
||||
BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
|
||||
BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
|
||||
BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
|
||||
/* Sleep modes */
|
||||
BIAS(sleep_in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(sleep_in_nopull_wkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE);
|
||||
BIAS(sleep_out_hi_wkup_pdis, PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(sleep_out_lo_wkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
|
||||
BIAS(sleep_out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
|
||||
/* STMPE1601/tc35893 keypad IRQ */
|
||||
GPIO218_GPIO | PIN_INPUT_PULLUP,
|
||||
/* We use these to define hog settings that are always done on boot */
|
||||
#define DB8500_MUX_HOG(group,func) \
|
||||
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
|
||||
#define DB8500_PIN_HOG(pin,conf) \
|
||||
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
|
||||
|
||||
/* MMC0 (MicroSD card) */
|
||||
GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH,
|
||||
GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH,
|
||||
GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH,
|
||||
/* These are default states associated with device and changed runtime */
|
||||
#define DB8500_MUX(group,func,dev) \
|
||||
PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
|
||||
#define DB8500_PIN(pin,conf,dev) \
|
||||
PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
|
||||
|
||||
GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL,
|
||||
GPIO23_MC0_CLK | PIN_OUTPUT_LOW,
|
||||
GPIO24_MC0_CMD | PIN_INPUT_PULLUP,
|
||||
GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP,
|
||||
GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP,
|
||||
GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP,
|
||||
GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP,
|
||||
#define DB8500_PIN_SLEEP(pin,conf,dev) \
|
||||
PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
|
||||
pin, conf)
|
||||
|
||||
/* SDI1 (SDIO) */
|
||||
GPIO208_MC1_CLK | PIN_OUTPUT_LOW,
|
||||
GPIO209_MC1_FBCLK | PIN_INPUT_NOPULL,
|
||||
GPIO210_MC1_CMD | PIN_INPUT_PULLUP,
|
||||
GPIO211_MC1_DAT0 | PIN_INPUT_PULLUP,
|
||||
GPIO212_MC1_DAT1 | PIN_INPUT_PULLUP,
|
||||
GPIO213_MC1_DAT2 | PIN_INPUT_PULLUP,
|
||||
GPIO214_MC1_DAT3 | PIN_INPUT_PULLUP,
|
||||
|
||||
/* MMC2 (On-board DATA INTERFACE eMMC) */
|
||||
GPIO128_MC2_CLK | PIN_OUTPUT_LOW,
|
||||
GPIO129_MC2_CMD | PIN_INPUT_PULLUP,
|
||||
GPIO130_MC2_FBCLK | PIN_INPUT_NOPULL,
|
||||
GPIO131_MC2_DAT0 | PIN_INPUT_PULLUP,
|
||||
GPIO132_MC2_DAT1 | PIN_INPUT_PULLUP,
|
||||
GPIO133_MC2_DAT2 | PIN_INPUT_PULLUP,
|
||||
GPIO134_MC2_DAT3 | PIN_INPUT_PULLUP,
|
||||
GPIO135_MC2_DAT4 | PIN_INPUT_PULLUP,
|
||||
GPIO136_MC2_DAT5 | PIN_INPUT_PULLUP,
|
||||
GPIO137_MC2_DAT6 | PIN_INPUT_PULLUP,
|
||||
GPIO138_MC2_DAT7 | PIN_INPUT_PULLUP,
|
||||
|
||||
/* MMC4 (On-board STORAGE INTERFACE eMMC) */
|
||||
GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP,
|
||||
GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP,
|
||||
GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP,
|
||||
GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP,
|
||||
GPIO201_MC4_CMD | PIN_INPUT_PULLUP,
|
||||
GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL,
|
||||
GPIO203_MC4_CLK | PIN_OUTPUT_LOW,
|
||||
GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP,
|
||||
GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP,
|
||||
GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP,
|
||||
GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP,
|
||||
|
||||
/* SKE keypad */
|
||||
GPIO153_KP_I7,
|
||||
GPIO154_KP_I6,
|
||||
GPIO155_KP_I5,
|
||||
GPIO156_KP_I4,
|
||||
GPIO157_KP_O7,
|
||||
GPIO158_KP_O6,
|
||||
GPIO159_KP_O5,
|
||||
GPIO160_KP_O4,
|
||||
GPIO161_KP_I3,
|
||||
GPIO162_KP_I2,
|
||||
GPIO163_KP_I1,
|
||||
GPIO164_KP_I0,
|
||||
GPIO165_KP_O3,
|
||||
GPIO166_KP_O2,
|
||||
GPIO167_KP_O1,
|
||||
GPIO168_KP_O0,
|
||||
|
||||
/* UART */
|
||||
/* uart-0 pins gpio configuration should be
|
||||
* kept intact to prevent glitch in tx line
|
||||
* when tty dev is opened. Later these pins
|
||||
* are configured to uart mop500_pins_uart0
|
||||
*
|
||||
* It will be replaced with uart configuration
|
||||
* once the issue is solved.
|
||||
/* Pin control settings */
|
||||
static struct pinctrl_map __initdata mop500_family_pinmap[] = {
|
||||
/*
|
||||
* uMSP0, mux in 4 pins, regular placement of RX/TX
|
||||
* explicitly set the pins to no pull
|
||||
*/
|
||||
GPIO0_GPIO | PIN_INPUT_PULLUP,
|
||||
GPIO1_GPIO | PIN_OUTPUT_HIGH,
|
||||
GPIO2_GPIO | PIN_INPUT_PULLUP,
|
||||
GPIO3_GPIO | PIN_OUTPUT_HIGH,
|
||||
|
||||
GPIO29_U2_RXD | PIN_INPUT_PULLUP,
|
||||
GPIO30_U2_TXD | PIN_OUTPUT_HIGH,
|
||||
GPIO31_U2_CTSn | PIN_INPUT_PULLUP,
|
||||
GPIO32_U2_RTSn | PIN_OUTPUT_HIGH,
|
||||
|
||||
/* Display & HDMI HW sync */
|
||||
GPIO68_LCD_VSI0 | PIN_INPUT_PULLUP,
|
||||
GPIO69_LCD_VSI1 | PIN_INPUT_PULLUP,
|
||||
DB8500_MUX_HOG("msp0txrx_a_1", "msp0"),
|
||||
DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"),
|
||||
DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */
|
||||
DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */
|
||||
DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */
|
||||
DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */
|
||||
/* MSP2 for HDMI, pull down TXD, TCK, TFS */
|
||||
DB8500_MUX_HOG("msp2_a_1", "msp2"),
|
||||
DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */
|
||||
DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */
|
||||
DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */
|
||||
DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */
|
||||
/*
|
||||
* LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to
|
||||
* pull-up
|
||||
* TODO: is this really correct? Snowball doesn't have a LCD.
|
||||
*/
|
||||
DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"),
|
||||
DB8500_PIN_HOG("GPIO68_E1", in_pu),
|
||||
DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu),
|
||||
/*
|
||||
* STMPE1601/tc35893 keypad IRQ GPIO 218
|
||||
* TODO: set for snowball and HREF really??
|
||||
*/
|
||||
DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu),
|
||||
/*
|
||||
* UART0, we do not mux in u0 here.
|
||||
* uart-0 pins gpio configuration should be kept intact to prevent
|
||||
* a glitch in tx line when the tty dev is opened. Later these pins
|
||||
* are configured to uart mop500_pins_uart0
|
||||
*/
|
||||
DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */
|
||||
DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */
|
||||
DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */
|
||||
DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */
|
||||
/*
|
||||
* Mux in UART2 on altfunction C and set pull-ups.
|
||||
* TODO: is this used on U8500 variants and Snowball really?
|
||||
* The setting on GPIO31 conflicts with magnetometer use on hrefv60
|
||||
*/
|
||||
DB8500_MUX_HOG("u2rxtx_c_1", "u2"),
|
||||
DB8500_MUX_HOG("u2ctsrts_c_1", "u2"),
|
||||
DB8500_PIN_HOG("GPIO29_W2", in_pu), /* RXD */
|
||||
DB8500_PIN_HOG("GPIO30_W3", out_hi), /* TXD */
|
||||
DB8500_PIN_HOG("GPIO31_V3", in_pu), /* CTS */
|
||||
DB8500_PIN_HOG("GPIO32_V2", out_hi), /* RTS */
|
||||
/*
|
||||
* The following pin sets were known as "runtime pins" before being
|
||||
* converted to the pinctrl model. Here we model them as "default"
|
||||
* states.
|
||||
*/
|
||||
/* Mux in UART0 after initialization */
|
||||
DB8500_MUX("u0_a_1", "u0", "uart0"),
|
||||
DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */
|
||||
DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */
|
||||
DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
|
||||
DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
|
||||
/* UART0 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO0_AJ5", sleep_in_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO1_AJ3", sleep_out_hi_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO2_AH4", sleep_in_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO3_AH3", sleep_out_wkup_pdis, "uart0"),
|
||||
/* MSP1 for ALSA codec */
|
||||
DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
|
||||
DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO33_AF2", out_lo_sleep_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO34_AE1", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO35_AE2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO36_AG2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
|
||||
/* MSP1 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO33_AF2", sleep_out_lo_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO34_AE1", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO35_AE2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO36_AG2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
|
||||
/* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
|
||||
DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
|
||||
DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
|
||||
/* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
|
||||
DB8500_MUX("lcdvsi1_a_1", "lcd", "av8100-hdmi"),
|
||||
/* Mux in I2C blocks, put pins into GPIO in sleepmode no pull-up */
|
||||
DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
|
||||
DB8500_PIN("GPIO147_C15", slpm_gpio_nopull, "nmk-i2c.0"),
|
||||
DB8500_PIN("GPIO148_B16", slpm_gpio_nopull, "nmk-i2c.0"),
|
||||
DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
|
||||
DB8500_PIN("GPIO16_AD3", slpm_gpio_nopull, "nmk-i2c.1"),
|
||||
DB8500_PIN("GPIO17_AD4", slpm_gpio_nopull, "nmk-i2c.1"),
|
||||
DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
|
||||
DB8500_PIN("GPIO10_AF5", slpm_gpio_nopull, "nmk-i2c.2"),
|
||||
DB8500_PIN("GPIO11_AG4", slpm_gpio_nopull, "nmk-i2c.2"),
|
||||
DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
|
||||
DB8500_PIN("GPIO229_AG7", slpm_gpio_nopull, "nmk-i2c.3"),
|
||||
DB8500_PIN("GPIO230_AF7", slpm_gpio_nopull, "nmk-i2c.3"),
|
||||
/* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
|
||||
DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
|
||||
DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
|
||||
DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */
|
||||
DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */
|
||||
DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */
|
||||
DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */
|
||||
DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */
|
||||
DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */
|
||||
DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */
|
||||
DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */
|
||||
DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */
|
||||
/* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */
|
||||
DB8500_MUX("mc1_a_1", "mc1", "sdi1"),
|
||||
DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */
|
||||
DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */
|
||||
DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */
|
||||
DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */
|
||||
DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */
|
||||
DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */
|
||||
DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */
|
||||
/* Mux in SDI2 (here called MC2) used for for PoP eMMC */
|
||||
DB8500_MUX("mc2_a_1", "mc2", "sdi2"),
|
||||
DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */
|
||||
DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */
|
||||
DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */
|
||||
DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */
|
||||
DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */
|
||||
DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */
|
||||
DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */
|
||||
DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */
|
||||
DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */
|
||||
DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */
|
||||
DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */
|
||||
/* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */
|
||||
DB8500_MUX("mc4_a_1", "mc4", "sdi4"),
|
||||
DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */
|
||||
DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */
|
||||
DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */
|
||||
DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */
|
||||
DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */
|
||||
DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */
|
||||
DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */
|
||||
DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */
|
||||
DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */
|
||||
DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */
|
||||
DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */
|
||||
/* Mux in USB pins, drive STP high */
|
||||
DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
|
||||
DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
|
||||
/* Mux in SPI2 pins on the "other C1" altfunction */
|
||||
DB8500_MUX("spi2_oc1_1", "spi2", "spi2"),
|
||||
DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
|
||||
DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
|
||||
DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
|
||||
DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
|
||||
};
|
||||
|
||||
static pin_cfg_t mop500_pins_default[] = {
|
||||
/* SSP0 */
|
||||
GPIO143_SSP0_CLK,
|
||||
GPIO144_SSP0_FRM,
|
||||
GPIO145_SSP0_RXD | PIN_PULL_DOWN,
|
||||
GPIO146_SSP0_TXD,
|
||||
|
||||
|
||||
GPIO217_GPIO | PIN_INPUT_PULLUP, /* TC35892 IRQ */
|
||||
|
||||
/* SDI0 (MicroSD card) */
|
||||
GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH,
|
||||
|
||||
/* UART */
|
||||
GPIO4_U1_RXD | PIN_INPUT_PULLUP,
|
||||
GPIO5_U1_TXD | PIN_OUTPUT_HIGH,
|
||||
GPIO6_U1_CTSn | PIN_INPUT_PULLUP,
|
||||
GPIO7_U1_RTSn | PIN_OUTPUT_HIGH,
|
||||
/*
|
||||
* These are specifically for the MOP500 and HREFP (pre-v60) version of the
|
||||
* board, which utilized a TC35892 GPIO expander instead of using a lot of
|
||||
* on-chip pins as the HREFv60 and later does.
|
||||
*/
|
||||
static struct pinctrl_map __initdata mop500_pinmap[] = {
|
||||
/* Mux in SSP0, pull down RXD pin */
|
||||
DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
|
||||
DB8500_PIN_HOG("GPIO145_C13", pd),
|
||||
/*
|
||||
* XENON Flashgun on image processor GPIO (controlled from image
|
||||
* processor firmware), mux in these image processor GPIO lines 0
|
||||
* (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up
|
||||
* the pins.
|
||||
*/
|
||||
DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
|
||||
DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
|
||||
DB8500_PIN_HOG("GPIO6_AF6", in_pu),
|
||||
DB8500_PIN_HOG("GPIO7_AG5", in_pu),
|
||||
/* TC35892 IRQ, pull up the line, let the driver mux in the pin */
|
||||
DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
|
||||
/* Mux in UART1 and set the pull-ups */
|
||||
DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
|
||||
DB8500_MUX_HOG("u1ctsrts_a_1", "u1"),
|
||||
DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */
|
||||
DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */
|
||||
DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* CTS */
|
||||
DB8500_PIN_HOG("GPIO7_AG5", out_hi), /* RTS */
|
||||
/*
|
||||
* Runtime stuff: make it possible to mux in the SKE keypad
|
||||
* and bias the pins
|
||||
*/
|
||||
DB8500_MUX("kp_a_2", "kp", "ske"),
|
||||
DB8500_PIN("GPIO153_B17", in_pd_slpm_in_pu, "ske"), /* I7 */
|
||||
DB8500_PIN("GPIO154_C16", in_pd_slpm_in_pu, "ske"), /* I6 */
|
||||
DB8500_PIN("GPIO155_C19", in_pd_slpm_in_pu, "ske"), /* I5 */
|
||||
DB8500_PIN("GPIO156_C17", in_pd_slpm_in_pu, "ske"), /* I4 */
|
||||
DB8500_PIN("GPIO161_D21", in_pd_slpm_in_pu, "ske"), /* I3 */
|
||||
DB8500_PIN("GPIO162_D20", in_pd_slpm_in_pu, "ske"), /* I2 */
|
||||
DB8500_PIN("GPIO163_C20", in_pd_slpm_in_pu, "ske"), /* I1 */
|
||||
DB8500_PIN("GPIO164_B21", in_pd_slpm_in_pu, "ske"), /* I0 */
|
||||
DB8500_PIN("GPIO157_A18", in_pu_slpm_out_lo, "ske"), /* O7 */
|
||||
DB8500_PIN("GPIO158_C18", in_pu_slpm_out_lo, "ske"), /* O6 */
|
||||
DB8500_PIN("GPIO159_B19", in_pu_slpm_out_lo, "ske"), /* O5 */
|
||||
DB8500_PIN("GPIO160_B20", in_pu_slpm_out_lo, "ske"), /* O4 */
|
||||
DB8500_PIN("GPIO165_C21", in_pu_slpm_out_lo, "ske"), /* O3 */
|
||||
DB8500_PIN("GPIO166_A22", in_pu_slpm_out_lo, "ske"), /* O2 */
|
||||
DB8500_PIN("GPIO167_B24", in_pu_slpm_out_lo, "ske"), /* O1 */
|
||||
DB8500_PIN("GPIO168_C22", in_pu_slpm_out_lo, "ske"), /* O0 */
|
||||
/* Mux in and drive the SDI0 DAT31DIR line high at runtime */
|
||||
DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"),
|
||||
DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"),
|
||||
};
|
||||
|
||||
static pin_cfg_t hrefv60_pins[] = {
|
||||
/* WLAN */
|
||||
GPIO4_GPIO | PIN_INPUT_PULLUP,/* WLAN_IRQ */
|
||||
GPIO85_GPIO | PIN_OUTPUT_LOW,/* WLAN_ENA */
|
||||
|
||||
/* XENON Flashgun INTERFACE */
|
||||
GPIO6_IP_GPIO0 | PIN_INPUT_PULLUP,/* XENON_FLASH_ID */
|
||||
GPIO7_IP_GPIO1 | PIN_INPUT_PULLUP,/* XENON_READY */
|
||||
GPIO170_GPIO | PIN_OUTPUT_LOW, /* XENON_CHARGE */
|
||||
|
||||
/* Assistant LED INTERFACE */
|
||||
GPIO21_GPIO | PIN_OUTPUT_LOW, /* XENON_EN1 */
|
||||
GPIO64_IP_GPIO4 | PIN_OUTPUT_LOW, /* XENON_EN2 */
|
||||
|
||||
/* Magnetometer */
|
||||
GPIO31_GPIO | PIN_INPUT_PULLUP, /* magnetometer_INT */
|
||||
GPIO32_GPIO | PIN_INPUT_PULLDOWN, /* Magnetometer DRDY */
|
||||
|
||||
/* Display Interface */
|
||||
GPIO65_GPIO | PIN_OUTPUT_LOW, /* DISP1 RST */
|
||||
GPIO66_GPIO | PIN_OUTPUT_LOW, /* DISP2 RST */
|
||||
|
||||
/* Touch screen INTERFACE */
|
||||
GPIO143_GPIO | PIN_OUTPUT_LOW,/*TOUCH_RST1 */
|
||||
|
||||
/* Touch screen INTERFACE 2 */
|
||||
GPIO67_GPIO | PIN_INPUT_PULLUP, /* TOUCH_INT2 */
|
||||
GPIO146_GPIO | PIN_OUTPUT_LOW,/*TOUCH_RST2 */
|
||||
|
||||
/* ETM_PTM_TRACE INTERFACE */
|
||||
GPIO70_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA23 */
|
||||
GPIO71_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA22 */
|
||||
GPIO72_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA21 */
|
||||
GPIO73_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA20 */
|
||||
GPIO74_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA19 */
|
||||
|
||||
/* NAHJ INTERFACE */
|
||||
GPIO76_GPIO | PIN_OUTPUT_LOW,/* NAHJ_CTRL */
|
||||
GPIO216_GPIO | PIN_OUTPUT_HIGH,/* NAHJ_CTRL_INV */
|
||||
|
||||
/* NFC INTERFACE */
|
||||
GPIO77_GPIO | PIN_OUTPUT_LOW, /* NFC_ENA */
|
||||
GPIO144_GPIO | PIN_INPUT_PULLDOWN, /* NFC_IRQ */
|
||||
GPIO142_GPIO | PIN_OUTPUT_LOW, /* NFC_RESET */
|
||||
|
||||
/* Keyboard MATRIX INTERFACE */
|
||||
GPIO90_MC5_CMD | PIN_OUTPUT_LOW, /* KP_O_1 */
|
||||
GPIO87_MC5_DAT1 | PIN_OUTPUT_LOW, /* KP_O_2 */
|
||||
GPIO86_MC5_DAT0 | PIN_OUTPUT_LOW, /* KP_O_3 */
|
||||
GPIO96_KP_O6 | PIN_OUTPUT_LOW, /* KP_O_6 */
|
||||
GPIO94_KP_O7 | PIN_OUTPUT_LOW, /* KP_O_7 */
|
||||
GPIO93_MC5_DAT4 | PIN_INPUT_PULLUP, /* KP_I_0 */
|
||||
GPIO89_MC5_DAT3 | PIN_INPUT_PULLUP, /* KP_I_2 */
|
||||
GPIO88_MC5_DAT2 | PIN_INPUT_PULLUP, /* KP_I_3 */
|
||||
GPIO91_GPIO | PIN_INPUT_PULLUP, /* FORCE_SENSING_INT */
|
||||
GPIO92_GPIO | PIN_OUTPUT_LOW, /* FORCE_SENSING_RST */
|
||||
GPIO97_GPIO | PIN_OUTPUT_LOW, /* FORCE_SENSING_WU */
|
||||
|
||||
/* DiPro Sensor Interface */
|
||||
GPIO139_GPIO | PIN_INPUT_PULLUP, /* DIPRO_INT */
|
||||
|
||||
/* HAL SWITCH INTERFACE */
|
||||
GPIO145_GPIO | PIN_INPUT_PULLDOWN,/* HAL_SW */
|
||||
|
||||
/* Audio Amplifier Interface */
|
||||
GPIO149_GPIO | PIN_OUTPUT_LOW, /* VAUDIO_HF_EN */
|
||||
|
||||
/* GBF INTERFACE */
|
||||
GPIO171_GPIO | PIN_OUTPUT_LOW, /* GBF_ENA_RESET */
|
||||
|
||||
/* MSP : HDTV INTERFACE */
|
||||
GPIO192_GPIO | PIN_INPUT_PULLDOWN,
|
||||
|
||||
/* ACCELEROMETER_INTERFACE */
|
||||
GPIO82_GPIO | PIN_INPUT_PULLUP, /* ACC_INT1 */
|
||||
GPIO83_GPIO | PIN_INPUT_PULLUP, /* ACC_INT2 */
|
||||
|
||||
/* Proximity Sensor */
|
||||
GPIO217_GPIO | PIN_INPUT_PULLUP,
|
||||
|
||||
|
||||
/*
|
||||
* The HREFv60 series of platforms is using available pins on the DB8500
|
||||
* insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
|
||||
* and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
|
||||
*/
|
||||
static struct pinctrl_map __initdata hrefv60_pinmap[] = {
|
||||
/* Drive WLAN_ENA low */
|
||||
DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
|
||||
/*
|
||||
* XENON Flashgun on image processor GPIO (controlled from image
|
||||
* processor firmware), mux in these image processor GPIO lines 0
|
||||
* (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
|
||||
* LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
|
||||
* from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
|
||||
*/
|
||||
DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
|
||||
DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
|
||||
DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
|
||||
DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
|
||||
DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
|
||||
DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
|
||||
DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
|
||||
/* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
|
||||
DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
|
||||
DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
|
||||
/*
|
||||
* Display Interface 1 uses GPIO 65 for RST (reset).
|
||||
* Display Interface 2 uses GPIO 66 for RST (reset).
|
||||
* Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
|
||||
*/
|
||||
DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
|
||||
DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
|
||||
/*
|
||||
* Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
|
||||
* GPIO 67 for interrupts. Pull-up the IRQ line and drive both
|
||||
* reset signals low.
|
||||
*/
|
||||
DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
|
||||
DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
|
||||
DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
|
||||
/*
|
||||
* Drive D19-D23 for the ETM PTM trace interface low,
|
||||
* (presumably pins are unconnected therefore grounded here,
|
||||
* the "other alt C1" setting enables these pins)
|
||||
*/
|
||||
DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
|
||||
DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
|
||||
DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
|
||||
DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
|
||||
DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
|
||||
/* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
|
||||
DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
|
||||
DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
|
||||
/* NFC ENA and RESET to low, pulldown IRQ line */
|
||||
DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
|
||||
DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
|
||||
DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
|
||||
/*
|
||||
* SKE keyboard partly on alt A and partly on "Other alt C1"
|
||||
* Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three
|
||||
* rows of 6 keys, then pull up force sensing interrup and
|
||||
* drive reset and force sensing WU low.
|
||||
*/
|
||||
DB8500_MUX_HOG("kp_a_1", "kp"),
|
||||
DB8500_MUX_HOG("kp_oc1_1", "kp"),
|
||||
DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */
|
||||
DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */
|
||||
DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */
|
||||
DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */
|
||||
DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */
|
||||
DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */
|
||||
DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */
|
||||
DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */
|
||||
DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
|
||||
DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
|
||||
DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
|
||||
/* DiPro Sensor interrupt */
|
||||
DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
|
||||
/* Audio Amplifier HF enable */
|
||||
DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
|
||||
/* GBF interface, pull low to reset state */
|
||||
DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
|
||||
/* MSP : HDTV INTERFACE GPIO line */
|
||||
DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
|
||||
/* Accelerometer interrupt lines */
|
||||
DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
|
||||
DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
|
||||
/* SD card detect GPIO pin */
|
||||
DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu),
|
||||
/*
|
||||
* Runtime stuff
|
||||
* Pull up/down of some sensor GPIO pins, for proximity, HAL sensor
|
||||
* etc.
|
||||
*/
|
||||
DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
|
||||
DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
|
||||
DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
|
||||
/*
|
||||
* Make it possible to mux in the SKE keypad and bias the pins
|
||||
* FIXME: what's the point with this on HREFv60? KP/SKE is already
|
||||
* muxed in at another place! Enabling this will bork.
|
||||
*/
|
||||
DB8500_MUX("kp_a_2", "kp", "ske"),
|
||||
DB8500_PIN("GPIO153_B17", in_pd_slpm_in_pu, "ske"), /* I7 */
|
||||
DB8500_PIN("GPIO154_C16", in_pd_slpm_in_pu, "ske"), /* I6 */
|
||||
DB8500_PIN("GPIO155_C19", in_pd_slpm_in_pu, "ske"), /* I5 */
|
||||
DB8500_PIN("GPIO156_C17", in_pd_slpm_in_pu, "ske"), /* I4 */
|
||||
DB8500_PIN("GPIO161_D21", in_pd_slpm_in_pu, "ske"), /* I3 */
|
||||
DB8500_PIN("GPIO162_D20", in_pd_slpm_in_pu, "ske"), /* I2 */
|
||||
DB8500_PIN("GPIO163_C20", in_pd_slpm_in_pu, "ske"), /* I1 */
|
||||
DB8500_PIN("GPIO164_B21", in_pd_slpm_in_pu, "ske"), /* I0 */
|
||||
DB8500_PIN("GPIO157_A18", in_pu_slpm_out_lo, "ske"), /* O7 */
|
||||
DB8500_PIN("GPIO158_C18", in_pu_slpm_out_lo, "ske"), /* O6 */
|
||||
DB8500_PIN("GPIO159_B19", in_pu_slpm_out_lo, "ske"), /* O5 */
|
||||
DB8500_PIN("GPIO160_B20", in_pu_slpm_out_lo, "ske"), /* O4 */
|
||||
DB8500_PIN("GPIO165_C21", in_pu_slpm_out_lo, "ske"), /* O3 */
|
||||
DB8500_PIN("GPIO166_A22", in_pu_slpm_out_lo, "ske"), /* O2 */
|
||||
DB8500_PIN("GPIO167_B24", in_pu_slpm_out_lo, "ske"), /* O1 */
|
||||
DB8500_PIN("GPIO168_C22", in_pu_slpm_out_lo, "ske"), /* O0 */
|
||||
};
|
||||
|
||||
static pin_cfg_t snowball_pins[] = {
|
||||
/* SSP0, to AB8500 */
|
||||
GPIO143_SSP0_CLK,
|
||||
GPIO144_SSP0_FRM,
|
||||
GPIO145_SSP0_RXD | PIN_PULL_DOWN,
|
||||
GPIO146_SSP0_TXD,
|
||||
|
||||
/* MMC0: MicroSD card */
|
||||
GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH,
|
||||
|
||||
/* MMC2: LAN */
|
||||
GPIO86_SM_ADQ0,
|
||||
GPIO87_SM_ADQ1,
|
||||
GPIO88_SM_ADQ2,
|
||||
GPIO89_SM_ADQ3,
|
||||
GPIO90_SM_ADQ4,
|
||||
GPIO91_SM_ADQ5,
|
||||
GPIO92_SM_ADQ6,
|
||||
GPIO93_SM_ADQ7,
|
||||
|
||||
GPIO94_SM_ADVn,
|
||||
GPIO95_SM_CS0n,
|
||||
GPIO96_SM_OEn,
|
||||
GPIO97_SM_WEn,
|
||||
|
||||
GPIO128_SM_CKO,
|
||||
GPIO130_SM_FBCLK,
|
||||
GPIO131_SM_ADQ8,
|
||||
GPIO132_SM_ADQ9,
|
||||
GPIO133_SM_ADQ10,
|
||||
GPIO134_SM_ADQ11,
|
||||
GPIO135_SM_ADQ12,
|
||||
GPIO136_SM_ADQ13,
|
||||
GPIO137_SM_ADQ14,
|
||||
GPIO138_SM_ADQ15,
|
||||
|
||||
/* RSTn_LAN */
|
||||
GPIO141_GPIO | PIN_OUTPUT_HIGH,
|
||||
static struct pinctrl_map __initdata u9500_pinmap[] = {
|
||||
/* Mux in UART1 (just RX/TX) and set the pull-ups */
|
||||
DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
|
||||
DB8500_PIN_HOG("GPIO4_AH6", in_pu),
|
||||
DB8500_PIN_HOG("GPIO5_AG6", out_hi),
|
||||
/* WLAN_IRQ line */
|
||||
DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
|
||||
/* HSI */
|
||||
DB8500_MUX_HOG("hsir_a_1", "hsi"),
|
||||
DB8500_MUX_HOG("hsit_a_1", "hsi"),
|
||||
DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
|
||||
DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
|
||||
DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
|
||||
DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
|
||||
DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
|
||||
DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
|
||||
DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
|
||||
DB8500_PIN_HOG("GPIO226_AF8", out_hi), /* ACWAKE0 */
|
||||
};
|
||||
|
||||
void __init mop500_pins_init(void)
|
||||
static struct pinctrl_map __initdata u8500_pinmap[] = {
|
||||
DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
|
||||
DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
|
||||
};
|
||||
|
||||
static struct pinctrl_map __initdata snowball_pinmap[] = {
|
||||
/* Mux in SSP0 connected to AB8500, pull down RXD pin */
|
||||
DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
|
||||
DB8500_PIN_HOG("GPIO145_C13", pd),
|
||||
/* Always drive the MC0 DAT31DIR line high on these boards */
|
||||
DB8500_PIN_HOG("GPIO21_AB3", out_hi),
|
||||
/* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
|
||||
DB8500_MUX_HOG("sm_b_1", "sm"),
|
||||
/* Drive RSTn_LAN high */
|
||||
DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
|
||||
/* Accelerometer/Magnetometer */
|
||||
DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
|
||||
DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
|
||||
DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
|
||||
/* WLAN/GBF */
|
||||
DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
|
||||
DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
|
||||
DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
|
||||
DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
|
||||
};
|
||||
|
||||
/*
|
||||
* passing "pinsfor=" in kernel cmdline allows for custom
|
||||
* configuration of GPIOs on u8500 derived boards.
|
||||
*/
|
||||
static int __init early_pinsfor(char *p)
|
||||
{
|
||||
nmk_config_pins(mop500_pins_common,
|
||||
ARRAY_SIZE(mop500_pins_common));
|
||||
pinsfor = PINS_FOR_DEFAULT;
|
||||
|
||||
nmk_config_pins(mop500_pins_default,
|
||||
ARRAY_SIZE(mop500_pins_default));
|
||||
if (strcmp(p, "u9500-21") == 0)
|
||||
pinsfor = PINS_FOR_U9500;
|
||||
|
||||
return 0;
|
||||
}
|
||||
early_param("pinsfor", early_pinsfor);
|
||||
|
||||
int pins_for_u9500(void)
|
||||
{
|
||||
if (pinsfor == PINS_FOR_U9500)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __init snowball_pins_init(void)
|
||||
static void __init mop500_href_family_pinmaps_init(void)
|
||||
{
|
||||
nmk_config_pins(mop500_pins_common,
|
||||
ARRAY_SIZE(mop500_pins_common));
|
||||
|
||||
nmk_config_pins(snowball_pins,
|
||||
ARRAY_SIZE(snowball_pins));
|
||||
switch (pinsfor) {
|
||||
case PINS_FOR_U9500:
|
||||
pinctrl_register_mappings(u9500_pinmap,
|
||||
ARRAY_SIZE(u9500_pinmap));
|
||||
break;
|
||||
case PINS_FOR_DEFAULT:
|
||||
pinctrl_register_mappings(u8500_pinmap,
|
||||
ARRAY_SIZE(u8500_pinmap));
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void __init hrefv60_pins_init(void)
|
||||
void __init mop500_pinmaps_init(void)
|
||||
{
|
||||
nmk_config_pins(mop500_pins_common,
|
||||
ARRAY_SIZE(mop500_pins_common));
|
||||
|
||||
nmk_config_pins(hrefv60_pins,
|
||||
ARRAY_SIZE(hrefv60_pins));
|
||||
pinctrl_register_mappings(mop500_family_pinmap,
|
||||
ARRAY_SIZE(mop500_family_pinmap));
|
||||
pinctrl_register_mappings(mop500_pinmap,
|
||||
ARRAY_SIZE(mop500_pinmap));
|
||||
mop500_href_family_pinmaps_init();
|
||||
}
|
||||
|
||||
void __init snowball_pinmaps_init(void)
|
||||
{
|
||||
pinctrl_register_mappings(mop500_family_pinmap,
|
||||
ARRAY_SIZE(mop500_family_pinmap));
|
||||
pinctrl_register_mappings(snowball_pinmap,
|
||||
ARRAY_SIZE(snowball_pinmap));
|
||||
pinctrl_register_mappings(u8500_pinmap,
|
||||
ARRAY_SIZE(u8500_pinmap));
|
||||
}
|
||||
|
||||
void __init hrefv60_pinmaps_init(void)
|
||||
{
|
||||
pinctrl_register_mappings(mop500_family_pinmap,
|
||||
ARRAY_SIZE(mop500_family_pinmap));
|
||||
pinctrl_register_mappings(hrefv60_pinmap,
|
||||
ARRAY_SIZE(hrefv60_pinmap));
|
||||
mop500_href_family_pinmaps_init();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
|
||||
/*
|
||||
* Copyright (C) 2008-2009 ST-Ericsson
|
||||
*
|
||||
|
|
@ -29,18 +30,17 @@
|
|||
#include <linux/smsc911x.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <linux/leds.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
#include <plat/i2c.h>
|
||||
#include <plat/ste_dma40.h>
|
||||
#include <plat/pincfg.h>
|
||||
#include <plat/gpio-nomadik.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
|
@ -48,11 +48,11 @@
|
|||
#include <mach/devices.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include "pins-db8500.h"
|
||||
#include "ste-dma40-db8500.h"
|
||||
#include "devices-db8500.h"
|
||||
#include "board-mop500.h"
|
||||
#include "board-mop500-regulators.h"
|
||||
#include "board-mop500-msp.h"
|
||||
|
||||
static struct gpio_led snowball_led_array[] = {
|
||||
{
|
||||
|
|
@ -520,14 +520,6 @@ static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
|
|||
};
|
||||
#endif
|
||||
|
||||
|
||||
static pin_cfg_t mop500_pins_uart0[] = {
|
||||
GPIO0_U0_CTSn | PIN_INPUT_PULLUP,
|
||||
GPIO1_U0_RTSn | PIN_OUTPUT_HIGH,
|
||||
GPIO2_U0_RXD | PIN_INPUT_PULLUP,
|
||||
GPIO3_U0_TXD | PIN_OUTPUT_HIGH,
|
||||
};
|
||||
|
||||
#define PRCC_K_SOFTRST_SET 0x18
|
||||
#define PRCC_K_SOFTRST_CLEAR 0x1C
|
||||
static void ux500_uart0_reset(void)
|
||||
|
|
@ -548,24 +540,33 @@ static void ux500_uart0_reset(void)
|
|||
udelay(1);
|
||||
}
|
||||
|
||||
/* This needs to be referenced by callbacks */
|
||||
struct pinctrl *u0_p;
|
||||
struct pinctrl_state *u0_def;
|
||||
struct pinctrl_state *u0_sleep;
|
||||
|
||||
static void ux500_uart0_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = nmk_config_pins(mop500_pins_uart0,
|
||||
ARRAY_SIZE(mop500_pins_uart0));
|
||||
if (ret < 0)
|
||||
pr_err("pl011: uart pins_enable failed\n");
|
||||
if (IS_ERR(u0_p) || IS_ERR(u0_def))
|
||||
return;
|
||||
|
||||
ret = pinctrl_select_state(u0_p, u0_def);
|
||||
if (ret)
|
||||
pr_err("could not set UART0 defstate\n");
|
||||
}
|
||||
|
||||
static void ux500_uart0_exit(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = nmk_config_pins_sleep(mop500_pins_uart0,
|
||||
ARRAY_SIZE(mop500_pins_uart0));
|
||||
if (ret < 0)
|
||||
pr_err("pl011: uart pins_disable failed\n");
|
||||
if (IS_ERR(u0_p) || IS_ERR(u0_sleep))
|
||||
return;
|
||||
|
||||
ret = pinctrl_select_state(u0_p, u0_sleep);
|
||||
if (ret)
|
||||
pr_err("could not set UART0 idlestate\n");
|
||||
}
|
||||
|
||||
static struct amba_pl011_data uart0_plat = {
|
||||
|
|
@ -597,7 +598,28 @@ static struct amba_pl011_data uart2_plat = {
|
|||
|
||||
static void __init mop500_uart_init(struct device *parent)
|
||||
{
|
||||
db8500_add_uart0(parent, &uart0_plat);
|
||||
struct amba_device *uart0_device;
|
||||
|
||||
uart0_device = db8500_add_uart0(parent, &uart0_plat);
|
||||
if (uart0_device) {
|
||||
u0_p = pinctrl_get(&uart0_device->dev);
|
||||
if (IS_ERR(u0_p))
|
||||
dev_err(&uart0_device->dev,
|
||||
"could not get UART0 pinctrl\n");
|
||||
else {
|
||||
u0_def = pinctrl_lookup_state(u0_p,
|
||||
PINCTRL_STATE_DEFAULT);
|
||||
if (IS_ERR(u0_def)) {
|
||||
dev_err(&uart0_device->dev,
|
||||
"could not get UART0 defstate\n");
|
||||
}
|
||||
u0_sleep = pinctrl_lookup_state(u0_p,
|
||||
PINCTRL_STATE_SLEEP);
|
||||
if (IS_ERR(u0_sleep))
|
||||
dev_err(&uart0_device->dev,
|
||||
"could not get UART0 idlestate\n");
|
||||
}
|
||||
}
|
||||
db8500_add_uart1(parent, &uart1_plat);
|
||||
db8500_add_uart2(parent, &uart2_plat);
|
||||
}
|
||||
|
|
@ -616,10 +638,9 @@ static void __init mop500_init_machine(void)
|
|||
|
||||
mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
|
||||
|
||||
mop500_pinmaps_init();
|
||||
parent = u8500_init_devices();
|
||||
|
||||
mop500_pins_init();
|
||||
|
||||
/* FIXME: parent of ab8500 should be prcmu */
|
||||
for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
|
||||
mop500_platform_devs[i]->dev.parent = parent;
|
||||
|
|
@ -630,6 +651,7 @@ static void __init mop500_init_machine(void)
|
|||
mop500_i2c_init(parent);
|
||||
mop500_sdi_init(parent);
|
||||
mop500_spi_init(parent);
|
||||
mop500_msp_init(parent);
|
||||
mop500_uart_init(parent);
|
||||
|
||||
i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
|
||||
|
|
@ -647,10 +669,9 @@ static void __init snowball_init_machine(void)
|
|||
struct device *parent = NULL;
|
||||
int i;
|
||||
|
||||
snowball_pinmaps_init();
|
||||
parent = u8500_init_devices();
|
||||
|
||||
snowball_pins_init();
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
|
||||
snowball_platform_devs[i]->dev.parent = parent;
|
||||
|
||||
|
|
@ -660,6 +681,7 @@ static void __init snowball_init_machine(void)
|
|||
mop500_i2c_init(parent);
|
||||
snowball_sdi_init(parent);
|
||||
mop500_spi_init(parent);
|
||||
mop500_msp_init(parent);
|
||||
mop500_uart_init(parent);
|
||||
|
||||
/* This board has full regulator constraints */
|
||||
|
|
@ -679,10 +701,9 @@ static void __init hrefv60_init_machine(void)
|
|||
*/
|
||||
mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
|
||||
|
||||
hrefv60_pinmaps_init();
|
||||
parent = u8500_init_devices();
|
||||
|
||||
hrefv60_pins_init();
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
|
||||
mop500_platform_devs[i]->dev.parent = parent;
|
||||
|
||||
|
|
@ -692,6 +713,7 @@ static void __init hrefv60_init_machine(void)
|
|||
mop500_i2c_init(parent);
|
||||
hrefv60_sdi_init(parent);
|
||||
mop500_spi_init(parent);
|
||||
mop500_msp_init(parent);
|
||||
mop500_uart_init(parent);
|
||||
|
||||
i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
|
||||
|
|
@ -739,10 +761,22 @@ MACHINE_END
|
|||
#ifdef CONFIG_MACH_UX500_DT
|
||||
|
||||
struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
|
||||
/* Requires DMA and call-back bindings. */
|
||||
OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
|
||||
OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
|
||||
OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
|
||||
/* Requires DMA bindings. */
|
||||
OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat),
|
||||
/* Requires clock name bindings. */
|
||||
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
|
||||
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
|
||||
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
|
||||
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL),
|
||||
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL),
|
||||
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL),
|
||||
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
|
||||
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
|
||||
OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
|
||||
{},
|
||||
};
|
||||
|
||||
|
|
@ -759,6 +793,14 @@ static void __init u8500_init_machine(void)
|
|||
int i2c0_devs;
|
||||
int i;
|
||||
|
||||
/* Pinmaps must be in place before devices register */
|
||||
if (of_machine_is_compatible("st-ericsson,mop500"))
|
||||
mop500_pinmaps_init();
|
||||
else if (of_machine_is_compatible("calaosystems,snowball-a9500"))
|
||||
snowball_pinmaps_init();
|
||||
else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
|
||||
hrefv60_pinmaps_init();
|
||||
|
||||
parent = u8500_init_devices();
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
|
||||
|
|
@ -771,7 +813,6 @@ static void __init u8500_init_machine(void)
|
|||
|
||||
if (of_machine_is_compatible("st-ericsson,mop500")) {
|
||||
mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
|
||||
mop500_pins_init();
|
||||
|
||||
platform_add_devices(mop500_platform_devs,
|
||||
ARRAY_SIZE(mop500_platform_devs));
|
||||
|
|
@ -784,7 +825,6 @@ static void __init u8500_init_machine(void)
|
|||
ARRAY_SIZE(mop500_i2c2_devices));
|
||||
|
||||
} else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
|
||||
snowball_pins_init();
|
||||
platform_add_devices(snowball_platform_devs,
|
||||
ARRAY_SIZE(snowball_platform_devs));
|
||||
|
||||
|
|
@ -796,7 +836,6 @@ static void __init u8500_init_machine(void)
|
|||
* instead.
|
||||
*/
|
||||
mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
|
||||
hrefv60_pins_init();
|
||||
platform_add_devices(mop500_platform_devs,
|
||||
ARRAY_SIZE(mop500_platform_devs));
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,9 @@
|
|||
#ifndef __BOARD_MOP500_H
|
||||
#define __BOARD_MOP500_H
|
||||
|
||||
/* For NOMADIK_NR_GPIO */
|
||||
#include <mach/irqs.h>
|
||||
|
||||
/* Snowball specific GPIO assignments, this board has no GPIO expander */
|
||||
#define SNOWBALL_ACCEL_INT1_GPIO 163
|
||||
#define SNOWBALL_ACCEL_INT2_GPIO 164
|
||||
|
|
@ -73,6 +76,7 @@
|
|||
#define SNOWBALL_PME_ETH_GPIO MOP500_AB8500_PIN_GPIO(24) /* SYSCLKREQ7/GPIO24 */
|
||||
#define SNOWBALL_EN_3V3_ETH_GPIO MOP500_AB8500_PIN_GPIO(26) /* GPIO26 */
|
||||
|
||||
struct device;
|
||||
struct i2c_board_info;
|
||||
|
||||
extern void mop500_sdi_init(struct device *parent);
|
||||
|
|
@ -81,9 +85,9 @@ extern void hrefv60_sdi_init(struct device *parent);
|
|||
extern void mop500_sdi_tc35892_init(struct device *parent);
|
||||
void __init mop500_u8500uib_init(void);
|
||||
void __init mop500_stuib_init(void);
|
||||
void __init mop500_pins_init(void);
|
||||
void __init hrefv60_pins_init(void);
|
||||
void __init snowball_pins_init(void);
|
||||
void __init mop500_pinmaps_init(void);
|
||||
void __init snowball_pinmaps_init(void);
|
||||
void __init hrefv60_pinmaps_init(void);
|
||||
|
||||
void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
|
||||
unsigned n);
|
||||
|
|
|
|||
|
|
@ -334,6 +334,7 @@ static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */
|
|||
*/
|
||||
|
||||
/* Peripheral Cluster #1 */
|
||||
static DEFINE_PRCC_CLK(1, msp3, 11, 10, &clk_msp1clk);
|
||||
static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk);
|
||||
static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL);
|
||||
static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk);
|
||||
|
|
@ -403,7 +404,7 @@ static struct clk_lookup u8500_clks[] = {
|
|||
CLK(slimbus0, "slimbus0", NULL),
|
||||
CLK(i2c2, "nmk-i2c.2", NULL),
|
||||
CLK(sdi0, "sdi0", NULL),
|
||||
CLK(msp0, "msp0", NULL),
|
||||
CLK(msp0, "ux500-msp-i2s.0", NULL),
|
||||
CLK(i2c1, "nmk-i2c.1", NULL),
|
||||
CLK(uart1, "uart1", NULL),
|
||||
CLK(uart0, "uart0", NULL),
|
||||
|
|
@ -453,7 +454,8 @@ static struct clk_lookup u8500_clks[] = {
|
|||
/* Peripheral Cluster #1 */
|
||||
CLK(i2c4, "nmk-i2c.4", NULL),
|
||||
CLK(spi3, "spi3", NULL),
|
||||
CLK(msp1, "msp1", NULL),
|
||||
CLK(msp1, "ux500-msp-i2s.1", NULL),
|
||||
CLK(msp3, "ux500-msp-i2s.3", NULL),
|
||||
|
||||
/* Peripheral Cluster #2 */
|
||||
CLK(gpio1, "gpio.6", NULL),
|
||||
|
|
@ -463,7 +465,7 @@ static struct clk_lookup u8500_clks[] = {
|
|||
CLK(spi0, "spi0", NULL),
|
||||
CLK(sdi3, "sdi3", NULL),
|
||||
CLK(sdi1, "sdi1", NULL),
|
||||
CLK(msp2, "msp2", NULL),
|
||||
CLK(msp2, "ux500-msp-i2s.2", NULL),
|
||||
CLK(sdi4, "sdi4", NULL),
|
||||
CLK(pwl, "pwl", NULL),
|
||||
CLK(spi1, "spi1", NULL),
|
||||
|
|
|
|||
|
|
@ -163,6 +163,7 @@ static void __init db8500_add_gpios(struct device *parent)
|
|||
|
||||
dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
|
||||
IRQ_DB8500_GPIO0, &pdata);
|
||||
dbx500_add_pinctrl(parent, "pinctrl-db8500");
|
||||
}
|
||||
|
||||
static int usb_db8500_rx_dma_cfg[] = {
|
||||
|
|
|
|||
|
|
@ -29,6 +29,18 @@
|
|||
|
||||
void __iomem *_PRCMU_BASE;
|
||||
|
||||
/*
|
||||
* FIXME: Should we set up the GPIO domain here?
|
||||
*
|
||||
* The problem is that we cannot put the interrupt resources into the platform
|
||||
* device until the irqdomain has been added. Right now, we set the GIC interrupt
|
||||
* domain from init_irq(), then load the gpio driver from
|
||||
* core_initcall(nmk_gpio_init) and add the platform devices from
|
||||
* arch_initcall(customize_machine).
|
||||
*
|
||||
* This feels fragile because it depends on the gpio device getting probed
|
||||
* _before_ any device uses the gpio interrupts.
|
||||
*/
|
||||
static const struct of_device_id ux500_dt_irq_match[] = {
|
||||
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
|
||||
{},
|
||||
|
|
|
|||
|
|
@ -90,4 +90,16 @@ struct nmk_gpio_platform_data;
|
|||
void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num,
|
||||
int irq, struct nmk_gpio_platform_data *pdata);
|
||||
|
||||
static inline void
|
||||
dbx500_add_pinctrl(struct device *parent, const char *name)
|
||||
{
|
||||
struct platform_device_info pdevinfo = {
|
||||
.parent = parent,
|
||||
.name = name,
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
platform_device_register_full(&pdevinfo);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -34,7 +34,6 @@ db8500_add_ssp(struct device *parent, const char *name, resource_size_t base,
|
|||
return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0);
|
||||
}
|
||||
|
||||
|
||||
#define db8500_add_i2c0(parent, pdata) \
|
||||
dbx500_add_i2c(parent, 0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata)
|
||||
#define db8500_add_i2c1(parent, pdata) \
|
||||
|
|
@ -46,15 +45,6 @@ db8500_add_ssp(struct device *parent, const char *name, resource_size_t base,
|
|||
#define db8500_add_i2c4(parent, pdata) \
|
||||
dbx500_add_i2c(parent, 4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata)
|
||||
|
||||
#define db8500_add_msp0_i2s(parent, pdata) \
|
||||
dbx500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata)
|
||||
#define db8500_add_msp1_i2s(parent, pdata) \
|
||||
dbx500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata)
|
||||
#define db8500_add_msp2_i2s(parent, pdata) \
|
||||
dbx500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata)
|
||||
#define db8500_add_msp3_i2s(parent, pdata) \
|
||||
dbx500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata)
|
||||
|
||||
#define db8500_add_msp0_spi(parent, pdata) \
|
||||
dbx500_add_msp_spi(parent, "msp0", U8500_MSP0_BASE, \
|
||||
IRQ_DB8500_MSP0, pdata)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Copyright (C) ST-Ericsson SA 2010
|
||||
*
|
||||
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
|
||||
* License terms: GNU General Public License (GPL), version 2.
|
||||
*/
|
||||
|
||||
#ifndef __MSP_H
|
||||
#define __MSP_H
|
||||
|
||||
#include <plat/ste_dma40.h>
|
||||
|
||||
enum msp_i2s_id {
|
||||
MSP_I2S_0 = 0,
|
||||
MSP_I2S_1,
|
||||
MSP_I2S_2,
|
||||
MSP_I2S_3,
|
||||
};
|
||||
|
||||
/* Platform data structure for a MSP I2S-device */
|
||||
struct msp_i2s_platform_data {
|
||||
enum msp_i2s_id id;
|
||||
struct stedma40_chan_cfg *msp_i2s_dma_rx;
|
||||
struct stedma40_chan_cfg *msp_i2s_dma_tx;
|
||||
int (*msp_i2s_init) (void);
|
||||
int (*msp_i2s_exit) (void);
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -35,40 +35,40 @@
|
|||
|
||||
#define GPIO4_GPIO PIN_CFG(4, GPIO)
|
||||
#define GPIO4_U1_RXD PIN_CFG(4, ALT_A)
|
||||
#define GPIO4_I2C4_SCL PIN_CFG_INPUT(4, ALT_B, PULLUP)
|
||||
#define GPIO4_I2C4_SCL PIN_CFG(4, ALT_B)
|
||||
#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C)
|
||||
|
||||
#define GPIO5_GPIO PIN_CFG(5, GPIO)
|
||||
#define GPIO5_U1_TXD PIN_CFG(5, ALT_A)
|
||||
#define GPIO5_I2C4_SDA PIN_CFG_INPUT(5, ALT_B, PULLUP)
|
||||
#define GPIO5_I2C4_SDA PIN_CFG(5, ALT_B)
|
||||
#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C)
|
||||
|
||||
#define GPIO6_GPIO PIN_CFG(6, GPIO)
|
||||
#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A)
|
||||
#define GPIO6_I2C1_SCL PIN_CFG_INPUT(6, ALT_B, PULLUP)
|
||||
#define GPIO6_I2C1_SCL PIN_CFG(6, ALT_B)
|
||||
#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C)
|
||||
|
||||
#define GPIO7_GPIO PIN_CFG(7, GPIO)
|
||||
#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A)
|
||||
#define GPIO7_I2C1_SDA PIN_CFG_INPUT(7, ALT_B, PULLUP)
|
||||
#define GPIO7_I2C1_SDA PIN_CFG(7, ALT_B)
|
||||
#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C)
|
||||
|
||||
#define GPIO8_GPIO PIN_CFG(8, GPIO)
|
||||
#define GPIO8_IPI2C_SDA PIN_CFG_INPUT(8, ALT_A, PULLUP)
|
||||
#define GPIO8_I2C2_SDA PIN_CFG_INPUT(8, ALT_B, PULLUP)
|
||||
#define GPIO8_IPI2C_SDA PIN_CFG(8, ALT_A)
|
||||
#define GPIO8_I2C2_SDA PIN_CFG(8, ALT_B)
|
||||
|
||||
#define GPIO9_GPIO PIN_CFG(9, GPIO)
|
||||
#define GPIO9_IPI2C_SCL PIN_CFG_INPUT(9, ALT_A, PULLUP)
|
||||
#define GPIO9_I2C2_SCL PIN_CFG_INPUT(9, ALT_B, PULLUP)
|
||||
#define GPIO9_IPI2C_SCL PIN_CFG(9, ALT_A)
|
||||
#define GPIO9_I2C2_SCL PIN_CFG(9, ALT_B)
|
||||
|
||||
#define GPIO10_GPIO PIN_CFG(10, GPIO)
|
||||
#define GPIO10_IPI2C_SDA PIN_CFG_INPUT(10, ALT_A, PULLUP)
|
||||
#define GPIO10_I2C2_SDA PIN_CFG_INPUT(10, ALT_B, PULLUP)
|
||||
#define GPIO10_IPI2C_SDA PIN_CFG(10, ALT_A)
|
||||
#define GPIO10_I2C2_SDA PIN_CFG(10, ALT_B)
|
||||
#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C)
|
||||
|
||||
#define GPIO11_GPIO PIN_CFG(11, GPIO)
|
||||
#define GPIO11_IPI2C_SCL PIN_CFG_INPUT(11, ALT_A, PULLUP)
|
||||
#define GPIO11_I2C2_SCL PIN_CFG_INPUT(11, ALT_B, PULLUP)
|
||||
#define GPIO11_IPI2C_SCL PIN_CFG(11, ALT_A)
|
||||
#define GPIO11_I2C2_SCL PIN_CFG(11, ALT_B)
|
||||
#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C)
|
||||
|
||||
#define GPIO12_GPIO PIN_CFG(12, GPIO)
|
||||
|
|
@ -87,12 +87,12 @@
|
|||
|
||||
#define GPIO16_GPIO PIN_CFG(16, GPIO)
|
||||
#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A)
|
||||
#define GPIO16_I2C1_SCL PIN_CFG_INPUT(16, ALT_B, PULLUP)
|
||||
#define GPIO16_I2C1_SCL PIN_CFG(16, ALT_B)
|
||||
#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C)
|
||||
|
||||
#define GPIO17_GPIO PIN_CFG(17, GPIO)
|
||||
#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A)
|
||||
#define GPIO17_I2C1_SDA PIN_CFG_INPUT(17, ALT_B, PULLUP)
|
||||
#define GPIO17_I2C1_SDA PIN_CFG(17, ALT_B)
|
||||
#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C)
|
||||
|
||||
#define GPIO18_GPIO PIN_CFG(18, GPIO)
|
||||
|
|
@ -434,10 +434,10 @@
|
|||
#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A)
|
||||
|
||||
#define GPIO147_GPIO PIN_CFG(147, GPIO)
|
||||
#define GPIO147_I2C0_SCL PIN_CFG_INPUT(147, ALT_A, PULLUP)
|
||||
#define GPIO147_I2C0_SCL PIN_CFG(147, ALT_A)
|
||||
|
||||
#define GPIO148_GPIO PIN_CFG(148, GPIO)
|
||||
#define GPIO148_I2C0_SDA PIN_CFG_INPUT(148, ALT_A, PULLUP)
|
||||
#define GPIO148_I2C0_SDA PIN_CFG(148, ALT_A)
|
||||
|
||||
#define GPIO149_GPIO PIN_CFG(149, GPIO)
|
||||
#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A)
|
||||
|
|
@ -459,82 +459,82 @@
|
|||
#define GPIO152_KP_O9 PIN_CFG(152, ALT_C)
|
||||
|
||||
#define GPIO153_GPIO PIN_CFG(153, GPIO)
|
||||
#define GPIO153_KP_I7 PIN_CFG_INPUT(153, ALT_A, PULLDOWN)
|
||||
#define GPIO153_KP_I7 PIN_CFG(153, ALT_A)
|
||||
#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B)
|
||||
#define GPIO153_U2_RXD PIN_CFG(153, ALT_C)
|
||||
|
||||
#define GPIO154_GPIO PIN_CFG(154, GPIO)
|
||||
#define GPIO154_KP_I6 PIN_CFG_INPUT(154, ALT_A, PULLDOWN)
|
||||
#define GPIO154_KP_I6 PIN_CFG(154, ALT_A)
|
||||
#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B)
|
||||
#define GPIO154_U2_TXD PIN_CFG(154, ALT_C)
|
||||
|
||||
#define GPIO155_GPIO PIN_CFG(155, GPIO)
|
||||
#define GPIO155_KP_I5 PIN_CFG_INPUT(155, ALT_A, PULLDOWN)
|
||||
#define GPIO155_KP_I5 PIN_CFG(155, ALT_A)
|
||||
#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B)
|
||||
#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C)
|
||||
|
||||
#define GPIO156_GPIO PIN_CFG(156, GPIO)
|
||||
#define GPIO156_KP_I4 PIN_CFG_INPUT(156, ALT_A, PULLDOWN)
|
||||
#define GPIO156_KP_I4 PIN_CFG(156, ALT_A)
|
||||
#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B)
|
||||
#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C)
|
||||
|
||||
#define GPIO157_GPIO PIN_CFG(157, GPIO)
|
||||
#define GPIO157_KP_O7 PIN_CFG_INPUT(157, ALT_A, PULLUP)
|
||||
#define GPIO157_KP_O7 PIN_CFG(157, ALT_A)
|
||||
#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B)
|
||||
#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C)
|
||||
|
||||
#define GPIO158_GPIO PIN_CFG(158, GPIO)
|
||||
#define GPIO158_KP_O6 PIN_CFG_INPUT(158, ALT_A, PULLUP)
|
||||
#define GPIO158_KP_O6 PIN_CFG(158, ALT_A)
|
||||
#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B)
|
||||
#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C)
|
||||
|
||||
#define GPIO159_GPIO PIN_CFG(159, GPIO)
|
||||
#define GPIO159_KP_O5 PIN_CFG_INPUT(159, ALT_A, PULLUP)
|
||||
#define GPIO159_KP_O5 PIN_CFG(159, ALT_A)
|
||||
#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B)
|
||||
#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C)
|
||||
|
||||
#define GPIO160_GPIO PIN_CFG(160, GPIO)
|
||||
#define GPIO160_KP_O4 PIN_CFG_INPUT(160, ALT_A, PULLUP)
|
||||
#define GPIO160_KP_O4 PIN_CFG(160, ALT_A)
|
||||
#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B)
|
||||
#define GPIO160_NONE PIN_CFG(160, ALT_C)
|
||||
|
||||
#define GPIO161_GPIO PIN_CFG(161, GPIO)
|
||||
#define GPIO161_KP_I3 PIN_CFG_INPUT(161, ALT_A, PULLDOWN)
|
||||
#define GPIO161_KP_I3 PIN_CFG(161, ALT_A)
|
||||
#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B)
|
||||
#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C)
|
||||
|
||||
#define GPIO162_GPIO PIN_CFG(162, GPIO)
|
||||
#define GPIO162_KP_I2 PIN_CFG_INPUT(162, ALT_A, PULLDOWN)
|
||||
#define GPIO162_KP_I2 PIN_CFG(162, ALT_A)
|
||||
#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B)
|
||||
#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C)
|
||||
|
||||
#define GPIO163_GPIO PIN_CFG(163, GPIO)
|
||||
#define GPIO163_KP_I1 PIN_CFG_INPUT(163, ALT_A, PULLDOWN)
|
||||
#define GPIO163_KP_I1 PIN_CFG(163, ALT_A)
|
||||
#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B)
|
||||
#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C)
|
||||
|
||||
#define GPIO164_GPIO PIN_CFG(164, GPIO)
|
||||
#define GPIO164_KP_I0 PIN_CFG_INPUT(164, ALT_A, PULLUP)
|
||||
#define GPIO164_KP_I0 PIN_CFG(164, ALT_A)
|
||||
#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B)
|
||||
#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C)
|
||||
|
||||
#define GPIO165_GPIO PIN_CFG(165, GPIO)
|
||||
#define GPIO165_KP_O3 PIN_CFG_INPUT(165, ALT_A, PULLUP)
|
||||
#define GPIO165_KP_O3 PIN_CFG(165, ALT_A)
|
||||
#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B)
|
||||
#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C)
|
||||
|
||||
#define GPIO166_GPIO PIN_CFG(166, GPIO)
|
||||
#define GPIO166_KP_O2 PIN_CFG_INPUT(166, ALT_A, PULLUP)
|
||||
#define GPIO166_KP_O2 PIN_CFG(166, ALT_A)
|
||||
#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B)
|
||||
#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C)
|
||||
|
||||
#define GPIO167_GPIO PIN_CFG(167, GPIO)
|
||||
#define GPIO167_KP_O1 PIN_CFG_INPUT(167, ALT_A, PULLUP)
|
||||
#define GPIO167_KP_O1 PIN_CFG(167, ALT_A)
|
||||
#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B)
|
||||
#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C)
|
||||
|
||||
#define GPIO168_GPIO PIN_CFG(168, GPIO)
|
||||
#define GPIO168_KP_O0 PIN_CFG_INPUT(168, ALT_A, PULLUP)
|
||||
#define GPIO168_KP_O0 PIN_CFG(168, ALT_A)
|
||||
#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B)
|
||||
#define GPIO168_NONE PIN_CFG(168, ALT_C)
|
||||
|
||||
|
|
@ -637,7 +637,7 @@
|
|||
#define GPIO216_GPIO PIN_CFG(216, GPIO)
|
||||
#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A)
|
||||
#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B)
|
||||
#define GPIO216_I2C3_SDA PIN_CFG_INPUT(216, ALT_C, PULLUP)
|
||||
#define GPIO216_I2C3_SDA PIN_CFG(216, ALT_C)
|
||||
#define GPIO216_SPI2_FRM PIN_CFG(216, ALT_C)
|
||||
|
||||
#define GPIO217_GPIO PIN_CFG(217, GPIO)
|
||||
|
|
@ -649,7 +649,7 @@
|
|||
#define GPIO218_GPIO PIN_CFG(218, GPIO)
|
||||
#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A)
|
||||
#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B)
|
||||
#define GPIO218_I2C3_SCL PIN_CFG_INPUT(218, ALT_C, PULLUP)
|
||||
#define GPIO218_I2C3_SCL PIN_CFG(218, ALT_C)
|
||||
#define GPIO218_SPI2_RXD PIN_CFG(218, ALT_C)
|
||||
|
||||
#define GPIO219_GPIO PIN_CFG(219, GPIO)
|
||||
|
|
@ -698,12 +698,12 @@
|
|||
#define GPIO229_GPIO PIN_CFG(229, GPIO)
|
||||
#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A)
|
||||
#define GPIO229_PWL PIN_CFG(229, ALT_B)
|
||||
#define GPIO229_I2C3_SDA PIN_CFG_INPUT(229, ALT_C, PULLUP)
|
||||
#define GPIO229_I2C3_SDA PIN_CFG(229, ALT_C)
|
||||
|
||||
#define GPIO230_GPIO PIN_CFG(230, GPIO)
|
||||
#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A)
|
||||
#define GPIO230_PWL PIN_CFG(230, ALT_B)
|
||||
#define GPIO230_I2C3_SCL PIN_CFG_INPUT(230, ALT_C, PULLUP)
|
||||
#define GPIO230_I2C3_SCL PIN_CFG(230, ALT_C)
|
||||
|
||||
#define GPIO256_GPIO PIN_CFG(256, GPIO)
|
||||
#define GPIO256_USB_NXT PIN_CFG(256, ALT_A)
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#define NMK_GPIO_SLPC 0x1c
|
||||
#define NMK_GPIO_AFSLA 0x20
|
||||
#define NMK_GPIO_AFSLB 0x24
|
||||
#define NMK_GPIO_LOWEMI 0x28
|
||||
|
||||
#define NMK_GPIO_RIMSC 0x40
|
||||
#define NMK_GPIO_FIMSC 0x44
|
||||
|
|
@ -61,7 +62,14 @@ enum nmk_gpio_slpm {
|
|||
|
||||
extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode);
|
||||
extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull);
|
||||
#ifdef CONFIG_PINCTRL_NOMADIK
|
||||
extern int nmk_gpio_set_mode(int gpio, int gpio_mode);
|
||||
#else
|
||||
static inline int nmk_gpio_set_mode(int gpio, int gpio_mode)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
extern int nmk_gpio_get_mode(int gpio);
|
||||
|
||||
extern void nmk_gpio_wakeups_suspend(void);
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
* bit 16..18 - SLPM pull up/down state
|
||||
* bit 19..20 - SLPM direction
|
||||
* bit 21..22 - SLPM Value (if output)
|
||||
* bit 23..25 - PDIS value (if input)
|
||||
*
|
||||
* to facilitate the definition, the following macros are provided
|
||||
*
|
||||
|
|
@ -67,6 +68,10 @@ typedef unsigned long pin_cfg_t;
|
|||
/* These two replace the above in DB8500v2+ */
|
||||
#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
|
||||
#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
|
||||
#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
|
||||
|
||||
#define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
|
||||
#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
|
||||
|
||||
#define PIN_DIR_SHIFT 14
|
||||
#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
|
||||
|
|
@ -105,6 +110,33 @@ typedef unsigned long pin_cfg_t;
|
|||
#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
|
||||
#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
|
||||
|
||||
#define PIN_SLPM_PDIS_SHIFT 23
|
||||
#define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
|
||||
#define PIN_SLPM_PDIS(x) \
|
||||
(((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
|
||||
#define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
|
||||
#define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
|
||||
#define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
|
||||
|
||||
#define PIN_LOWEMI_SHIFT 25
|
||||
#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
|
||||
#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
|
||||
#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
|
||||
#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
|
||||
|
||||
#define PIN_GPIOMODE_SHIFT 26
|
||||
#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
|
||||
#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
|
||||
#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
|
||||
#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
|
||||
|
||||
#define PIN_SLEEPMODE_SHIFT 27
|
||||
#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
|
||||
#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
|
||||
#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
|
||||
#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
|
||||
|
||||
|
||||
/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
|
||||
#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
|
||||
#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@ config ARCH_SPEAR3XX
|
|||
select ARM_VIC
|
||||
select CPU_ARM926T
|
||||
select USE_OF
|
||||
select PINCTRL
|
||||
help
|
||||
Supports for ARM's SPEAR3XX family
|
||||
|
||||
|
|
|
|||
|
|
@ -5,4 +5,4 @@
|
|||
# Common support
|
||||
obj-y := clock.o restart.o time.o pl080.o
|
||||
|
||||
obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o
|
||||
obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o
|
||||
|
|
|
|||
|
|
@ -1,92 +0,0 @@
|
|||
/*
|
||||
* arch/arm/plat-spear/include/plat/padmux.h
|
||||
*
|
||||
* SPEAr platform specific gpio pads muxing file
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_PADMUX_H
|
||||
#define __PLAT_PADMUX_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/*
|
||||
* struct pmx_reg: configuration structure for mode reg and mux reg
|
||||
*
|
||||
* offset: offset of mode reg
|
||||
* mask: mask of mode reg
|
||||
*/
|
||||
struct pmx_reg {
|
||||
u32 offset;
|
||||
u32 mask;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct pmx_dev_mode: configuration structure every group of modes of a device
|
||||
*
|
||||
* ids: all modes for this configuration
|
||||
* mask: mask for supported mode
|
||||
*/
|
||||
struct pmx_dev_mode {
|
||||
u32 ids;
|
||||
u32 mask;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct pmx_mode: mode definition structure
|
||||
*
|
||||
* name: mode name
|
||||
* mask: mode mask
|
||||
*/
|
||||
struct pmx_mode {
|
||||
char *name;
|
||||
u32 id;
|
||||
u32 mask;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct pmx_dev: device definition structure
|
||||
*
|
||||
* name: device name
|
||||
* modes: device configuration array for different modes supported
|
||||
* mode_count: size of modes array
|
||||
* is_active: is peripheral active/enabled
|
||||
* enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
|
||||
*/
|
||||
struct pmx_dev {
|
||||
char *name;
|
||||
struct pmx_dev_mode *modes;
|
||||
u8 mode_count;
|
||||
bool is_active;
|
||||
bool enb_on_reset;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct pmx_driver: driver definition structure
|
||||
*
|
||||
* mode: mode to be set
|
||||
* devs: array of pointer to pmx devices
|
||||
* devs_count: ARRAY_SIZE of devs
|
||||
* base: base address of soc config registers
|
||||
* mode_reg: structure of mode config register
|
||||
* mux_reg: structure of device mux config register
|
||||
*/
|
||||
struct pmx_driver {
|
||||
struct pmx_mode *mode;
|
||||
struct pmx_dev **devs;
|
||||
u8 devs_count;
|
||||
u32 *base;
|
||||
struct pmx_reg mode_reg;
|
||||
struct pmx_reg mux_reg;
|
||||
};
|
||||
|
||||
/* pmx functions */
|
||||
int pmx_register(struct pmx_driver *driver);
|
||||
|
||||
#endif /* __PLAT_PADMUX_H */
|
||||
|
|
@ -1,164 +0,0 @@
|
|||
/*
|
||||
* arch/arm/plat-spear/include/plat/padmux.c
|
||||
*
|
||||
* SPEAr platform specific gpio pads muxing source file
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
#include <plat/padmux.h>
|
||||
|
||||
/*
|
||||
* struct pmx: pmx definition structure
|
||||
*
|
||||
* base: base address of configuration registers
|
||||
* mode_reg: mode configurations
|
||||
* mux_reg: muxing configurations
|
||||
* active_mode: pointer to current active mode
|
||||
*/
|
||||
struct pmx {
|
||||
u32 base;
|
||||
struct pmx_reg mode_reg;
|
||||
struct pmx_reg mux_reg;
|
||||
struct pmx_mode *active_mode;
|
||||
};
|
||||
|
||||
static struct pmx *pmx;
|
||||
|
||||
/**
|
||||
* pmx_mode_set - Enables an multiplexing mode
|
||||
* @mode - pointer to pmx mode
|
||||
*
|
||||
* It will set mode of operation in hardware.
|
||||
* Returns -ve on Err otherwise 0
|
||||
*/
|
||||
static int pmx_mode_set(struct pmx_mode *mode)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (!mode->name)
|
||||
return -EFAULT;
|
||||
|
||||
pmx->active_mode = mode;
|
||||
|
||||
val = readl(pmx->base + pmx->mode_reg.offset);
|
||||
val &= ~pmx->mode_reg.mask;
|
||||
val |= mode->mask & pmx->mode_reg.mask;
|
||||
writel(val, pmx->base + pmx->mode_reg.offset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* pmx_devs_enable - Enables list of devices
|
||||
* @devs - pointer to pmx device array
|
||||
* @count - number of devices to enable
|
||||
*
|
||||
* It will enable pads for all required peripherals once and only once.
|
||||
* If peripheral is not supported by current mode then request is rejected.
|
||||
* Conflicts between peripherals are not handled and peripherals will be
|
||||
* enabled in the order they are present in pmx_dev array.
|
||||
* In case of conflicts last peripheral enabled will be present.
|
||||
* Returns -ve on Err otherwise 0
|
||||
*/
|
||||
static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
|
||||
{
|
||||
u32 val, i, mask;
|
||||
|
||||
if (!count)
|
||||
return -EINVAL;
|
||||
|
||||
val = readl(pmx->base + pmx->mux_reg.offset);
|
||||
for (i = 0; i < count; i++) {
|
||||
u8 j = 0;
|
||||
|
||||
if (!devs[i]->name || !devs[i]->modes) {
|
||||
printk(KERN_ERR "padmux: dev name or modes is null\n");
|
||||
continue;
|
||||
}
|
||||
/* check if peripheral exists in active mode */
|
||||
if (pmx->active_mode) {
|
||||
bool found = false;
|
||||
for (j = 0; j < devs[i]->mode_count; j++) {
|
||||
if (devs[i]->modes[j].ids &
|
||||
pmx->active_mode->id) {
|
||||
found = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (found == false) {
|
||||
printk(KERN_ERR "%s device not available in %s"\
|
||||
"mode\n", devs[i]->name,
|
||||
pmx->active_mode->name);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
/* enable peripheral */
|
||||
mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
|
||||
if (devs[i]->enb_on_reset)
|
||||
val &= ~mask;
|
||||
else
|
||||
val |= mask;
|
||||
|
||||
devs[i]->is_active = true;
|
||||
}
|
||||
writel(val, pmx->base + pmx->mux_reg.offset);
|
||||
kfree(pmx);
|
||||
|
||||
/* this will ensure that multiplexing can't be changed now */
|
||||
pmx = (struct pmx *)-1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* pmx_register - registers a platform requesting pad mux feature
|
||||
* @driver - pointer to driver structure containing driver specific parameters
|
||||
*
|
||||
* Also this must be called only once. This will allocate memory for pmx
|
||||
* structure, will call pmx_mode_set, will call pmx_devs_enable.
|
||||
* Returns -ve on Err otherwise 0
|
||||
*/
|
||||
int pmx_register(struct pmx_driver *driver)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (pmx)
|
||||
return -EPERM;
|
||||
if (!driver->base || !driver->devs)
|
||||
return -EFAULT;
|
||||
|
||||
pmx = kzalloc(sizeof(*pmx), GFP_KERNEL);
|
||||
if (!pmx)
|
||||
return -ENOMEM;
|
||||
|
||||
pmx->base = (u32)driver->base;
|
||||
pmx->mode_reg.offset = driver->mode_reg.offset;
|
||||
pmx->mode_reg.mask = driver->mode_reg.mask;
|
||||
pmx->mux_reg.offset = driver->mux_reg.offset;
|
||||
pmx->mux_reg.mask = driver->mux_reg.mask;
|
||||
|
||||
/* choose mode to enable */
|
||||
if (driver->mode) {
|
||||
ret = pmx_mode_set(driver->mode);
|
||||
if (ret)
|
||||
goto pmx_fail;
|
||||
}
|
||||
ret = pmx_devs_enable(driver->devs, driver->devs_count);
|
||||
if (ret)
|
||||
goto pmx_fail;
|
||||
|
||||
return 0;
|
||||
|
||||
pmx_fail:
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -37,7 +37,6 @@ obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o
|
|||
obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o
|
||||
obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
|
||||
obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o
|
||||
obj-$(CONFIG_PLAT_NOMADIK) += gpio-nomadik.o
|
||||
obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o
|
||||
obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o
|
||||
obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o
|
||||
|
|
|
|||
|
|
@ -26,10 +26,10 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include <mach/gpio-tegra.h>
|
||||
#include <mach/iomap.h>
|
||||
#include <mach/suspend.h>
|
||||
|
||||
|
|
@ -108,18 +108,29 @@ static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
|
|||
tegra_gpio_writel(val, reg);
|
||||
}
|
||||
|
||||
void tegra_gpio_enable(int gpio)
|
||||
static void tegra_gpio_enable(int gpio)
|
||||
{
|
||||
tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(tegra_gpio_enable);
|
||||
|
||||
void tegra_gpio_disable(int gpio)
|
||||
static void tegra_gpio_disable(int gpio)
|
||||
{
|
||||
tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(tegra_gpio_disable);
|
||||
|
||||
int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
return pinctrl_request_gpio(offset);
|
||||
}
|
||||
|
||||
void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
pinctrl_free_gpio(offset);
|
||||
tegra_gpio_disable(offset);
|
||||
}
|
||||
|
||||
static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
{
|
||||
tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
|
||||
|
|
@ -133,6 +144,7 @@ static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
|
|||
static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
|
||||
tegra_gpio_enable(offset);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -141,6 +153,7 @@ static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
|
|||
{
|
||||
tegra_gpio_set(chip, offset, value);
|
||||
tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
|
||||
tegra_gpio_enable(offset);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -151,13 +164,14 @@ static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
|
|||
|
||||
static struct gpio_chip tegra_gpio_chip = {
|
||||
.label = "tegra-gpio",
|
||||
.request = tegra_gpio_request,
|
||||
.free = tegra_gpio_free,
|
||||
.direction_input = tegra_gpio_direction_input,
|
||||
.get = tegra_gpio_get,
|
||||
.direction_output = tegra_gpio_direction_output,
|
||||
.set = tegra_gpio_set,
|
||||
.to_irq = tegra_gpio_to_irq,
|
||||
.base = 0,
|
||||
.ngpio = TEGRA_NR_GPIOS,
|
||||
};
|
||||
|
||||
static void tegra_gpio_irq_ack(struct irq_data *d)
|
||||
|
|
@ -224,6 +238,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
|
|||
|
||||
spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
|
||||
|
||||
tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
|
||||
tegra_gpio_enable(gpio);
|
||||
|
||||
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
|
||||
__irq_set_handler_locked(d->irq, handle_level_irq);
|
||||
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
|
||||
|
|
@ -490,20 +507,6 @@ static int __init tegra_gpio_init(void)
|
|||
}
|
||||
postcore_initcall(tegra_gpio_init);
|
||||
|
||||
void tegra_gpio_config(struct tegra_gpio_table *table, int num)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num; i++) {
|
||||
int gpio = table[i].gpio;
|
||||
|
||||
if (table[i].enable)
|
||||
tegra_gpio_enable(gpio);
|
||||
else
|
||||
tegra_gpio_disable(gpio);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
|
||||
#include <linux/debugfs.h>
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_i2c.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/hardware.h>
|
||||
|
|
@ -470,6 +471,7 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
|
|||
struct imx_i2c_struct *i2c_imx;
|
||||
struct resource *res;
|
||||
struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
|
||||
struct pinctrl *pinctrl;
|
||||
void __iomem *base;
|
||||
resource_size_t res_size;
|
||||
int irq, bitrate;
|
||||
|
|
@ -520,6 +522,12 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
|
|||
i2c_imx->base = base;
|
||||
i2c_imx->res = res;
|
||||
|
||||
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
||||
if (IS_ERR(pinctrl)) {
|
||||
ret = PTR_ERR(pinctrl);
|
||||
goto fail3;
|
||||
}
|
||||
|
||||
/* Get I2C clock */
|
||||
i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk");
|
||||
if (IS_ERR(i2c_imx->clk)) {
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
#include <mach/common.h>
|
||||
|
||||
|
|
@ -325,10 +326,15 @@ static int __devinit mxs_i2c_probe(struct platform_device *pdev)
|
|||
struct device *dev = &pdev->dev;
|
||||
struct mxs_i2c_dev *i2c;
|
||||
struct i2c_adapter *adap;
|
||||
struct pinctrl *pinctrl;
|
||||
struct resource *res;
|
||||
resource_size_t res_size;
|
||||
int err, irq;
|
||||
|
||||
pinctrl = devm_pinctrl_get_select_default(dev);
|
||||
if (IS_ERR(pinctrl))
|
||||
return PTR_ERR(pinctrl);
|
||||
|
||||
i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
|
||||
if (!i2c)
|
||||
return -ENOMEM;
|
||||
|
|
|
|||
|
|
@ -39,6 +39,7 @@
|
|||
#include <linux/regulator/consumer.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/fsl/mxs-dma.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
#include <mach/mxs.h>
|
||||
#include <mach/common.h>
|
||||
|
|
@ -682,6 +683,7 @@ static int mxs_mmc_probe(struct platform_device *pdev)
|
|||
struct mmc_host *mmc;
|
||||
struct resource *iores, *dmares, *r;
|
||||
struct mxs_mmc_platform_data *pdata;
|
||||
struct pinctrl *pinctrl;
|
||||
int ret = 0, irq_err, irq_dma;
|
||||
dma_cap_mask_t mask;
|
||||
|
||||
|
|
@ -719,6 +721,12 @@ static int mxs_mmc_probe(struct platform_device *pdev)
|
|||
host->irq = irq_err;
|
||||
host->sdio_irq_en = 0;
|
||||
|
||||
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
||||
if (IS_ERR(pinctrl)) {
|
||||
ret = PTR_ERR(pinctrl);
|
||||
goto out_iounmap;
|
||||
}
|
||||
|
||||
host->clk = clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(host->clk)) {
|
||||
ret = PTR_ERR(host->clk);
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <mach/esdhc.h>
|
||||
#include "sdhci-pltfm.h"
|
||||
#include "sdhci-esdhc.h"
|
||||
|
|
@ -68,6 +69,7 @@ struct pltfm_imx_data {
|
|||
int flags;
|
||||
u32 scratchpad;
|
||||
enum imx_esdhc_type devtype;
|
||||
struct pinctrl *pinctrl;
|
||||
struct esdhc_platform_data boarddata;
|
||||
};
|
||||
|
||||
|
|
@ -467,6 +469,12 @@ static int __devinit sdhci_esdhc_imx_probe(struct platform_device *pdev)
|
|||
clk_prepare_enable(clk);
|
||||
pltfm_host->clk = clk;
|
||||
|
||||
imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
||||
if (IS_ERR(imx_data->pinctrl)) {
|
||||
err = PTR_ERR(imx_data->pinctrl);
|
||||
goto pin_err;
|
||||
}
|
||||
|
||||
host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
|
||||
|
||||
if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
|
||||
|
|
@ -558,6 +566,7 @@ no_card_detect_irq:
|
|||
gpio_free(boarddata->wp_gpio);
|
||||
no_card_detect_pin:
|
||||
no_board_data:
|
||||
pin_err:
|
||||
clk_disable_unprepare(pltfm_host->clk);
|
||||
clk_put(pltfm_host->clk);
|
||||
err_clk_get:
|
||||
|
|
|
|||
|
|
@ -269,7 +269,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
|
|||
"failed to allocate power gpio\n");
|
||||
goto err_power_req;
|
||||
}
|
||||
tegra_gpio_enable(plat->power_gpio);
|
||||
gpio_direction_output(plat->power_gpio, 1);
|
||||
}
|
||||
|
||||
|
|
@ -280,7 +279,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
|
|||
"failed to allocate cd gpio\n");
|
||||
goto err_cd_req;
|
||||
}
|
||||
tegra_gpio_enable(plat->cd_gpio);
|
||||
gpio_direction_input(plat->cd_gpio);
|
||||
|
||||
rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq,
|
||||
|
|
@ -301,7 +299,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
|
|||
"failed to allocate wp gpio\n");
|
||||
goto err_wp_req;
|
||||
}
|
||||
tegra_gpio_enable(plat->wp_gpio);
|
||||
gpio_direction_input(plat->wp_gpio);
|
||||
}
|
||||
|
||||
|
|
@ -329,23 +326,17 @@ err_add_host:
|
|||
clk_disable(pltfm_host->clk);
|
||||
clk_put(pltfm_host->clk);
|
||||
err_clk_get:
|
||||
if (gpio_is_valid(plat->wp_gpio)) {
|
||||
tegra_gpio_disable(plat->wp_gpio);
|
||||
if (gpio_is_valid(plat->wp_gpio))
|
||||
gpio_free(plat->wp_gpio);
|
||||
}
|
||||
err_wp_req:
|
||||
if (gpio_is_valid(plat->cd_gpio))
|
||||
free_irq(gpio_to_irq(plat->cd_gpio), host);
|
||||
err_cd_irq_req:
|
||||
if (gpio_is_valid(plat->cd_gpio)) {
|
||||
tegra_gpio_disable(plat->cd_gpio);
|
||||
if (gpio_is_valid(plat->cd_gpio))
|
||||
gpio_free(plat->cd_gpio);
|
||||
}
|
||||
err_cd_req:
|
||||
if (gpio_is_valid(plat->power_gpio)) {
|
||||
tegra_gpio_disable(plat->power_gpio);
|
||||
if (gpio_is_valid(plat->power_gpio))
|
||||
gpio_free(plat->power_gpio);
|
||||
}
|
||||
err_power_req:
|
||||
err_no_plat:
|
||||
sdhci_pltfm_free(pdev);
|
||||
|
|
@ -362,21 +353,16 @@ static int __devexit sdhci_tegra_remove(struct platform_device *pdev)
|
|||
|
||||
sdhci_remove_host(host, dead);
|
||||
|
||||
if (gpio_is_valid(plat->wp_gpio)) {
|
||||
tegra_gpio_disable(plat->wp_gpio);
|
||||
if (gpio_is_valid(plat->wp_gpio))
|
||||
gpio_free(plat->wp_gpio);
|
||||
}
|
||||
|
||||
if (gpio_is_valid(plat->cd_gpio)) {
|
||||
free_irq(gpio_to_irq(plat->cd_gpio), host);
|
||||
tegra_gpio_disable(plat->cd_gpio);
|
||||
gpio_free(plat->cd_gpio);
|
||||
}
|
||||
|
||||
if (gpio_is_valid(plat->power_gpio)) {
|
||||
tegra_gpio_disable(plat->power_gpio);
|
||||
if (gpio_is_valid(plat->power_gpio))
|
||||
gpio_free(plat->power_gpio);
|
||||
}
|
||||
|
||||
clk_disable(pltfm_host->clk);
|
||||
clk_put(pltfm_host->clk);
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/mtd/gpmi-nand.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include "gpmi-nand.h"
|
||||
|
||||
/* add our owner bbt descriptor */
|
||||
|
|
@ -476,6 +477,7 @@ acquire_err:
|
|||
static int __devinit acquire_resources(struct gpmi_nand_data *this)
|
||||
{
|
||||
struct resources *res = &this->resources;
|
||||
struct pinctrl *pinctrl;
|
||||
int ret;
|
||||
|
||||
ret = acquire_register_block(this, GPMI_NAND_GPMI_REGS_ADDR_RES_NAME);
|
||||
|
|
@ -494,6 +496,12 @@ static int __devinit acquire_resources(struct gpmi_nand_data *this)
|
|||
if (ret)
|
||||
goto exit_dma_channels;
|
||||
|
||||
pinctrl = devm_pinctrl_get_select_default(&this->pdev->dev);
|
||||
if (IS_ERR(pinctrl)) {
|
||||
ret = PTR_ERR(pinctrl);
|
||||
goto exit_pin;
|
||||
}
|
||||
|
||||
res->clock = clk_get(&this->pdev->dev, NULL);
|
||||
if (IS_ERR(res->clock)) {
|
||||
pr_err("can not get the clock\n");
|
||||
|
|
@ -503,6 +511,7 @@ static int __devinit acquire_resources(struct gpmi_nand_data *this)
|
|||
return 0;
|
||||
|
||||
exit_clock:
|
||||
exit_pin:
|
||||
release_dma_channels(this);
|
||||
exit_dma_channels:
|
||||
release_bch_irq(this);
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
#define DRV_NAME "flexcan"
|
||||
|
||||
|
|
@ -927,11 +928,16 @@ static int __devinit flexcan_probe(struct platform_device *pdev)
|
|||
struct flexcan_priv *priv;
|
||||
struct resource *mem;
|
||||
struct clk *clk = NULL;
|
||||
struct pinctrl *pinctrl;
|
||||
void __iomem *base;
|
||||
resource_size_t mem_size;
|
||||
int err, irq;
|
||||
u32 clock_freq = 0;
|
||||
|
||||
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
||||
if (IS_ERR(pinctrl))
|
||||
return PTR_ERR(pinctrl);
|
||||
|
||||
if (pdev->dev.of_node) {
|
||||
const u32 *clock_freq_p;
|
||||
|
||||
|
|
|
|||
|
|
@ -48,6 +48,7 @@
|
|||
#include <linux/of_device.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <linux/of_net.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
|
|
@ -1543,6 +1544,7 @@ fec_probe(struct platform_device *pdev)
|
|||
struct resource *r;
|
||||
const struct of_device_id *of_id;
|
||||
static int dev_id;
|
||||
struct pinctrl *pinctrl;
|
||||
|
||||
of_id = of_match_device(fec_dt_ids, &pdev->dev);
|
||||
if (of_id)
|
||||
|
|
@ -1610,6 +1612,12 @@ fec_probe(struct platform_device *pdev)
|
|||
}
|
||||
}
|
||||
|
||||
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
||||
if (IS_ERR(pinctrl)) {
|
||||
ret = PTR_ERR(pinctrl);
|
||||
goto failed_pin;
|
||||
}
|
||||
|
||||
fep->clk = clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(fep->clk)) {
|
||||
ret = PTR_ERR(fep->clk);
|
||||
|
|
@ -1640,6 +1648,7 @@ failed_mii_init:
|
|||
failed_init:
|
||||
clk_disable_unprepare(fep->clk);
|
||||
clk_put(fep->clk);
|
||||
failed_pin:
|
||||
failed_clk:
|
||||
for (i = 0; i < FEC_IRQ_NUM; i++) {
|
||||
irq = platform_get_irq(pdev, i);
|
||||
|
|
|
|||
|
|
@ -80,6 +80,16 @@ config PINCTRL_IMX28
|
|||
select PINCONF
|
||||
select PINCTRL_MXS
|
||||
|
||||
config PINCTRL_NOMADIK
|
||||
bool "Nomadik pin controller driver"
|
||||
depends on ARCH_U8500 || ARCH_NOMADIK
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
|
||||
config PINCTRL_DB8500
|
||||
bool "DB8500 pin controller driver"
|
||||
depends on PINCTRL_NOMADIK && ARCH_U8500
|
||||
|
||||
config PINCTRL_PXA168
|
||||
bool "PXA168 pin controller driver"
|
||||
depends on ARCH_MMP
|
||||
|
|
@ -127,6 +137,8 @@ config PINCTRL_COH901
|
|||
COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
|
||||
ports of 8 GPIO pins each.
|
||||
|
||||
source "drivers/pinctrl/spear/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@ obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o
|
|||
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
|
||||
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
|
||||
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
|
||||
obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
|
||||
obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
|
||||
obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
|
||||
obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
|
||||
obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o
|
||||
|
|
@ -26,3 +28,5 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
|
|||
obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
|
||||
obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
|
||||
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
|
||||
|
||||
obj-$(CONFIG_PLAT_SPEAR) += spear/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,857 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include "pinctrl-nomadik.h"
|
||||
|
||||
/* All the pins that can be used for GPIO and some other functions */
|
||||
#define _GPIO(offset) (offset)
|
||||
|
||||
#define DB8500_PIN_AJ5 _GPIO(0)
|
||||
#define DB8500_PIN_AJ3 _GPIO(1)
|
||||
#define DB8500_PIN_AH4 _GPIO(2)
|
||||
#define DB8500_PIN_AH3 _GPIO(3)
|
||||
#define DB8500_PIN_AH6 _GPIO(4)
|
||||
#define DB8500_PIN_AG6 _GPIO(5)
|
||||
#define DB8500_PIN_AF6 _GPIO(6)
|
||||
#define DB8500_PIN_AG5 _GPIO(7)
|
||||
#define DB8500_PIN_AD5 _GPIO(8)
|
||||
#define DB8500_PIN_AE4 _GPIO(9)
|
||||
#define DB8500_PIN_AF5 _GPIO(10)
|
||||
#define DB8500_PIN_AG4 _GPIO(11)
|
||||
#define DB8500_PIN_AC4 _GPIO(12)
|
||||
#define DB8500_PIN_AF3 _GPIO(13)
|
||||
#define DB8500_PIN_AE3 _GPIO(14)
|
||||
#define DB8500_PIN_AC3 _GPIO(15)
|
||||
#define DB8500_PIN_AD3 _GPIO(16)
|
||||
#define DB8500_PIN_AD4 _GPIO(17)
|
||||
#define DB8500_PIN_AC2 _GPIO(18)
|
||||
#define DB8500_PIN_AC1 _GPIO(19)
|
||||
#define DB8500_PIN_AB4 _GPIO(20)
|
||||
#define DB8500_PIN_AB3 _GPIO(21)
|
||||
#define DB8500_PIN_AA3 _GPIO(22)
|
||||
#define DB8500_PIN_AA4 _GPIO(23)
|
||||
#define DB8500_PIN_AB2 _GPIO(24)
|
||||
#define DB8500_PIN_Y4 _GPIO(25)
|
||||
#define DB8500_PIN_Y2 _GPIO(26)
|
||||
#define DB8500_PIN_AA2 _GPIO(27)
|
||||
#define DB8500_PIN_AA1 _GPIO(28)
|
||||
#define DB8500_PIN_W2 _GPIO(29)
|
||||
#define DB8500_PIN_W3 _GPIO(30)
|
||||
#define DB8500_PIN_V3 _GPIO(31)
|
||||
#define DB8500_PIN_V2 _GPIO(32)
|
||||
#define DB8500_PIN_AF2 _GPIO(33)
|
||||
#define DB8500_PIN_AE1 _GPIO(34)
|
||||
#define DB8500_PIN_AE2 _GPIO(35)
|
||||
#define DB8500_PIN_AG2 _GPIO(36)
|
||||
/* Hole */
|
||||
#define DB8500_PIN_F3 _GPIO(64)
|
||||
#define DB8500_PIN_F1 _GPIO(65)
|
||||
#define DB8500_PIN_G3 _GPIO(66)
|
||||
#define DB8500_PIN_G2 _GPIO(67)
|
||||
#define DB8500_PIN_E1 _GPIO(68)
|
||||
#define DB8500_PIN_E2 _GPIO(69)
|
||||
#define DB8500_PIN_G5 _GPIO(70)
|
||||
#define DB8500_PIN_G4 _GPIO(71)
|
||||
#define DB8500_PIN_H4 _GPIO(72)
|
||||
#define DB8500_PIN_H3 _GPIO(73)
|
||||
#define DB8500_PIN_J3 _GPIO(74)
|
||||
#define DB8500_PIN_H2 _GPIO(75)
|
||||
#define DB8500_PIN_J2 _GPIO(76)
|
||||
#define DB8500_PIN_H1 _GPIO(77)
|
||||
#define DB8500_PIN_F4 _GPIO(78)
|
||||
#define DB8500_PIN_E3 _GPIO(79)
|
||||
#define DB8500_PIN_E4 _GPIO(80)
|
||||
#define DB8500_PIN_D2 _GPIO(81)
|
||||
#define DB8500_PIN_C1 _GPIO(82)
|
||||
#define DB8500_PIN_D3 _GPIO(83)
|
||||
#define DB8500_PIN_C2 _GPIO(84)
|
||||
#define DB8500_PIN_D5 _GPIO(85)
|
||||
#define DB8500_PIN_C6 _GPIO(86)
|
||||
#define DB8500_PIN_B3 _GPIO(87)
|
||||
#define DB8500_PIN_C4 _GPIO(88)
|
||||
#define DB8500_PIN_E6 _GPIO(89)
|
||||
#define DB8500_PIN_A3 _GPIO(90)
|
||||
#define DB8500_PIN_B6 _GPIO(91)
|
||||
#define DB8500_PIN_D6 _GPIO(92)
|
||||
#define DB8500_PIN_B7 _GPIO(93)
|
||||
#define DB8500_PIN_D7 _GPIO(94)
|
||||
#define DB8500_PIN_E8 _GPIO(95)
|
||||
#define DB8500_PIN_D8 _GPIO(96)
|
||||
#define DB8500_PIN_D9 _GPIO(97)
|
||||
/* Hole */
|
||||
#define DB8500_PIN_A5 _GPIO(128)
|
||||
#define DB8500_PIN_B4 _GPIO(129)
|
||||
#define DB8500_PIN_C8 _GPIO(130)
|
||||
#define DB8500_PIN_A12 _GPIO(131)
|
||||
#define DB8500_PIN_C10 _GPIO(132)
|
||||
#define DB8500_PIN_B10 _GPIO(133)
|
||||
#define DB8500_PIN_B9 _GPIO(134)
|
||||
#define DB8500_PIN_A9 _GPIO(135)
|
||||
#define DB8500_PIN_C7 _GPIO(136)
|
||||
#define DB8500_PIN_A7 _GPIO(137)
|
||||
#define DB8500_PIN_C5 _GPIO(138)
|
||||
#define DB8500_PIN_C9 _GPIO(139)
|
||||
#define DB8500_PIN_B11 _GPIO(140)
|
||||
#define DB8500_PIN_C12 _GPIO(141)
|
||||
#define DB8500_PIN_C11 _GPIO(142)
|
||||
#define DB8500_PIN_D12 _GPIO(143)
|
||||
#define DB8500_PIN_B13 _GPIO(144)
|
||||
#define DB8500_PIN_C13 _GPIO(145)
|
||||
#define DB8500_PIN_D13 _GPIO(146)
|
||||
#define DB8500_PIN_C15 _GPIO(147)
|
||||
#define DB8500_PIN_B16 _GPIO(148)
|
||||
#define DB8500_PIN_B14 _GPIO(149)
|
||||
#define DB8500_PIN_C14 _GPIO(150)
|
||||
#define DB8500_PIN_D17 _GPIO(151)
|
||||
#define DB8500_PIN_D16 _GPIO(152)
|
||||
#define DB8500_PIN_B17 _GPIO(153)
|
||||
#define DB8500_PIN_C16 _GPIO(154)
|
||||
#define DB8500_PIN_C19 _GPIO(155)
|
||||
#define DB8500_PIN_C17 _GPIO(156)
|
||||
#define DB8500_PIN_A18 _GPIO(157)
|
||||
#define DB8500_PIN_C18 _GPIO(158)
|
||||
#define DB8500_PIN_B19 _GPIO(159)
|
||||
#define DB8500_PIN_B20 _GPIO(160)
|
||||
#define DB8500_PIN_D21 _GPIO(161)
|
||||
#define DB8500_PIN_D20 _GPIO(162)
|
||||
#define DB8500_PIN_C20 _GPIO(163)
|
||||
#define DB8500_PIN_B21 _GPIO(164)
|
||||
#define DB8500_PIN_C21 _GPIO(165)
|
||||
#define DB8500_PIN_A22 _GPIO(166)
|
||||
#define DB8500_PIN_B24 _GPIO(167)
|
||||
#define DB8500_PIN_C22 _GPIO(168)
|
||||
#define DB8500_PIN_D22 _GPIO(169)
|
||||
#define DB8500_PIN_C23 _GPIO(170)
|
||||
#define DB8500_PIN_D23 _GPIO(171)
|
||||
/* Hole */
|
||||
#define DB8500_PIN_AJ27 _GPIO(192)
|
||||
#define DB8500_PIN_AH27 _GPIO(193)
|
||||
#define DB8500_PIN_AF27 _GPIO(194)
|
||||
#define DB8500_PIN_AG28 _GPIO(195)
|
||||
#define DB8500_PIN_AG26 _GPIO(196)
|
||||
#define DB8500_PIN_AH24 _GPIO(197)
|
||||
#define DB8500_PIN_AG25 _GPIO(198)
|
||||
#define DB8500_PIN_AH23 _GPIO(199)
|
||||
#define DB8500_PIN_AH26 _GPIO(200)
|
||||
#define DB8500_PIN_AF24 _GPIO(201)
|
||||
#define DB8500_PIN_AF25 _GPIO(202)
|
||||
#define DB8500_PIN_AE23 _GPIO(203)
|
||||
#define DB8500_PIN_AF23 _GPIO(204)
|
||||
#define DB8500_PIN_AG23 _GPIO(205)
|
||||
#define DB8500_PIN_AG24 _GPIO(206)
|
||||
#define DB8500_PIN_AJ23 _GPIO(207)
|
||||
#define DB8500_PIN_AH16 _GPIO(208)
|
||||
#define DB8500_PIN_AG15 _GPIO(209)
|
||||
#define DB8500_PIN_AJ15 _GPIO(210)
|
||||
#define DB8500_PIN_AG14 _GPIO(211)
|
||||
#define DB8500_PIN_AF13 _GPIO(212)
|
||||
#define DB8500_PIN_AG13 _GPIO(213)
|
||||
#define DB8500_PIN_AH15 _GPIO(214)
|
||||
#define DB8500_PIN_AH13 _GPIO(215)
|
||||
#define DB8500_PIN_AG12 _GPIO(216)
|
||||
#define DB8500_PIN_AH12 _GPIO(217)
|
||||
#define DB8500_PIN_AH11 _GPIO(218)
|
||||
#define DB8500_PIN_AG10 _GPIO(219)
|
||||
#define DB8500_PIN_AH10 _GPIO(220)
|
||||
#define DB8500_PIN_AJ11 _GPIO(221)
|
||||
#define DB8500_PIN_AJ9 _GPIO(222)
|
||||
#define DB8500_PIN_AH9 _GPIO(223)
|
||||
#define DB8500_PIN_AG9 _GPIO(224)
|
||||
#define DB8500_PIN_AG8 _GPIO(225)
|
||||
#define DB8500_PIN_AF8 _GPIO(226)
|
||||
#define DB8500_PIN_AH7 _GPIO(227)
|
||||
#define DB8500_PIN_AJ6 _GPIO(228)
|
||||
#define DB8500_PIN_AG7 _GPIO(229)
|
||||
#define DB8500_PIN_AF7 _GPIO(230)
|
||||
/* Hole */
|
||||
#define DB8500_PIN_AF28 _GPIO(256)
|
||||
#define DB8500_PIN_AE29 _GPIO(257)
|
||||
#define DB8500_PIN_AD29 _GPIO(258)
|
||||
#define DB8500_PIN_AC29 _GPIO(259)
|
||||
#define DB8500_PIN_AD28 _GPIO(260)
|
||||
#define DB8500_PIN_AD26 _GPIO(261)
|
||||
#define DB8500_PIN_AE26 _GPIO(262)
|
||||
#define DB8500_PIN_AG29 _GPIO(263)
|
||||
#define DB8500_PIN_AE27 _GPIO(264)
|
||||
#define DB8500_PIN_AD27 _GPIO(265)
|
||||
#define DB8500_PIN_AC28 _GPIO(266)
|
||||
#define DB8500_PIN_AC27 _GPIO(267)
|
||||
|
||||
/*
|
||||
* The names of the pins are denoted by GPIO number and ball name, even
|
||||
* though they can be used for other things than GPIO, this is the first
|
||||
* column in the table of the data sheet and often used on schematics and
|
||||
* such.
|
||||
*/
|
||||
static const struct pinctrl_pin_desc nmk_db8500_pins[] = {
|
||||
PINCTRL_PIN(DB8500_PIN_AJ5, "GPIO0_AJ5"),
|
||||
PINCTRL_PIN(DB8500_PIN_AJ3, "GPIO1_AJ3"),
|
||||
PINCTRL_PIN(DB8500_PIN_AH4, "GPIO2_AH4"),
|
||||
PINCTRL_PIN(DB8500_PIN_AH3, "GPIO3_AH3"),
|
||||
PINCTRL_PIN(DB8500_PIN_AH6, "GPIO4_AH6"),
|
||||
PINCTRL_PIN(DB8500_PIN_AG6, "GPIO5_AG6"),
|
||||
PINCTRL_PIN(DB8500_PIN_AF6, "GPIO6_AF6"),
|
||||
PINCTRL_PIN(DB8500_PIN_AG5, "GPIO7_AG5"),
|
||||
PINCTRL_PIN(DB8500_PIN_AD5, "GPIO8_AD5"),
|
||||
PINCTRL_PIN(DB8500_PIN_AE4, "GPIO9_AE4"),
|
||||
PINCTRL_PIN(DB8500_PIN_AF5, "GPIO10_AF5"),
|
||||
PINCTRL_PIN(DB8500_PIN_AG4, "GPIO11_AG4"),
|
||||
PINCTRL_PIN(DB8500_PIN_AC4, "GPIO12_AC4"),
|
||||
PINCTRL_PIN(DB8500_PIN_AF3, "GPIO13_AF3"),
|
||||
PINCTRL_PIN(DB8500_PIN_AE3, "GPIO14_AE3"),
|
||||
PINCTRL_PIN(DB8500_PIN_AC3, "GPIO15_AC3"),
|
||||
PINCTRL_PIN(DB8500_PIN_AD3, "GPIO16_AD3"),
|
||||
PINCTRL_PIN(DB8500_PIN_AD4, "GPIO17_AD4"),
|
||||
PINCTRL_PIN(DB8500_PIN_AC2, "GPIO18_AC2"),
|
||||
PINCTRL_PIN(DB8500_PIN_AC1, "GPIO19_AC1"),
|
||||
PINCTRL_PIN(DB8500_PIN_AB4, "GPIO20_AB4"),
|
||||
PINCTRL_PIN(DB8500_PIN_AB3, "GPIO21_AB3"),
|
||||
PINCTRL_PIN(DB8500_PIN_AA3, "GPIO22_AA3"),
|
||||
PINCTRL_PIN(DB8500_PIN_AA4, "GPIO23_AA4"),
|
||||
PINCTRL_PIN(DB8500_PIN_AB2, "GPIO24_AB2"),
|
||||
PINCTRL_PIN(DB8500_PIN_Y4, "GPIO25_Y4"),
|
||||
PINCTRL_PIN(DB8500_PIN_Y2, "GPIO26_Y2"),
|
||||
PINCTRL_PIN(DB8500_PIN_AA2, "GPIO27_AA2"),
|
||||
PINCTRL_PIN(DB8500_PIN_AA1, "GPIO28_AA1"),
|
||||
PINCTRL_PIN(DB8500_PIN_W2, "GPIO29_W2"),
|
||||
PINCTRL_PIN(DB8500_PIN_W3, "GPIO30_W3"),
|
||||
PINCTRL_PIN(DB8500_PIN_V3, "GPIO31_V3"),
|
||||
PINCTRL_PIN(DB8500_PIN_V2, "GPIO32_V2"),
|
||||
PINCTRL_PIN(DB8500_PIN_AF2, "GPIO33_AF2"),
|
||||
PINCTRL_PIN(DB8500_PIN_AE1, "GPIO34_AE1"),
|
||||
PINCTRL_PIN(DB8500_PIN_AE2, "GPIO35_AE2"),
|
||||
PINCTRL_PIN(DB8500_PIN_AG2, "GPIO36_AG2"),
|
||||
/* Hole */
|
||||
PINCTRL_PIN(DB8500_PIN_F3, "GPIO64_F3"),
|
||||
PINCTRL_PIN(DB8500_PIN_F1, "GPIO65_F1"),
|
||||
PINCTRL_PIN(DB8500_PIN_G3, "GPIO66_G3"),
|
||||
PINCTRL_PIN(DB8500_PIN_G2, "GPIO67_G2"),
|
||||
PINCTRL_PIN(DB8500_PIN_E1, "GPIO68_E1"),
|
||||
PINCTRL_PIN(DB8500_PIN_E2, "GPIO69_E2"),
|
||||
PINCTRL_PIN(DB8500_PIN_G5, "GPIO70_G5"),
|
||||
PINCTRL_PIN(DB8500_PIN_G4, "GPIO71_G4"),
|
||||
PINCTRL_PIN(DB8500_PIN_H4, "GPIO72_H4"),
|
||||
PINCTRL_PIN(DB8500_PIN_H3, "GPIO73_H3"),
|
||||
PINCTRL_PIN(DB8500_PIN_J3, "GPIO74_J3"),
|
||||
PINCTRL_PIN(DB8500_PIN_H2, "GPIO75_H2"),
|
||||
PINCTRL_PIN(DB8500_PIN_J2, "GPIO76_J2"),
|
||||
PINCTRL_PIN(DB8500_PIN_H1, "GPIO77_H1"),
|
||||
PINCTRL_PIN(DB8500_PIN_F4, "GPIO78_F4"),
|
||||
PINCTRL_PIN(DB8500_PIN_E3, "GPIO79_E3"),
|
||||
PINCTRL_PIN(DB8500_PIN_E4, "GPIO80_E4"),
|
||||
PINCTRL_PIN(DB8500_PIN_D2, "GPIO81_D2"),
|
||||
PINCTRL_PIN(DB8500_PIN_C1, "GPIO82_C1"),
|
||||
PINCTRL_PIN(DB8500_PIN_D3, "GPIO83_D3"),
|
||||
PINCTRL_PIN(DB8500_PIN_C2, "GPIO84_C2"),
|
||||
PINCTRL_PIN(DB8500_PIN_D5, "GPIO85_D5"),
|
||||
PINCTRL_PIN(DB8500_PIN_C6, "GPIO86_C6"),
|
||||
PINCTRL_PIN(DB8500_PIN_B3, "GPIO87_B3"),
|
||||
PINCTRL_PIN(DB8500_PIN_C4, "GPIO88_C4"),
|
||||
PINCTRL_PIN(DB8500_PIN_E6, "GPIO89_E6"),
|
||||
PINCTRL_PIN(DB8500_PIN_A3, "GPIO90_A3"),
|
||||
PINCTRL_PIN(DB8500_PIN_B6, "GPIO91_B6"),
|
||||
PINCTRL_PIN(DB8500_PIN_D6, "GPIO92_D6"),
|
||||
PINCTRL_PIN(DB8500_PIN_B7, "GPIO93_B7"),
|
||||
PINCTRL_PIN(DB8500_PIN_D7, "GPIO94_D7"),
|
||||
PINCTRL_PIN(DB8500_PIN_E8, "GPIO95_E8"),
|
||||
PINCTRL_PIN(DB8500_PIN_D8, "GPIO96_D8"),
|
||||
PINCTRL_PIN(DB8500_PIN_D9, "GPIO97_D9"),
|
||||
/* Hole */
|
||||
PINCTRL_PIN(DB8500_PIN_A5, "GPIO128_A5"),
|
||||
PINCTRL_PIN(DB8500_PIN_B4, "GPIO129_B4"),
|
||||
PINCTRL_PIN(DB8500_PIN_C8, "GPIO130_C8"),
|
||||
PINCTRL_PIN(DB8500_PIN_A12, "GPIO131_A12"),
|
||||
PINCTRL_PIN(DB8500_PIN_C10, "GPIO132_C10"),
|
||||
PINCTRL_PIN(DB8500_PIN_B10, "GPIO133_B10"),
|
||||
PINCTRL_PIN(DB8500_PIN_B9, "GPIO134_B9"),
|
||||
PINCTRL_PIN(DB8500_PIN_A9, "GPIO135_A9"),
|
||||
PINCTRL_PIN(DB8500_PIN_C7, "GPIO136_C7"),
|
||||
PINCTRL_PIN(DB8500_PIN_A7, "GPIO137_A7"),
|
||||
PINCTRL_PIN(DB8500_PIN_C5, "GPIO138_C5"),
|
||||
PINCTRL_PIN(DB8500_PIN_C9, "GPIO139_C9"),
|
||||
PINCTRL_PIN(DB8500_PIN_B11, "GPIO140_B11"),
|
||||
PINCTRL_PIN(DB8500_PIN_C12, "GPIO141_C12"),
|
||||
PINCTRL_PIN(DB8500_PIN_C11, "GPIO142_C11"),
|
||||
PINCTRL_PIN(DB8500_PIN_D12, "GPIO143_D12"),
|
||||
PINCTRL_PIN(DB8500_PIN_B13, "GPIO144_B13"),
|
||||
PINCTRL_PIN(DB8500_PIN_C13, "GPIO145_C13"),
|
||||
PINCTRL_PIN(DB8500_PIN_D13, "GPIO146_D13"),
|
||||
PINCTRL_PIN(DB8500_PIN_C15, "GPIO147_C15"),
|
||||
PINCTRL_PIN(DB8500_PIN_B16, "GPIO148_B16"),
|
||||
PINCTRL_PIN(DB8500_PIN_B14, "GPIO149_B14"),
|
||||
PINCTRL_PIN(DB8500_PIN_C14, "GPIO150_C14"),
|
||||
PINCTRL_PIN(DB8500_PIN_D17, "GPIO151_D17"),
|
||||
PINCTRL_PIN(DB8500_PIN_D16, "GPIO152_D16"),
|
||||
PINCTRL_PIN(DB8500_PIN_B17, "GPIO153_B17"),
|
||||
PINCTRL_PIN(DB8500_PIN_C16, "GPIO154_C16"),
|
||||
PINCTRL_PIN(DB8500_PIN_C19, "GPIO155_C19"),
|
||||
PINCTRL_PIN(DB8500_PIN_C17, "GPIO156_C17"),
|
||||
PINCTRL_PIN(DB8500_PIN_A18, "GPIO157_A18"),
|
||||
PINCTRL_PIN(DB8500_PIN_C18, "GPIO158_C18"),
|
||||
PINCTRL_PIN(DB8500_PIN_B19, "GPIO159_B19"),
|
||||
PINCTRL_PIN(DB8500_PIN_B20, "GPIO160_B20"),
|
||||
PINCTRL_PIN(DB8500_PIN_D21, "GPIO161_D21"),
|
||||
PINCTRL_PIN(DB8500_PIN_D20, "GPIO162_D20"),
|
||||
PINCTRL_PIN(DB8500_PIN_C20, "GPIO163_C20"),
|
||||
PINCTRL_PIN(DB8500_PIN_B21, "GPIO164_B21"),
|
||||
PINCTRL_PIN(DB8500_PIN_C21, "GPIO165_C21"),
|
||||
PINCTRL_PIN(DB8500_PIN_A22, "GPIO166_A22"),
|
||||
PINCTRL_PIN(DB8500_PIN_B24, "GPIO167_B24"),
|
||||
PINCTRL_PIN(DB8500_PIN_C22, "GPIO168_C22"),
|
||||
PINCTRL_PIN(DB8500_PIN_D22, "GPIO169_D22"),
|
||||
PINCTRL_PIN(DB8500_PIN_C23, "GPIO170_C23"),
|
||||
PINCTRL_PIN(DB8500_PIN_D23, "GPIO171_D23"),
|
||||
/* Hole */
|
||||
PINCTRL_PIN(DB8500_PIN_AJ27, "GPIO192_AJ27"),
|
||||
PINCTRL_PIN(DB8500_PIN_AH27, "GPIO193_AH27"),
|
||||
PINCTRL_PIN(DB8500_PIN_AF27, "GPIO194_AF27"),
|
||||
PINCTRL_PIN(DB8500_PIN_AG28, "GPIO195_AG28"),
|
||||
PINCTRL_PIN(DB8500_PIN_AG26, "GPIO196_AG26"),
|
||||
PINCTRL_PIN(DB8500_PIN_AH24, "GPIO197_AH24"),
|
||||
PINCTRL_PIN(DB8500_PIN_AG25, "GPIO198_AG25"),
|
||||
PINCTRL_PIN(DB8500_PIN_AH23, "GPIO199_AH23"),
|
||||
PINCTRL_PIN(DB8500_PIN_AH26, "GPIO200_AH26"),
|
||||
PINCTRL_PIN(DB8500_PIN_AF24, "GPIO201_AF24"),
|
||||
PINCTRL_PIN(DB8500_PIN_AF25, "GPIO202_AF25"),
|
||||
PINCTRL_PIN(DB8500_PIN_AE23, "GPIO203_AE23"),
|
||||
PINCTRL_PIN(DB8500_PIN_AF23, "GPIO204_AF23"),
|
||||
PINCTRL_PIN(DB8500_PIN_AG23, "GPIO205_AG23"),
|
||||
PINCTRL_PIN(DB8500_PIN_AG24, "GPIO206_AG24"),
|
||||
PINCTRL_PIN(DB8500_PIN_AJ23, "GPIO207_AJ23"),
|
||||
PINCTRL_PIN(DB8500_PIN_AH16, "GPIO208_AH16"),
|
||||
PINCTRL_PIN(DB8500_PIN_AG15, "GPIO209_AG15"),
|
||||
PINCTRL_PIN(DB8500_PIN_AJ15, "GPIO210_AJ15"),
|
||||
PINCTRL_PIN(DB8500_PIN_AG14, "GPIO211_AG14"),
|
||||
PINCTRL_PIN(DB8500_PIN_AF13, "GPIO212_AF13"),
|
||||
PINCTRL_PIN(DB8500_PIN_AG13, "GPIO213_AG13"),
|
||||
PINCTRL_PIN(DB8500_PIN_AH15, "GPIO214_AH15"),
|
||||
PINCTRL_PIN(DB8500_PIN_AH13, "GPIO215_AH13"),
|
||||
PINCTRL_PIN(DB8500_PIN_AG12, "GPIO216_AG12"),
|
||||
PINCTRL_PIN(DB8500_PIN_AH12, "GPIO217_AH12"),
|
||||
PINCTRL_PIN(DB8500_PIN_AH11, "GPIO218_AH11"),
|
||||
PINCTRL_PIN(DB8500_PIN_AG10, "GPIO219_AG10"),
|
||||
PINCTRL_PIN(DB8500_PIN_AH10, "GPIO220_AH10"),
|
||||
PINCTRL_PIN(DB8500_PIN_AJ11, "GPIO221_AJ11"),
|
||||
PINCTRL_PIN(DB8500_PIN_AJ9, "GPIO222_AJ9"),
|
||||
PINCTRL_PIN(DB8500_PIN_AH9, "GPIO223_AH9"),
|
||||
PINCTRL_PIN(DB8500_PIN_AG9, "GPIO224_AG9"),
|
||||
PINCTRL_PIN(DB8500_PIN_AG8, "GPIO225_AG8"),
|
||||
PINCTRL_PIN(DB8500_PIN_AF8, "GPIO226_AF8"),
|
||||
PINCTRL_PIN(DB8500_PIN_AH7, "GPIO227_AH7"),
|
||||
PINCTRL_PIN(DB8500_PIN_AJ6, "GPIO228_AJ6"),
|
||||
PINCTRL_PIN(DB8500_PIN_AG7, "GPIO229_AG7"),
|
||||
PINCTRL_PIN(DB8500_PIN_AF7, "GPIO230_AF7"),
|
||||
/* Hole */
|
||||
PINCTRL_PIN(DB8500_PIN_AF28, "GPIO256_AF28"),
|
||||
PINCTRL_PIN(DB8500_PIN_AE29, "GPIO257_AE29"),
|
||||
PINCTRL_PIN(DB8500_PIN_AD29, "GPIO258_AD29"),
|
||||
PINCTRL_PIN(DB8500_PIN_AC29, "GPIO259_AC29"),
|
||||
PINCTRL_PIN(DB8500_PIN_AD28, "GPIO260_AD28"),
|
||||
PINCTRL_PIN(DB8500_PIN_AD26, "GPIO261_AD26"),
|
||||
PINCTRL_PIN(DB8500_PIN_AE26, "GPIO262_AE26"),
|
||||
PINCTRL_PIN(DB8500_PIN_AG29, "GPIO263_AG29"),
|
||||
PINCTRL_PIN(DB8500_PIN_AE27, "GPIO264_AE27"),
|
||||
PINCTRL_PIN(DB8500_PIN_AD27, "GPIO265_AD27"),
|
||||
PINCTRL_PIN(DB8500_PIN_AC28, "GPIO266_AC28"),
|
||||
PINCTRL_PIN(DB8500_PIN_AC27, "GPIO267_AC27"),
|
||||
};
|
||||
|
||||
#define DB8500_GPIO_RANGE(a, b, c) { .name = "DB8500", .id = a, .base = b, \
|
||||
.pin_base = b, .npins = c }
|
||||
|
||||
/*
|
||||
* This matches the 32-pin gpio chips registered by the GPIO portion. This
|
||||
* cannot be const since we assign the struct gpio_chip * pointer at runtime.
|
||||
*/
|
||||
static struct pinctrl_gpio_range nmk_db8500_ranges[] = {
|
||||
DB8500_GPIO_RANGE(0, 0, 32),
|
||||
DB8500_GPIO_RANGE(1, 32, 5),
|
||||
DB8500_GPIO_RANGE(2, 64, 32),
|
||||
DB8500_GPIO_RANGE(3, 96, 2),
|
||||
DB8500_GPIO_RANGE(4, 128, 32),
|
||||
DB8500_GPIO_RANGE(5, 160, 12),
|
||||
DB8500_GPIO_RANGE(6, 192, 32),
|
||||
DB8500_GPIO_RANGE(7, 224, 7),
|
||||
DB8500_GPIO_RANGE(8, 256, 12),
|
||||
};
|
||||
|
||||
/*
|
||||
* Read the pin group names like this:
|
||||
* u0_a_1 = first groups of pins for uart0 on alt function a
|
||||
* i2c2_b_2 = second group of pins for i2c2 on alt function b
|
||||
*
|
||||
* The groups are arranged as sets per altfunction column, so we can
|
||||
* mux in one group at a time by selecting the same altfunction for them
|
||||
* all. When functions require pins on different altfunctions, you need
|
||||
* to combine several groups.
|
||||
*/
|
||||
|
||||
/* Altfunction A column */
|
||||
static const unsigned u0_a_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3,
|
||||
DB8500_PIN_AH4, DB8500_PIN_AH3 };
|
||||
static const unsigned u1rxtx_a_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 };
|
||||
static const unsigned u1ctsrts_a_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 };
|
||||
/* Image processor I2C line, this is driven by image processor firmware */
|
||||
static const unsigned ipi2c_a_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 };
|
||||
static const unsigned ipi2c_a_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 };
|
||||
/* MSP0 can only be on these pins, but TXD and RXD can be flipped */
|
||||
static const unsigned msp0txrx_a_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 };
|
||||
static const unsigned msp0tfstck_a_1_pins[] = { DB8500_PIN_AF3, DB8500_PIN_AE3 };
|
||||
static const unsigned msp0rfsrck_a_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
|
||||
/* Basic pins of the MMC/SD card 0 interface */
|
||||
static const unsigned mc0_a_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1,
|
||||
DB8500_PIN_AB4, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2,
|
||||
DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
|
||||
/* Often only 4 bits are used, then these are not needed (only used for MMC) */
|
||||
static const unsigned mc0_dat47_a_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3,
|
||||
DB8500_PIN_V3, DB8500_PIN_V2};
|
||||
static const unsigned mc0dat31dir_a_1_pins[] = { DB8500_PIN_AB3 };
|
||||
/* MSP1 can only be on these pins, but TXD and RXD can be flipped */
|
||||
static const unsigned msp1txrx_a_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 };
|
||||
static const unsigned msp1_a_1_pins[] = { DB8500_PIN_AE1, DB8500_PIN_AE2 };
|
||||
/* LCD interface */
|
||||
static const unsigned lcdb_a_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
|
||||
DB8500_PIN_G3, DB8500_PIN_G2 };
|
||||
static const unsigned lcdvsi0_a_1_pins[] = { DB8500_PIN_E1 };
|
||||
static const unsigned lcdvsi1_a_1_pins[] = { DB8500_PIN_E2 };
|
||||
static const unsigned lcd_d0_d7_a_1_pins[] = {
|
||||
DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3,
|
||||
DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1 };
|
||||
/* D8 thru D11 often used as TVOUT lines */
|
||||
static const unsigned lcd_d8_d11_a_1_pins[] = { DB8500_PIN_F4,
|
||||
DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2 };
|
||||
static const unsigned lcd_d12_d23_a_1_pins[] = {
|
||||
DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5,
|
||||
DB8500_PIN_C6, DB8500_PIN_B3, DB8500_PIN_C4, DB8500_PIN_E6,
|
||||
DB8500_PIN_A3, DB8500_PIN_B6, DB8500_PIN_D6, DB8500_PIN_B7 };
|
||||
static const unsigned kp_a_1_pins[] = { DB8500_PIN_D7, DB8500_PIN_E8,
|
||||
DB8500_PIN_D8, DB8500_PIN_D9 };
|
||||
static const unsigned kpskaskb_a_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16 };
|
||||
static const unsigned kp_a_2_pins[] = {
|
||||
DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17,
|
||||
DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20,
|
||||
DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
|
||||
DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
|
||||
/* MC2 has 8 data lines and no direction control, so only for (e)MMC */
|
||||
static const unsigned mc2_a_1_pins[] = { DB8500_PIN_A5, DB8500_PIN_B4,
|
||||
DB8500_PIN_C8, DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10,
|
||||
DB8500_PIN_B9, DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7,
|
||||
DB8500_PIN_C5 };
|
||||
static const unsigned ssp1_a_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11,
|
||||
DB8500_PIN_C12, DB8500_PIN_C11 };
|
||||
static const unsigned ssp0_a_1_pins[] = { DB8500_PIN_D12, DB8500_PIN_B13,
|
||||
DB8500_PIN_C13, DB8500_PIN_D13 };
|
||||
static const unsigned i2c0_a_1_pins[] = { DB8500_PIN_C15, DB8500_PIN_B16 };
|
||||
/*
|
||||
* Image processor GPIO pins are named "ipgpio" and have their own
|
||||
* numberspace
|
||||
*/
|
||||
static const unsigned ipgpio0_a_1_pins[] = { DB8500_PIN_B14 };
|
||||
static const unsigned ipgpio1_a_1_pins[] = { DB8500_PIN_C14 };
|
||||
/* Three modem pins named RF_PURn, MODEM_STATE and MODEM_PWREN */
|
||||
static const unsigned modem_a_1_pins[] = { DB8500_PIN_D22, DB8500_PIN_C23,
|
||||
DB8500_PIN_D23 };
|
||||
/*
|
||||
* This MSP cannot switch RX and TX, SCK in a separate group since this
|
||||
* seems to be optional.
|
||||
*/
|
||||
static const unsigned msp2sck_a_1_pins[] = { DB8500_PIN_AJ27 };
|
||||
static const unsigned msp2_a_1_pins[] = { DB8500_PIN_AH27, DB8500_PIN_AF27,
|
||||
DB8500_PIN_AG28, DB8500_PIN_AG26 };
|
||||
static const unsigned mc4_a_1_pins[] = { DB8500_PIN_AH24, DB8500_PIN_AG25,
|
||||
DB8500_PIN_AH23, DB8500_PIN_AH26, DB8500_PIN_AF24, DB8500_PIN_AF25,
|
||||
DB8500_PIN_AE23, DB8500_PIN_AF23, DB8500_PIN_AG23, DB8500_PIN_AG24,
|
||||
DB8500_PIN_AJ23 };
|
||||
/* MC1 has only 4 data pins, designed for SD or SDIO exclusively */
|
||||
static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15,
|
||||
DB8500_PIN_AJ15, DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13,
|
||||
DB8500_PIN_AH15 };
|
||||
static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
|
||||
DB8500_PIN_AH12, DB8500_PIN_AH11 };
|
||||
static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10 };
|
||||
static const unsigned hsit_a_1_pins[] = { DB8500_PIN_AJ11, DB8500_PIN_AJ9,
|
||||
DB8500_PIN_AH9, DB8500_PIN_AG9, DB8500_PIN_AG8, DB8500_PIN_AF8 };
|
||||
static const unsigned clkout_a_1_pins[] = { DB8500_PIN_AH7, DB8500_PIN_AJ6 };
|
||||
static const unsigned clkout_a_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 };
|
||||
static const unsigned usb_a_1_pins[] = { DB8500_PIN_AF28, DB8500_PIN_AE29,
|
||||
DB8500_PIN_AD29, DB8500_PIN_AC29, DB8500_PIN_AD28, DB8500_PIN_AD26,
|
||||
DB8500_PIN_AE26, DB8500_PIN_AG29, DB8500_PIN_AE27, DB8500_PIN_AD27,
|
||||
DB8500_PIN_AC28, DB8500_PIN_AC27 };
|
||||
|
||||
/* Altfunction B column */
|
||||
static const unsigned trig_b_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3 };
|
||||
static const unsigned i2c4_b_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 };
|
||||
static const unsigned i2c1_b_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 };
|
||||
static const unsigned i2c2_b_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 };
|
||||
static const unsigned i2c2_b_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 };
|
||||
static const unsigned msp0txrx_b_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 };
|
||||
static const unsigned i2c1_b_2_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
|
||||
/* Just RX and TX for UART2 */
|
||||
static const unsigned u2rxtx_b_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1 };
|
||||
static const unsigned uartmodtx_b_1_pins[] = { DB8500_PIN_AB4 };
|
||||
static const unsigned msp0sck_b_1_pins[] = { DB8500_PIN_AB3 };
|
||||
static const unsigned uartmodrx_b_1_pins[] = { DB8500_PIN_AA3 };
|
||||
static const unsigned stmmod_b_1_pins[] = { DB8500_PIN_AA4, DB8500_PIN_Y4,
|
||||
DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
|
||||
static const unsigned uartmodrx_b_2_pins[] = { DB8500_PIN_AB2 };
|
||||
static const unsigned spi3_b_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3,
|
||||
DB8500_PIN_V3, DB8500_PIN_V2 };
|
||||
static const unsigned msp1txrx_b_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 };
|
||||
static const unsigned kp_b_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
|
||||
DB8500_PIN_G3, DB8500_PIN_G2, DB8500_PIN_E1, DB8500_PIN_E2,
|
||||
DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3,
|
||||
DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1,
|
||||
DB8500_PIN_F4, DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2,
|
||||
DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5 };
|
||||
static const unsigned sm_b_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
|
||||
DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
|
||||
DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8,
|
||||
DB8500_PIN_D9, DB8500_PIN_A5, DB8500_PIN_B4, DB8500_PIN_C8,
|
||||
DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, DB8500_PIN_B9,
|
||||
DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, DB8500_PIN_C5,
|
||||
DB8500_PIN_C9, DB8500_PIN_B14 };
|
||||
/* This chip select pin can be "ps0" in alt B so have it separately */
|
||||
static const unsigned smcs0_b_1_pins[] = { DB8500_PIN_E8 };
|
||||
static const unsigned ipgpio7_b_1_pins[] = { DB8500_PIN_B11 };
|
||||
static const unsigned ipgpio2_b_1_pins[] = { DB8500_PIN_C12 };
|
||||
static const unsigned ipgpio3_b_1_pins[] = { DB8500_PIN_C11 };
|
||||
static const unsigned lcdaclk_b_1_pins[] = { DB8500_PIN_C14 };
|
||||
static const unsigned lcda_b_1_pins[] = { DB8500_PIN_D22,
|
||||
DB8500_PIN_C23, DB8500_PIN_D23 };
|
||||
static const unsigned lcd_b_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16,
|
||||
DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17,
|
||||
DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20,
|
||||
DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
|
||||
DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
|
||||
static const unsigned ddrtrig_b_1_pins[] = { DB8500_PIN_AJ27 };
|
||||
static const unsigned pwl_b_1_pins[] = { DB8500_PIN_AF25 };
|
||||
static const unsigned spi1_b_1_pins[] = { DB8500_PIN_AG15, DB8500_PIN_AF13,
|
||||
DB8500_PIN_AG13, DB8500_PIN_AH15 };
|
||||
static const unsigned mc3_b_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
|
||||
DB8500_PIN_AH12, DB8500_PIN_AH11, DB8500_PIN_AG10, DB8500_PIN_AH10,
|
||||
DB8500_PIN_AJ11, DB8500_PIN_AJ9, DB8500_PIN_AH9, DB8500_PIN_AG9,
|
||||
DB8500_PIN_AG8 };
|
||||
static const unsigned pwl_b_2_pins[] = { DB8500_PIN_AF8 };
|
||||
static const unsigned pwl_b_3_pins[] = { DB8500_PIN_AG7 };
|
||||
static const unsigned pwl_b_4_pins[] = { DB8500_PIN_AF7 };
|
||||
|
||||
/* Altfunction C column */
|
||||
static const unsigned ipjtag_c_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3,
|
||||
DB8500_PIN_AH4, DB8500_PIN_AH3, DB8500_PIN_AH6 };
|
||||
static const unsigned ipgpio6_c_1_pins[] = { DB8500_PIN_AG6 };
|
||||
static const unsigned ipgpio0_c_1_pins[] = { DB8500_PIN_AF6 };
|
||||
static const unsigned ipgpio1_c_1_pins[] = { DB8500_PIN_AG5 };
|
||||
static const unsigned ipgpio3_c_1_pins[] = { DB8500_PIN_AF5 };
|
||||
static const unsigned ipgpio2_c_1_pins[] = { DB8500_PIN_AG4 };
|
||||
static const unsigned slim0_c_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
|
||||
/* Optional 4-bit Memory Stick interface */
|
||||
static const unsigned ms_c_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1,
|
||||
DB8500_PIN_AB3, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2,
|
||||
DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
|
||||
static const unsigned iptrigout_c_1_pins[] = { DB8500_PIN_AB4 };
|
||||
static const unsigned u2rxtx_c_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3 };
|
||||
static const unsigned u2ctsrts_c_1_pins[] = { DB8500_PIN_V3, DB8500_PIN_V2 };
|
||||
static const unsigned u0_c_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AE1,
|
||||
DB8500_PIN_AE2, DB8500_PIN_AG2 };
|
||||
static const unsigned ipgpio4_c_1_pins[] = { DB8500_PIN_F3 };
|
||||
static const unsigned ipgpio5_c_1_pins[] = { DB8500_PIN_F1 };
|
||||
static const unsigned ipgpio6_c_2_pins[] = { DB8500_PIN_G3 };
|
||||
static const unsigned ipgpio7_c_1_pins[] = { DB8500_PIN_G2 };
|
||||
static const unsigned smcleale_c_1_pins[] = { DB8500_PIN_E1, DB8500_PIN_E2 };
|
||||
static const unsigned stmape_c_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4,
|
||||
DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3 };
|
||||
static const unsigned u2rxtx_c_2_pins[] = { DB8500_PIN_H2, DB8500_PIN_J2 };
|
||||
static const unsigned ipgpio2_c_2_pins[] = { DB8500_PIN_F4 };
|
||||
static const unsigned ipgpio3_c_2_pins[] = { DB8500_PIN_E3 };
|
||||
static const unsigned ipgpio4_c_2_pins[] = { DB8500_PIN_E4 };
|
||||
static const unsigned ipgpio5_c_2_pins[] = { DB8500_PIN_D2 };
|
||||
static const unsigned mc5_c_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
|
||||
DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
|
||||
DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8,
|
||||
DB8500_PIN_D9 };
|
||||
static const unsigned mc2rstn_c_1_pins[] = { DB8500_PIN_C8 };
|
||||
static const unsigned kp_c_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11,
|
||||
DB8500_PIN_C12, DB8500_PIN_C11, DB8500_PIN_D17, DB8500_PIN_D16,
|
||||
DB8500_PIN_C23, DB8500_PIN_D23 };
|
||||
static const unsigned smps1_c_1_pins[] = { DB8500_PIN_B14 };
|
||||
static const unsigned u2rxtx_c_3_pins[] = { DB8500_PIN_B17, DB8500_PIN_C16 };
|
||||
static const unsigned stmape_c_2_pins[] = { DB8500_PIN_C19, DB8500_PIN_C17,
|
||||
DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19 };
|
||||
static const unsigned uartmodrx_c_1_pins[] = { DB8500_PIN_D21 };
|
||||
static const unsigned uartmodtx_c_1_pins[] = { DB8500_PIN_D20 };
|
||||
static const unsigned stmmod_c_1_pins[] = { DB8500_PIN_C20, DB8500_PIN_B21,
|
||||
DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24 };
|
||||
static const unsigned usbsim_c_1_pins[] = { DB8500_PIN_D22 };
|
||||
static const unsigned mc4rstn_c_1_pins[] = { DB8500_PIN_AF25 };
|
||||
static const unsigned clkout_c_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AH12 };
|
||||
static const unsigned i2c3_c_1_pins[] = { DB8500_PIN_AG12, DB8500_PIN_AH11 };
|
||||
static const unsigned spi0_c_1_pins[] = { DB8500_PIN_AH10, DB8500_PIN_AH9,
|
||||
DB8500_PIN_AG9, DB8500_PIN_AG8 };
|
||||
static const unsigned usbsim_c_2_pins[] = { DB8500_PIN_AF8 };
|
||||
static const unsigned i2c3_c_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 };
|
||||
|
||||
/* Other C1 column */
|
||||
static const unsigned kp_oc1_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
|
||||
DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
|
||||
DB8500_PIN_D6, DB8500_PIN_B7 };
|
||||
static const unsigned spi2_oc1_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
|
||||
DB8500_PIN_AH12, DB8500_PIN_AH11 };
|
||||
|
||||
#define DB8500_PIN_GROUP(a,b) { .name = #a, .pins = a##_pins, \
|
||||
.npins = ARRAY_SIZE(a##_pins), .altsetting = b }
|
||||
|
||||
static const struct nmk_pingroup nmk_db8500_groups[] = {
|
||||
/* Altfunction A column */
|
||||
DB8500_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(clkout_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(clkout_a_2, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A),
|
||||
/* Altfunction B column */
|
||||
DB8500_PIN_GROUP(trig_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(u2rxtx_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(uartmodtx_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(msp0sck_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(uartmodrx_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(uartmodrx_b_2, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(spi3_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(lcdaclk_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(lcda_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(lcd_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B),
|
||||
DB8500_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B),
|
||||
/* Altfunction C column */
|
||||
DB8500_PIN_GROUP(ipjtag_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(slim0_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(ms_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(iptrigout_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(u2ctsrts_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(u2rxtx_c_2, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(u2rxtx_c_3, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(stmape_c_2, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(uartmodrx_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(uartmodtx_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(stmmod_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(usbsim_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(clkout_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(usbsim_c_2, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(i2c3_c_2, NMK_GPIO_ALT_C),
|
||||
/* Other alt C1 column, these are still configured as alt C */
|
||||
DB8500_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C),
|
||||
DB8500_PIN_GROUP(spi2_oc1_1, NMK_GPIO_ALT_C),
|
||||
};
|
||||
|
||||
/* We use this macro to define the groups applicable to a function */
|
||||
#define DB8500_FUNC_GROUPS(a, b...) \
|
||||
static const char * const a##_groups[] = { b };
|
||||
|
||||
DB8500_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1");
|
||||
DB8500_FUNC_GROUPS(u1, "u1rxtx_a_1", "u1ctsrts_a_1");
|
||||
/*
|
||||
* UART2 can be muxed out with just RX/TX in four places, CTS+RTS is however
|
||||
* only available on two pins in alternative function C
|
||||
*/
|
||||
DB8500_FUNC_GROUPS(u2, "u2rxtx_b_1", "u2rxtx_c_1", "u2ctsrts_c_1",
|
||||
"u2rxtx_c_2", "u2rxtx_c_3");
|
||||
DB8500_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2");
|
||||
/*
|
||||
* MSP0 can only be on a certain set of pins, but the TX/RX pins can be
|
||||
* switched around by selecting the altfunction A or B. The SCK pin is
|
||||
* only available on the altfunction B.
|
||||
*/
|
||||
DB8500_FUNC_GROUPS(msp0, "msp0txrx_a_1", "msp0tfstck_a_1", "msp0rfstck_a_1",
|
||||
"msp0txrx_b_1", "msp0sck_b_1");
|
||||
DB8500_FUNC_GROUPS(mc0, "mc0_a_1");
|
||||
/* MSP0 can swap RX/TX like MSP0 but has no SCK pin available */
|
||||
DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1");
|
||||
DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1");
|
||||
DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1",
|
||||
"lcd_d8_d11_a_1", "lcd_d12_d23_a_1", "lcd_b_1");
|
||||
DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1");
|
||||
DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1");
|
||||
DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1");
|
||||
DB8500_FUNC_GROUPS(ssp0, "ssp0_a_1");
|
||||
DB8500_FUNC_GROUPS(i2c0, "i2c0_a_1");
|
||||
/* The image processor has 8 GPIO pins that can be muxed out */
|
||||
DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1",
|
||||
"ipgpio2_b_1", "ipgpio3_b_1", "ipgpio6_c_1", "ipgpio0_c_1",
|
||||
"ipgpio1_c_1", "ipgpio3_c_1", "ipgpio2_c_1", "ipgpio4_c_1",
|
||||
"ipgpio5_c_1", "ipgpio6_c_2", "ipgpio7_c_1", "ipgpio2_c_2",
|
||||
"ipgpio3_c_2", "ipgpio4_c_2", "ipgpio5_c_2");
|
||||
/* MSP2 can not invert the RX/TX pins but has the optional SCK pin */
|
||||
DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1");
|
||||
DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
|
||||
DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1dir_a_1");
|
||||
DB8500_FUNC_GROUPS(hsi, "hsir1_a_1", "hsit1_a_1");
|
||||
DB8500_FUNC_GROUPS(clkout, "clkout_a_1", "clkout_a_2", "clkout_c_1");
|
||||
DB8500_FUNC_GROUPS(usb, "usb_a_1");
|
||||
DB8500_FUNC_GROUPS(trig, "trig_b_1");
|
||||
DB8500_FUNC_GROUPS(i2c4, "i2c4_b_1");
|
||||
DB8500_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2");
|
||||
DB8500_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2");
|
||||
/*
|
||||
* The modem UART can output its RX and TX pins in some different places,
|
||||
* so select one of each.
|
||||
*/
|
||||
DB8500_FUNC_GROUPS(uartmod, "uartmodtx_b_1", "uartmodrx_b_1", "uartmodrx_b_2",
|
||||
"uartmodrx_c_1", "uartmod_tx_c_1");
|
||||
DB8500_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_c_1");
|
||||
DB8500_FUNC_GROUPS(spi3, "spi3_b_1");
|
||||
/* Select between CS0 on alt B or PS1 on alt C */
|
||||
DB8500_FUNC_GROUPS(sm, "sm_b_1", "smcs0_b_1", "smcleale_c_1", "smps1_c_1");
|
||||
DB8500_FUNC_GROUPS(lcda, "lcdaclk_b_1", "lcda_b_1");
|
||||
DB8500_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1");
|
||||
DB8500_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4");
|
||||
DB8500_FUNC_GROUPS(spi1, "spi1_b_1");
|
||||
DB8500_FUNC_GROUPS(mc3, "mc3_b_1");
|
||||
DB8500_FUNC_GROUPS(ipjtag, "ipjtag_c_1");
|
||||
DB8500_FUNC_GROUPS(slim0, "slim0_c_1");
|
||||
DB8500_FUNC_GROUPS(ms, "ms_c_1");
|
||||
DB8500_FUNC_GROUPS(iptrigout, "iptrigout_c_1");
|
||||
DB8500_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_c_2");
|
||||
DB8500_FUNC_GROUPS(mc5, "mc5_c_1");
|
||||
DB8500_FUNC_GROUPS(usbsim, "usbsim_c_1", "usbsim_c_2");
|
||||
DB8500_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c3_c_2");
|
||||
DB8500_FUNC_GROUPS(spi0, "spi0_c_1");
|
||||
DB8500_FUNC_GROUPS(spi2, "spi2_oc1_1");
|
||||
|
||||
#define FUNCTION(fname) \
|
||||
{ \
|
||||
.name = #fname, \
|
||||
.groups = fname##_groups, \
|
||||
.ngroups = ARRAY_SIZE(fname##_groups), \
|
||||
}
|
||||
|
||||
static const struct nmk_function nmk_db8500_functions[] = {
|
||||
FUNCTION(u0),
|
||||
FUNCTION(u1),
|
||||
FUNCTION(u2),
|
||||
FUNCTION(ipi2c),
|
||||
FUNCTION(msp0),
|
||||
FUNCTION(mc0),
|
||||
FUNCTION(msp1),
|
||||
FUNCTION(lcdb),
|
||||
FUNCTION(lcd),
|
||||
FUNCTION(kp),
|
||||
FUNCTION(mc2),
|
||||
FUNCTION(ssp1),
|
||||
FUNCTION(ssp0),
|
||||
FUNCTION(i2c0),
|
||||
FUNCTION(ipgpio),
|
||||
FUNCTION(msp2),
|
||||
FUNCTION(mc4),
|
||||
FUNCTION(mc1),
|
||||
FUNCTION(hsi),
|
||||
FUNCTION(clkout),
|
||||
FUNCTION(usb),
|
||||
FUNCTION(trig),
|
||||
FUNCTION(i2c4),
|
||||
FUNCTION(i2c1),
|
||||
FUNCTION(i2c2),
|
||||
FUNCTION(uartmod),
|
||||
FUNCTION(stmmod),
|
||||
FUNCTION(spi3),
|
||||
FUNCTION(sm),
|
||||
FUNCTION(lcda),
|
||||
FUNCTION(ddrtrig),
|
||||
FUNCTION(pwl),
|
||||
FUNCTION(spi1),
|
||||
FUNCTION(mc3),
|
||||
FUNCTION(ipjtag),
|
||||
FUNCTION(slim0),
|
||||
FUNCTION(ms),
|
||||
FUNCTION(iptrigout),
|
||||
FUNCTION(stmape),
|
||||
FUNCTION(mc5),
|
||||
FUNCTION(usbsim),
|
||||
FUNCTION(i2c3),
|
||||
FUNCTION(spi0),
|
||||
FUNCTION(spi2),
|
||||
};
|
||||
|
||||
static const struct nmk_pinctrl_soc_data nmk_db8500_soc = {
|
||||
.gpio_ranges = nmk_db8500_ranges,
|
||||
.gpio_num_ranges = ARRAY_SIZE(nmk_db8500_ranges),
|
||||
.pins = nmk_db8500_pins,
|
||||
.npins = ARRAY_SIZE(nmk_db8500_pins),
|
||||
.functions = nmk_db8500_functions,
|
||||
.nfunctions = ARRAY_SIZE(nmk_db8500_functions),
|
||||
.groups = nmk_db8500_groups,
|
||||
.ngroups = ARRAY_SIZE(nmk_db8500_groups),
|
||||
};
|
||||
|
||||
void __devinit
|
||||
nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
|
||||
{
|
||||
*soc = &nmk_db8500_soc;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,77 @@
|
|||
#ifndef PINCTRL_PINCTRL_NOMADIK_H
|
||||
#define PINCTRL_PINCTRL_NOMADIK_H
|
||||
|
||||
#include <plat/gpio-nomadik.h>
|
||||
|
||||
/* Package definitions */
|
||||
#define PINCTRL_NMK_STN8815 0
|
||||
#define PINCTRL_NMK_DB8500 1
|
||||
|
||||
/**
|
||||
* struct nmk_function - Nomadik pinctrl mux function
|
||||
* @name: The name of the function, exported to pinctrl core.
|
||||
* @groups: An array of pin groups that may select this function.
|
||||
* @ngroups: The number of entries in @groups.
|
||||
*/
|
||||
struct nmk_function {
|
||||
const char *name;
|
||||
const char * const *groups;
|
||||
unsigned ngroups;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct nmk_pingroup - describes a Nomadik pin group
|
||||
* @name: the name of this specific pin group
|
||||
* @pins: an array of discrete physical pins used in this group, taken
|
||||
* from the driver-local pin enumeration space
|
||||
* @num_pins: the number of pins in this group array, i.e. the number of
|
||||
* elements in .pins so we can iterate over that array
|
||||
* @altsetting: the altsetting to apply to all pins in this group to
|
||||
* configure them to be used by a function
|
||||
*/
|
||||
struct nmk_pingroup {
|
||||
const char *name;
|
||||
const unsigned int *pins;
|
||||
const unsigned npins;
|
||||
int altsetting;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct nmk_pinctrl_soc_data - Nomadik pin controller per-SoC configuration
|
||||
* @gpio_ranges: An array of GPIO ranges for this SoC
|
||||
* @gpio_num_ranges: The number of GPIO ranges for this SoC
|
||||
* @pins: An array describing all pins the pin controller affects.
|
||||
* All pins which are also GPIOs must be listed first within the
|
||||
* array, and be numbered identically to the GPIO controller's
|
||||
* numbering.
|
||||
* @npins: The number of entries in @pins.
|
||||
* @functions: The functions supported on this SoC.
|
||||
* @nfunction: The number of entries in @functions.
|
||||
* @groups: An array describing all pin groups the pin SoC supports.
|
||||
* @ngroups: The number of entries in @groups.
|
||||
*/
|
||||
struct nmk_pinctrl_soc_data {
|
||||
struct pinctrl_gpio_range *gpio_ranges;
|
||||
unsigned gpio_num_ranges;
|
||||
const struct pinctrl_pin_desc *pins;
|
||||
unsigned npins;
|
||||
const struct nmk_function *functions;
|
||||
unsigned nfunctions;
|
||||
const struct nmk_pingroup *groups;
|
||||
unsigned ngroups;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_DB8500
|
||||
|
||||
void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc);
|
||||
|
||||
#else
|
||||
|
||||
static inline void
|
||||
nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* PINCTRL_PINCTRL_NOMADIK_H */
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Driver for the NVIDIA Tegra pinmux
|
||||
*
|
||||
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Derived from code:
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
|
|
@ -22,7 +22,8 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/pinmux.h>
|
||||
|
|
@ -31,10 +32,9 @@
|
|||
|
||||
#include <mach/pinconf-tegra.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "pinctrl-tegra.h"
|
||||
|
||||
#define DRIVER_NAME "tegra-pinmux-disabled"
|
||||
|
||||
struct tegra_pmx {
|
||||
struct device *dev;
|
||||
struct pinctrl_dev *pctl;
|
||||
|
|
@ -83,15 +83,18 @@ static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s,
|
||||
unsigned offset)
|
||||
{
|
||||
seq_printf(s, " " DRIVER_NAME);
|
||||
seq_printf(s, " %s", dev_name(pctldev->dev));
|
||||
}
|
||||
#endif
|
||||
|
||||
static int reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
|
||||
unsigned *num_maps, unsigned reserve)
|
||||
static int reserve_map(struct device *dev, struct pinctrl_map **map,
|
||||
unsigned *reserved_maps, unsigned *num_maps,
|
||||
unsigned reserve)
|
||||
{
|
||||
unsigned old_num = *reserved_maps;
|
||||
unsigned new_num = *num_maps + reserve;
|
||||
|
|
@ -101,8 +104,10 @@ static int reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
|
|||
return 0;
|
||||
|
||||
new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
|
||||
if (!new_map)
|
||||
if (!new_map) {
|
||||
dev_err(dev, "krealloc(map) failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
|
||||
|
||||
|
|
@ -116,7 +121,7 @@ static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
|
|||
unsigned *num_maps, const char *group,
|
||||
const char *function)
|
||||
{
|
||||
if (*num_maps == *reserved_maps)
|
||||
if (WARN_ON(*num_maps == *reserved_maps))
|
||||
return -ENOSPC;
|
||||
|
||||
(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
|
||||
|
|
@ -127,19 +132,22 @@ static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int add_map_configs(struct pinctrl_map **map, unsigned *reserved_maps,
|
||||
unsigned *num_maps, const char *group,
|
||||
unsigned long *configs, unsigned num_configs)
|
||||
static int add_map_configs(struct device *dev, struct pinctrl_map **map,
|
||||
unsigned *reserved_maps, unsigned *num_maps,
|
||||
const char *group, unsigned long *configs,
|
||||
unsigned num_configs)
|
||||
{
|
||||
unsigned long *dup_configs;
|
||||
|
||||
if (*num_maps == *reserved_maps)
|
||||
if (WARN_ON(*num_maps == *reserved_maps))
|
||||
return -ENOSPC;
|
||||
|
||||
dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
|
||||
GFP_KERNEL);
|
||||
if (!dup_configs)
|
||||
if (!dup_configs) {
|
||||
dev_err(dev, "kmemdup(configs) failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
(*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
|
||||
(*map)[*num_maps].data.configs.group_or_pin = group;
|
||||
|
|
@ -150,8 +158,8 @@ static int add_map_configs(struct pinctrl_map **map, unsigned *reserved_maps,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int add_config(unsigned long **configs, unsigned *num_configs,
|
||||
unsigned long config)
|
||||
static int add_config(struct device *dev, unsigned long **configs,
|
||||
unsigned *num_configs, unsigned long config)
|
||||
{
|
||||
unsigned old_num = *num_configs;
|
||||
unsigned new_num = old_num + 1;
|
||||
|
|
@ -159,8 +167,10 @@ static int add_config(unsigned long **configs, unsigned *num_configs,
|
|||
|
||||
new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
|
||||
GFP_KERNEL);
|
||||
if (!new_configs)
|
||||
if (!new_configs) {
|
||||
dev_err(dev, "krealloc(configs) failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
new_configs[old_num] = config;
|
||||
|
||||
|
|
@ -201,7 +211,8 @@ static const struct cfg_param {
|
|||
{"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
|
||||
};
|
||||
|
||||
int tegra_pinctrl_dt_subnode_to_map(struct device_node *np,
|
||||
int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
|
||||
struct device_node *np,
|
||||
struct pinctrl_map **map,
|
||||
unsigned *reserved_maps,
|
||||
unsigned *num_maps)
|
||||
|
|
@ -217,16 +228,25 @@ int tegra_pinctrl_dt_subnode_to_map(struct device_node *np,
|
|||
const char *group;
|
||||
|
||||
ret = of_property_read_string(np, "nvidia,function", &function);
|
||||
if (ret < 0)
|
||||
if (ret < 0) {
|
||||
/* EINVAL=missing, which is fine since it's optional */
|
||||
if (ret != -EINVAL)
|
||||
dev_err(dev,
|
||||
"could not parse property nvidia,function\n");
|
||||
function = NULL;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
|
||||
ret = of_property_read_u32(np, cfg_params[i].property, &val);
|
||||
if (!ret) {
|
||||
config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
|
||||
ret = add_config(&configs, &num_configs, config);
|
||||
ret = add_config(dev, &configs, &num_configs, config);
|
||||
if (ret < 0)
|
||||
goto exit;
|
||||
/* EINVAL=missing, which is fine since it's optional */
|
||||
} else if (ret != -EINVAL) {
|
||||
dev_err(dev, "could not parse property %s\n",
|
||||
cfg_params[i].property);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -236,11 +256,13 @@ int tegra_pinctrl_dt_subnode_to_map(struct device_node *np,
|
|||
if (num_configs)
|
||||
reserve++;
|
||||
ret = of_property_count_strings(np, "nvidia,pins");
|
||||
if (ret < 0)
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "could not parse property nvidia,pins\n");
|
||||
goto exit;
|
||||
}
|
||||
reserve *= ret;
|
||||
|
||||
ret = reserve_map(map, reserved_maps, num_maps, reserve);
|
||||
ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
|
||||
if (ret < 0)
|
||||
goto exit;
|
||||
|
||||
|
|
@ -253,8 +275,9 @@ int tegra_pinctrl_dt_subnode_to_map(struct device_node *np,
|
|||
}
|
||||
|
||||
if (num_configs) {
|
||||
ret = add_map_configs(map, reserved_maps, num_maps,
|
||||
group, configs, num_configs);
|
||||
ret = add_map_configs(dev, map, reserved_maps,
|
||||
num_maps, group, configs,
|
||||
num_configs);
|
||||
if (ret < 0)
|
||||
goto exit;
|
||||
}
|
||||
|
|
@ -280,8 +303,8 @@ int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
|||
*num_maps = 0;
|
||||
|
||||
for_each_child_of_node(np_config, np) {
|
||||
ret = tegra_pinctrl_dt_subnode_to_map(np, map, &reserved_maps,
|
||||
num_maps);
|
||||
ret = tegra_pinctrl_dt_subnode_to_map(pctldev->dev, np, map,
|
||||
&reserved_maps, num_maps);
|
||||
if (ret < 0) {
|
||||
tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
|
||||
return ret;
|
||||
|
|
@ -295,7 +318,9 @@ static struct pinctrl_ops tegra_pinctrl_ops = {
|
|||
.get_groups_count = tegra_pinctrl_get_groups_count,
|
||||
.get_group_name = tegra_pinctrl_get_group_name,
|
||||
.get_group_pins = tegra_pinctrl_get_group_pins,
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
.pin_dbg_show = tegra_pinctrl_pin_dbg_show,
|
||||
#endif
|
||||
.dt_node_to_map = tegra_pinctrl_dt_node_to_map,
|
||||
.dt_free_map = tegra_pinctrl_dt_free_map,
|
||||
};
|
||||
|
|
@ -338,14 +363,14 @@ static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
|
|||
|
||||
g = &pmx->soc->groups[group];
|
||||
|
||||
if (g->mux_reg < 0)
|
||||
if (WARN_ON(g->mux_reg < 0))
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
|
||||
if (g->funcs[i] == function)
|
||||
break;
|
||||
}
|
||||
if (i == ARRAY_SIZE(g->funcs))
|
||||
if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
|
||||
return -EINVAL;
|
||||
|
||||
val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
|
||||
|
|
@ -365,7 +390,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
|
|||
|
||||
g = &pmx->soc->groups[group];
|
||||
|
||||
if (g->mux_reg < 0)
|
||||
if (WARN_ON(g->mux_reg < 0))
|
||||
return;
|
||||
|
||||
val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
|
||||
|
|
@ -385,6 +410,7 @@ static struct pinmux_ops tegra_pinmux_ops = {
|
|||
static int tegra_pinconf_reg(struct tegra_pmx *pmx,
|
||||
const struct tegra_pingroup *g,
|
||||
enum tegra_pinconf_param param,
|
||||
bool report_err,
|
||||
s8 *bank, s16 *reg, s8 *bit, s8 *width)
|
||||
{
|
||||
switch (param) {
|
||||
|
|
@ -472,9 +498,10 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
|
|||
}
|
||||
|
||||
if (*reg < 0) {
|
||||
dev_err(pmx->dev,
|
||||
"Config param %04x not supported on group %s\n",
|
||||
param, g->name);
|
||||
if (report_err)
|
||||
dev_err(pmx->dev,
|
||||
"Config param %04x not supported on group %s\n",
|
||||
param, g->name);
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
|
|
@ -484,12 +511,14 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
|
|||
static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
|
||||
unsigned pin, unsigned long *config)
|
||||
{
|
||||
dev_err(pctldev->dev, "pin_config_get op not supported\n");
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
|
||||
unsigned pin, unsigned long config)
|
||||
{
|
||||
dev_err(pctldev->dev, "pin_config_set op not supported\n");
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
|
|
@ -507,7 +536,8 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
|
|||
|
||||
g = &pmx->soc->groups[group];
|
||||
|
||||
ret = tegra_pinconf_reg(pmx, g, param, &bank, ®, &bit, &width);
|
||||
ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
|
||||
&width);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
|
@ -534,7 +564,8 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
|
|||
|
||||
g = &pmx->soc->groups[group];
|
||||
|
||||
ret = tegra_pinconf_reg(pmx, g, param, &bank, ®, &bit, &width);
|
||||
ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
|
||||
&width);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
|
@ -542,8 +573,10 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
|
|||
|
||||
/* LOCK can't be cleared */
|
||||
if (param == TEGRA_PINCONF_PARAM_LOCK) {
|
||||
if ((val & BIT(bit)) && !arg)
|
||||
if ((val & BIT(bit)) && !arg) {
|
||||
dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
/* Special-case Boolean values; allow any non-zero as true */
|
||||
|
|
@ -552,8 +585,12 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
|
|||
|
||||
/* Range-check user-supplied value */
|
||||
mask = (1 << width) - 1;
|
||||
if (arg & ~mask)
|
||||
if (arg & ~mask) {
|
||||
dev_err(pctldev->dev,
|
||||
"config %lx: %x too big for %d bit register\n",
|
||||
config, arg, width);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Update register */
|
||||
val &= ~(mask << bit);
|
||||
|
|
@ -563,23 +600,78 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s, unsigned offset)
|
||||
{
|
||||
}
|
||||
|
||||
static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s, unsigned selector)
|
||||
static const char *strip_prefix(const char *s)
|
||||
{
|
||||
const char *comma = strchr(s, ',');
|
||||
if (!comma)
|
||||
return s;
|
||||
|
||||
return comma + 1;
|
||||
}
|
||||
|
||||
static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s, unsigned group)
|
||||
{
|
||||
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
const struct tegra_pingroup *g;
|
||||
int i, ret;
|
||||
s8 bank, bit, width;
|
||||
s16 reg;
|
||||
u32 val;
|
||||
|
||||
g = &pmx->soc->groups[group];
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
|
||||
ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
|
||||
&bank, ®, &bit, &width);
|
||||
if (ret < 0)
|
||||
continue;
|
||||
|
||||
val = pmx_readl(pmx, bank, reg);
|
||||
val >>= bit;
|
||||
val &= (1 << width) - 1;
|
||||
|
||||
seq_printf(s, "\n\t%s=%u",
|
||||
strip_prefix(cfg_params[i].property), val);
|
||||
}
|
||||
}
|
||||
|
||||
static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s,
|
||||
unsigned long config)
|
||||
{
|
||||
enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
|
||||
u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
|
||||
const char *pname = "unknown";
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
|
||||
if (cfg_params[i].param == param) {
|
||||
pname = cfg_params[i].property;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
seq_printf(s, "%s=%d", strip_prefix(pname), arg);
|
||||
}
|
||||
#endif
|
||||
|
||||
struct pinconf_ops tegra_pinconf_ops = {
|
||||
.pin_config_get = tegra_pinconf_get,
|
||||
.pin_config_set = tegra_pinconf_set,
|
||||
.pin_config_group_get = tegra_pinconf_group_get,
|
||||
.pin_config_group_set = tegra_pinconf_group_set,
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
.pin_config_dbg_show = tegra_pinconf_dbg_show,
|
||||
.pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
|
||||
.pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
|
||||
|
|
@ -589,60 +681,29 @@ static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
|
|||
};
|
||||
|
||||
static struct pinctrl_desc tegra_pinctrl_desc = {
|
||||
.name = DRIVER_NAME,
|
||||
.pctlops = &tegra_pinctrl_ops,
|
||||
.pmxops = &tegra_pinmux_ops,
|
||||
.confops = &tegra_pinconf_ops,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static struct of_device_id tegra_pinctrl_of_match[] __devinitdata = {
|
||||
#ifdef CONFIG_PINCTRL_TEGRA20
|
||||
{
|
||||
.compatible = "nvidia,tegra20-pinmux-disabled",
|
||||
.data = tegra20_pinctrl_init,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_TEGRA30
|
||||
{
|
||||
.compatible = "nvidia,tegra30-pinmux-disabled",
|
||||
.data = tegra30_pinctrl_init,
|
||||
},
|
||||
#endif
|
||||
{},
|
||||
};
|
||||
|
||||
static int __devinit tegra_pinctrl_probe(struct platform_device *pdev)
|
||||
int __devinit tegra_pinctrl_probe(struct platform_device *pdev,
|
||||
const struct tegra_pinctrl_soc_data *soc_data)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
tegra_pinctrl_soc_initf initf = NULL;
|
||||
struct tegra_pmx *pmx;
|
||||
struct resource *res;
|
||||
int i;
|
||||
|
||||
match = of_match_device(tegra_pinctrl_of_match, &pdev->dev);
|
||||
if (match)
|
||||
initf = (tegra_pinctrl_soc_initf)match->data;
|
||||
#ifdef CONFIG_PINCTRL_TEGRA20
|
||||
if (!initf)
|
||||
initf = tegra20_pinctrl_init;
|
||||
#endif
|
||||
if (!initf) {
|
||||
dev_err(&pdev->dev,
|
||||
"Could not determine SoC-specific init func\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
|
||||
if (!pmx) {
|
||||
dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
pmx->dev = &pdev->dev;
|
||||
|
||||
(*initf)(&pmx->soc);
|
||||
pmx->soc = soc_data;
|
||||
|
||||
tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
|
||||
tegra_pinctrl_desc.name = dev_name(&pdev->dev);
|
||||
tegra_pinctrl_desc.pins = pmx->soc->pins;
|
||||
tegra_pinctrl_desc.npins = pmx->soc->npins;
|
||||
|
||||
|
|
@ -697,8 +758,9 @@ static int __devinit tegra_pinctrl_probe(struct platform_device *pdev)
|
|||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
|
||||
|
||||
static int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
|
||||
int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra_pmx *pmx = platform_get_drvdata(pdev);
|
||||
|
||||
|
|
@ -707,30 +769,4 @@ static int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver tegra_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = tegra_pinctrl_of_match,
|
||||
},
|
||||
.probe = tegra_pinctrl_probe,
|
||||
.remove = __devexit_p(tegra_pinctrl_remove),
|
||||
};
|
||||
|
||||
static int __init tegra_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&tegra_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(tegra_pinctrl_init);
|
||||
|
||||
static void __exit tegra_pinctrl_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&tegra_pinctrl_driver);
|
||||
}
|
||||
module_exit(tegra_pinctrl_exit);
|
||||
|
||||
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
|
||||
MODULE_DESCRIPTION("NVIDIA Tegra pinctrl driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DEVICE_TABLE(of, tegra_pinctrl_of_match);
|
||||
EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);
|
||||
|
|
|
|||
|
|
@ -139,25 +139,8 @@ struct tegra_pinctrl_soc_data {
|
|||
unsigned ngroups;
|
||||
};
|
||||
|
||||
/**
|
||||
* tegra_pinctrl_soc_initf() - Retrieve pin controller details for a SoC.
|
||||
* @soc_data: This pointer must be updated to point at a struct containing
|
||||
* details of the SoC.
|
||||
*/
|
||||
typedef void (*tegra_pinctrl_soc_initf)(
|
||||
const struct tegra_pinctrl_soc_data **soc_data);
|
||||
|
||||
/**
|
||||
* tegra20_pinctrl_init() - Retrieve pin controller details for Tegra20
|
||||
* @soc_data: This pointer will be updated to point at a struct containing
|
||||
* details of Tegra20's pin controller.
|
||||
*/
|
||||
void tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc_data);
|
||||
/**
|
||||
* tegra30_pinctrl_init() - Retrieve pin controller details for Tegra20
|
||||
* @soc_data: This pointer will be updated to point at a struct containing
|
||||
* details of Tegra30's pin controller.
|
||||
*/
|
||||
void tegra30_pinctrl_init(const struct tegra_pinctrl_soc_data **soc_data);
|
||||
int tegra_pinctrl_probe(struct platform_device *pdev,
|
||||
const struct tegra_pinctrl_soc_data *soc_data);
|
||||
int tegra_pinctrl_remove(struct platform_device *pdev);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Pinctrl data for the NVIDIA Tegra20 pinmux
|
||||
*
|
||||
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Derived from code:
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
|
|
@ -17,6 +17,8 @@
|
|||
* more details.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/pinmux.h>
|
||||
|
|
@ -2854,7 +2856,39 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
|
|||
.ngroups = ARRAY_SIZE(tegra20_groups),
|
||||
};
|
||||
|
||||
void __devinit tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc)
|
||||
static int __devinit tegra20_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
*soc = &tegra20_pinctrl;
|
||||
return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
|
||||
}
|
||||
|
||||
static struct of_device_id tegra20_pinctrl_of_match[] __devinitdata = {
|
||||
{ .compatible = "nvidia,tegra20-pinmux", },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct platform_driver tegra20_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "tegra20-pinctrl",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = tegra20_pinctrl_of_match,
|
||||
},
|
||||
.probe = tegra20_pinctrl_probe,
|
||||
.remove = __devexit_p(tegra_pinctrl_remove),
|
||||
};
|
||||
|
||||
static int __init tegra20_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&tegra20_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(tegra20_pinctrl_init);
|
||||
|
||||
static void __exit tegra20_pinctrl_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&tegra20_pinctrl_driver);
|
||||
}
|
||||
module_exit(tegra20_pinctrl_exit);
|
||||
|
||||
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
|
||||
MODULE_DESCRIPTION("NVIDIA Tegra20 pinctrl driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DEVICE_TABLE(of, tegra20_pinctrl_of_match);
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Pinctrl data for the NVIDIA Tegra30 pinmux
|
||||
*
|
||||
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
|
|
@ -13,6 +13,8 @@
|
|||
* more details.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/pinmux.h>
|
||||
|
|
@ -3720,7 +3722,39 @@ static const struct tegra_pinctrl_soc_data tegra30_pinctrl = {
|
|||
.ngroups = ARRAY_SIZE(tegra30_groups),
|
||||
};
|
||||
|
||||
void __devinit tegra30_pinctrl_init(const struct tegra_pinctrl_soc_data **soc)
|
||||
static int __devinit tegra30_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
*soc = &tegra30_pinctrl;
|
||||
return tegra_pinctrl_probe(pdev, &tegra30_pinctrl);
|
||||
}
|
||||
|
||||
static struct of_device_id tegra30_pinctrl_of_match[] __devinitdata = {
|
||||
{ .compatible = "nvidia,tegra30-pinmux", },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct platform_driver tegra30_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "tegra30-pinctrl",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = tegra30_pinctrl_of_match,
|
||||
},
|
||||
.probe = tegra30_pinctrl_probe,
|
||||
.remove = __devexit_p(tegra_pinctrl_remove),
|
||||
};
|
||||
|
||||
static int __init tegra30_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&tegra30_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(tegra30_pinctrl_init);
|
||||
|
||||
static void __exit tegra30_pinctrl_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&tegra30_pinctrl_driver);
|
||||
}
|
||||
module_exit(tegra30_pinctrl_exit);
|
||||
|
||||
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
|
||||
MODULE_DESCRIPTION("NVIDIA Tegra30 pinctrl driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match);
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue