e752x_edac: provide more info about how DIMMS/ranks are mapped
No funtional changes here. Only the comments got updated. Reviewed-by: Aristeu Rozanski <arozansk@redhat.com> Cc: Mark Gross <mark.gross@intel.com> Cc: Doug Thompson <norsk5@yahoo.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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@ -4,10 +4,11 @@
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* This file may be distributed under the terms of the
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* GNU General Public License.
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*
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* See "enum e752x_chips" below for supported chipsets
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* Implement support for the e7520, E7525, e7320 and i3100 memory controllers.
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*
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* Datasheet:
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* Datasheets:
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* http://www.intel.in/content/www/in/en/chipsets/e7525-memory-controller-hub-datasheet.html
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* ftp://download.intel.com/design/intarch/datashts/31345803.pdf
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*
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* Written by Tom Zimmerman
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*
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@ -16,8 +17,6 @@
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* Wang Zhenyu at intel.com
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* Dave Jiang at mvista.com
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*
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* $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
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*
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*/
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#include <linux/module.h>
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@ -190,6 +189,25 @@ enum e752x_chips {
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I3100 = 3
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};
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/*
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* Those chips Support single-rank and dual-rank memories only.
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*
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* On e752x chips, the odd rows are present only on dual-rank memories.
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* Dividing the rank by two will provide the dimm#
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*
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* i3100 MC has a different mapping: it supports only 4 ranks.
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*
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* The mapping is (from 1 to n):
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* slot single-ranked double-ranked
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* dimm #1 -> rank #4 NA
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* dimm #2 -> rank #3 NA
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* dimm #3 -> rank #2 Ranks 2 and 3
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* dimm #4 -> rank $1 Ranks 1 and 4
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*
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* FIXME: The current mapping for i3100 considers that it supports up to 8
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* ranks/chanel, but datasheet says that the MC supports only 4 ranks.
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*/
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struct e752x_pvt {
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struct pci_dev *bridge_ck;
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struct pci_dev *dev_d0f0;
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