[PATCH] adjust i386 watchdog tick calculation
Get the i386 watchdog tick calculation into a state where it can also be used on CPUs with frequencies beyond 4GHz, and it consolidates the calculation into a single place (for potential furture adjustments). Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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1 changed files with 15 additions and 9 deletions
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@ -28,8 +28,7 @@
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#include <linux/sysctl.h>
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#include <asm/smp.h>
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#include <asm/mtrr.h>
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#include <asm/mpspec.h>
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#include <asm/div64.h>
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#include <asm/nmi.h>
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#include "mach_traps.h"
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@ -324,6 +323,16 @@ static void clear_msr_range(unsigned int base, unsigned int n)
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wrmsr(base+i, 0, 0);
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}
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static inline void write_watchdog_counter(const char *descr)
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{
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u64 count = (u64)cpu_khz * 1000;
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do_div(count, nmi_hz);
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if(descr)
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Dprintk("setting %s to -0x%08Lx\n", descr, count);
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wrmsrl(nmi_perfctr_msr, 0 - count);
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}
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static void setup_k7_watchdog(void)
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{
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unsigned int evntsel;
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@ -339,8 +348,7 @@ static void setup_k7_watchdog(void)
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| K7_NMI_EVENT;
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wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
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Dprintk("setting K7_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
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wrmsr(MSR_K7_PERFCTR0, -(cpu_khz/nmi_hz*1000), -1);
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write_watchdog_counter("K7_PERFCTR0");
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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evntsel |= K7_EVNTSEL_ENABLE;
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wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
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@ -361,8 +369,7 @@ static void setup_p6_watchdog(void)
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| P6_NMI_EVENT;
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wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
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Dprintk("setting P6_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
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wrmsr(MSR_P6_PERFCTR0, -(cpu_khz/nmi_hz*1000), 0);
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write_watchdog_counter("P6_PERFCTR0");
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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evntsel |= P6_EVNTSEL0_ENABLE;
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wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
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@ -402,8 +409,7 @@ static int setup_p4_watchdog(void)
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wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
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wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
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Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000));
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wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1);
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write_watchdog_counter("P4_IQ_COUNTER0");
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
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return 1;
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@ -518,7 +524,7 @@ void nmi_watchdog_tick (struct pt_regs * regs)
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* other P6 variant */
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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}
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wrmsr(nmi_perfctr_msr, -(cpu_khz/nmi_hz*1000), -1);
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write_watchdog_counter(NULL);
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}
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}
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