ixgbe: Add SR-IOV register, structure and bit defines
This patch adds register definitions, bit definitions and structures used by the driver to support SR-IOV features of the 82599 controller. Signed-off-by: Greg Rose <gregory.v.rose@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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10ca132c41
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3 changed files with 83 additions and 3 deletions
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@ -98,6 +98,23 @@
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#define IXGBE_MAX_RSC_INT_RATE 162760
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#define IXGBE_MAX_VF_MC_ENTRIES 30
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#define IXGBE_MAX_VF_FUNCTIONS 64
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#define IXGBE_MAX_VFTA_ENTRIES 128
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#define MAX_EMULATION_MAC_ADDRS 16
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#define VMDQ_P(p) ((p) + adapter->num_vfs)
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struct vf_data_storage {
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unsigned char vf_mac_addresses[ETH_ALEN];
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u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
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u16 num_vf_mc_hashes;
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u16 default_vf_vlan_id;
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u16 vlans_enabled;
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unsigned char em_mac_addresses[MAX_EMULATION_MAC_ADDRS * ETH_ALEN];
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bool clear_to_send;
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int rar;
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};
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/* wrapper around a pointer to a socket buffer,
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* so a DMA handle can be stored along with the buffer */
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struct ixgbe_tx_buffer {
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@ -171,7 +188,7 @@ struct ixgbe_ring {
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enum ixgbe_ring_f_enum {
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RING_F_NONE = 0,
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RING_F_DCB,
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RING_F_VMDQ,
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RING_F_VMDQ, /* SR-IOV uses the same ring feature */
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RING_F_RSS,
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RING_F_FDIR,
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#ifdef IXGBE_FCOE
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@ -183,7 +200,7 @@ enum ixgbe_ring_f_enum {
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#define IXGBE_MAX_DCB_INDICES 8
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#define IXGBE_MAX_RSS_INDICES 16
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#define IXGBE_MAX_VMDQ_INDICES 16
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#define IXGBE_MAX_VMDQ_INDICES 64
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#define IXGBE_MAX_FDIR_INDICES 64
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#ifdef IXGBE_FCOE
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#define IXGBE_MAX_FCOE_INDICES 8
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@ -288,6 +305,8 @@ struct ixgbe_adapter {
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/* RX */
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struct ixgbe_ring *rx_ring ____cacheline_aligned_in_smp; /* One per active queue */
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int num_rx_queues;
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int num_rx_pools; /* == num_rx_queues in 82598 */
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int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
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u64 hw_csum_rx_error;
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u64 hw_rx_no_dma_resources;
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u64 non_eop_descs;
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@ -330,6 +349,8 @@ struct ixgbe_adapter {
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#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 27)
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#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 28)
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#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 29)
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#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 30)
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#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 31)
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u32 flags2;
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#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
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@ -379,6 +400,11 @@ struct ixgbe_adapter {
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u64 rsc_total_flush;
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u32 wol;
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u16 eeprom_version;
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/* SR-IOV */
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DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
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unsigned int num_vfs;
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struct vf_data_storage *vfinfo;
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};
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enum ixbge_state_t {
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@ -440,6 +466,7 @@ extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
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u16 flex_byte);
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extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
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u8 l4type);
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extern void ixgbe_set_rx_mode(struct net_device *netdev);
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#ifdef IXGBE_FCOE
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extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
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extern int ixgbe_fso(struct ixgbe_adapter *adapter,
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@ -2409,7 +2409,7 @@ static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
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* responsible for configuring the hardware for proper unicast, multicast and
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* promiscuous mode.
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**/
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static void ixgbe_set_rx_mode(struct net_device *netdev)
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void ixgbe_set_rx_mode(struct net_device *netdev)
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{
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struct ixgbe_adapter *adapter = netdev_priv(netdev);
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struct ixgbe_hw *hw = &adapter->hw;
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@ -277,6 +277,7 @@
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#define IXGBE_DTXCTL 0x07E00
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#define IXGBE_DMATXCTL 0x04A80
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#define IXGBE_PFDTXGSWC 0x08220
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#define IXGBE_DTXMXSZRQ 0x08100
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#define IXGBE_DTXTCPFLGL 0x04A88
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#define IXGBE_DTXTCPFLGH 0x04A8C
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@ -287,6 +288,8 @@
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#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
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#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
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#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
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#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
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#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
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/* Tx DCA Control register : 128 of these (0-127) */
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#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
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@ -497,6 +500,7 @@
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/* DCB registers */
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#define IXGBE_RTRPCS 0x02430
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#define IXGBE_RTTDCS 0x04900
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#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */
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#define IXGBE_RTTPCS 0x0CD00
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#define IXGBE_RTRUP2TC 0x03020
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#define IXGBE_RTTUP2TC 0x0C800
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@ -730,6 +734,13 @@
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#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000
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#define IXGBE_GCR_CAP_VER2 0x00040000
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#define IXGBE_GCR_EXT_MSIX_EN 0x80000000
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#define IXGBE_GCR_EXT_VT_MODE_16 0x00000001
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#define IXGBE_GCR_EXT_VT_MODE_32 0x00000002
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#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
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#define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
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IXGBE_GCR_EXT_VT_MODE_64)
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/* Time Sync Registers */
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#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
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#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
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@ -1065,6 +1076,8 @@
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/* VFRE bitmask */
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#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
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#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
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/* RDHMPN and TDHMPN bitmasks */
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#define IXGBE_RDHMPN_RDICADDR 0x007FF800
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#define IXGBE_RDHMPN_RDICRDREQ 0x00800000
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@ -1295,6 +1308,7 @@
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/* VLAN pool filtering masks */
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#define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */
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#define IXGBE_VLVF_ENTRIES 64
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#define IXGBE_VLVF_VLANID_MASK 0x00000FFF
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#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
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@ -1843,6 +1857,12 @@
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#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
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#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
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/* SR-IOV specific macros */
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#define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4)
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#define IXGBE_MBVFICR(_i) (0x00710 + (_i * 4))
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#define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600))
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#define IXGBE_VFLREC(_i) (0x00700 + (_i * 4))
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/* Little Endian defines */
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#ifndef __le32
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#define __le32 u32
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@ -2463,6 +2483,37 @@ struct ixgbe_phy_info {
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bool multispeed_fiber;
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};
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#include "ixgbe_mbx.h"
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struct ixgbe_mbx_operations {
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s32 (*init_params)(struct ixgbe_hw *hw);
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s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16);
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s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);
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s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16);
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s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
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s32 (*check_for_msg)(struct ixgbe_hw *, u16);
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s32 (*check_for_ack)(struct ixgbe_hw *, u16);
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s32 (*check_for_rst)(struct ixgbe_hw *, u16);
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};
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struct ixgbe_mbx_stats {
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u32 msgs_tx;
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u32 msgs_rx;
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u32 acks;
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u32 reqs;
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u32 rsts;
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};
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struct ixgbe_mbx_info {
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struct ixgbe_mbx_operations ops;
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struct ixgbe_mbx_stats stats;
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u32 timeout;
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u32 usec_delay;
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u32 v2p_mailbox;
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u16 size;
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};
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struct ixgbe_hw {
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u8 __iomem *hw_addr;
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void *back;
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@ -2472,6 +2523,7 @@ struct ixgbe_hw {
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struct ixgbe_phy_info phy;
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struct ixgbe_eeprom_info eeprom;
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struct ixgbe_bus_info bus;
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struct ixgbe_mbx_info mbx;
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u16 device_id;
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u16 vendor_id;
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u16 subsystem_device_id;
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@ -2486,6 +2538,7 @@ struct ixgbe_info {
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struct ixgbe_mac_operations *mac_ops;
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struct ixgbe_eeprom_operations *eeprom_ops;
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struct ixgbe_phy_operations *phy_ops;
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struct ixgbe_mbx_operations *mbx_ops;
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};
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