drm/radeon/kms: simplify r6xx blit code
Covert 4k pages to multiples of 64x64x4 tiles. This is also more efficient than a scanline based approach from the MC's perspective. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
eb32d0c34e
commit
7dbf41db32
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@ -2363,14 +2363,14 @@ int r600_copy_blit(struct radeon_device *rdev,
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mutex_lock(&rdev->r600_blit.mutex);
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rdev->r600_blit.vb_ib = NULL;
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r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
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r = r600_blit_prepare_copy(rdev, num_pages);
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if (r) {
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if (rdev->r600_blit.vb_ib)
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radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
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mutex_unlock(&rdev->r600_blit.mutex);
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return r;
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}
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r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
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r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages);
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r600_blit_done_copy(rdev, fence);
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mutex_unlock(&rdev->r600_blit.mutex);
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return 0;
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@ -42,6 +42,10 @@
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#define COLOR_5_6_5 0x8
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#define COLOR_8_8_8_8 0x1a
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#define RECT_UNIT_H 32
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#define RECT_UNIT_W (RADEON_GPU_PAGE_SIZE / 4 / RECT_UNIT_H)
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#define MAX_RECT_DIM 8192
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/* emits 21 on rv770+, 23 on r600 */
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static void
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set_render_target(struct radeon_device *rdev, int format,
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@ -600,13 +604,59 @@ static void r600_vb_ib_put(struct radeon_device *rdev)
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radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
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}
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int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
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/* FIXME: the function is very similar to evergreen_blit_create_rect, except
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that it different predefined constants; consider commonizing */
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static unsigned r600_blit_create_rect(unsigned num_pages, int *width, int *height)
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{
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unsigned max_pages;
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unsigned pages = num_pages;
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int w, h;
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if (num_pages == 0) {
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/* not supposed to be called with no pages, but just in case */
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h = 0;
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w = 0;
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pages = 0;
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WARN_ON(1);
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} else {
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int rect_order = 2;
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h = RECT_UNIT_H;
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while (num_pages / rect_order) {
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h *= 2;
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rect_order *= 4;
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if (h >= MAX_RECT_DIM) {
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h = MAX_RECT_DIM;
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break;
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}
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}
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max_pages = (MAX_RECT_DIM * h) / (RECT_UNIT_W * RECT_UNIT_H);
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if (pages > max_pages)
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pages = max_pages;
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w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h;
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w = (w / RECT_UNIT_W) * RECT_UNIT_W;
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pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H);
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BUG_ON(pages == 0);
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}
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DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h, w, pages);
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/* return width and height only of the caller wants it */
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if (height)
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*height = h;
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if (width)
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*width = w;
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return pages;
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}
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int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_pages)
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{
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int r;
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int ring_size, line_size;
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int max_size;
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int ring_size;
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/* loops of emits 64 + fence emit possible */
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int dwords_per_loop = 76, num_loops;
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int dwords_per_loop = 76, num_loops = 0;
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r = r600_vb_ib_get(rdev);
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if (r)
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@ -616,18 +666,12 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
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if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
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dwords_per_loop += 2;
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/* 8 bpp vs 32 bpp for xfer unit */
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if (size_bytes & 3)
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line_size = 8192;
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else
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line_size = 8192*4;
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/* num loops */
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while (num_pages) {
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num_pages -= r600_blit_create_rect(num_pages, NULL, NULL);
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num_loops++;
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}
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max_size = 8192 * line_size;
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/* major loops cover the max size transfer */
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num_loops = ((size_bytes + max_size) / max_size);
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/* minor loops cover the extra non aligned bits */
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num_loops += ((size_bytes % line_size) ? 1 : 0);
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/* calculate number of loops correctly */
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ring_size = num_loops * dwords_per_loop;
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/* set default + shaders */
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@ -659,182 +703,72 @@ void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
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void r600_kms_blit_copy(struct radeon_device *rdev,
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u64 src_gpu_addr, u64 dst_gpu_addr,
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int size_bytes)
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unsigned num_pages)
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{
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int max_bytes;
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u64 vb_gpu_addr;
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u32 *vb;
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DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
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size_bytes, rdev->r600_blit.vb_used);
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num_pages, rdev->r600_blit.vb_used);
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vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
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if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
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max_bytes = 8192;
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while (size_bytes) {
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int cur_size = size_bytes;
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int src_x = src_gpu_addr & 255;
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int dst_x = dst_gpu_addr & 255;
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int h = 1;
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src_gpu_addr = src_gpu_addr & ~255ULL;
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dst_gpu_addr = dst_gpu_addr & ~255ULL;
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while (num_pages) {
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int w, h;
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unsigned size_in_bytes;
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unsigned pages_per_loop = r600_blit_create_rect(num_pages, &w, &h);
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if (!src_x && !dst_x) {
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h = (cur_size / max_bytes);
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if (h > 8192)
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h = 8192;
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if (h == 0)
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h = 1;
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else
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cur_size = max_bytes;
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} else {
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if (cur_size > max_bytes)
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cur_size = max_bytes;
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if (cur_size > (max_bytes - dst_x))
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cur_size = (max_bytes - dst_x);
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if (cur_size > (max_bytes - src_x))
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cur_size = (max_bytes - src_x);
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}
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size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE;
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DRM_DEBUG("rectangle w=%d h=%d\n", w, h);
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if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
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WARN_ON(1);
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}
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vb[0] = i2f(dst_x);
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vb[1] = 0;
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vb[2] = i2f(src_x);
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vb[3] = 0;
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vb[4] = i2f(dst_x);
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vb[5] = i2f(h);
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vb[6] = i2f(src_x);
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vb[7] = i2f(h);
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vb[8] = i2f(dst_x + cur_size);
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vb[9] = i2f(h);
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vb[10] = i2f(src_x + cur_size);
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vb[11] = i2f(h);
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/* src 9 */
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set_tex_resource(rdev, FMT_8,
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src_x + cur_size, h, src_x + cur_size,
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src_gpu_addr);
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/* 5 */
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cp_set_surface_sync(rdev,
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PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
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/* dst 23 */
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set_render_target(rdev, COLOR_8,
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dst_x + cur_size, h,
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dst_gpu_addr);
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/* scissors 12 */
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set_scissors(rdev, dst_x, 0, dst_x + cur_size, h);
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/* 14 */
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vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
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set_vtx_resource(rdev, vb_gpu_addr);
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/* draw 10 */
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draw_auto(rdev);
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/* 5 */
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cp_set_surface_sync(rdev,
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PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
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cur_size * h, dst_gpu_addr);
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vb += 12;
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rdev->r600_blit.vb_used += 12 * 4;
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src_gpu_addr += cur_size * h;
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dst_gpu_addr += cur_size * h;
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size_bytes -= cur_size * h;
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if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
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WARN_ON(1);
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}
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} else {
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max_bytes = 8192 * 4;
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while (size_bytes) {
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int cur_size = size_bytes;
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int src_x = (src_gpu_addr & 255);
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int dst_x = (dst_gpu_addr & 255);
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int h = 1;
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src_gpu_addr = src_gpu_addr & ~255ULL;
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dst_gpu_addr = dst_gpu_addr & ~255ULL;
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vb[0] = 0;
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vb[1] = 0;
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vb[2] = 0;
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vb[3] = 0;
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if (!src_x && !dst_x) {
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h = (cur_size / max_bytes);
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if (h > 8192)
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h = 8192;
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if (h == 0)
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h = 1;
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else
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cur_size = max_bytes;
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} else {
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if (cur_size > max_bytes)
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cur_size = max_bytes;
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if (cur_size > (max_bytes - dst_x))
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cur_size = (max_bytes - dst_x);
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if (cur_size > (max_bytes - src_x))
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cur_size = (max_bytes - src_x);
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}
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vb[4] = 0;
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vb[5] = i2f(h);
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vb[6] = 0;
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vb[7] = i2f(h);
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if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
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WARN_ON(1);
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}
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vb[8] = i2f(w);
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vb[9] = i2f(h);
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vb[10] = i2f(w);
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vb[11] = i2f(h);
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vb[0] = i2f(dst_x / 4);
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vb[1] = 0;
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vb[2] = i2f(src_x / 4);
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vb[3] = 0;
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/* src 9 */
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set_tex_resource(rdev, FMT_8_8_8_8, w, h, w, src_gpu_addr);
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vb[4] = i2f(dst_x / 4);
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vb[5] = i2f(h);
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vb[6] = i2f(src_x / 4);
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vb[7] = i2f(h);
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/* 5 */
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cp_set_surface_sync(rdev,
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PACKET3_TC_ACTION_ENA, size_in_bytes, src_gpu_addr);
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vb[8] = i2f((dst_x + cur_size) / 4);
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vb[9] = i2f(h);
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vb[10] = i2f((src_x + cur_size) / 4);
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vb[11] = i2f(h);
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/* dst 23 */
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set_render_target(rdev, COLOR_8_8_8_8, w, h, dst_gpu_addr);
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/* src 9 */
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set_tex_resource(rdev, FMT_8_8_8_8,
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(src_x + cur_size) / 4,
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h, (src_x + cur_size) / 4,
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src_gpu_addr);
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/* 5 */
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cp_set_surface_sync(rdev,
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PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
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/* scissors 12 */
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set_scissors(rdev, 0, 0, w, h);
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/* dst 23 */
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set_render_target(rdev, COLOR_8_8_8_8,
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(dst_x + cur_size) / 4, h,
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dst_gpu_addr);
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/* Vertex buffer setup 14 */
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vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
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set_vtx_resource(rdev, vb_gpu_addr);
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/* scissors 12 */
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set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
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/* draw 10 */
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draw_auto(rdev);
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/* Vertex buffer setup 14 */
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vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
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set_vtx_resource(rdev, vb_gpu_addr);
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/* 5 */
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cp_set_surface_sync(rdev,
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PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
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size_in_bytes, dst_gpu_addr);
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/* draw 10 */
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draw_auto(rdev);
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/* 5 */
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cp_set_surface_sync(rdev,
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PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
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cur_size * h, dst_gpu_addr);
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/* 78 ring dwords per loop */
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vb += 12;
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rdev->r600_blit.vb_used += 12 * 4;
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src_gpu_addr += cur_size * h;
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dst_gpu_addr += cur_size * h;
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size_bytes -= cur_size * h;
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}
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/* 78 ring dwords per loop */
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vb += 12;
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rdev->r600_blit.vb_used += 4*12;
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src_gpu_addr += size_in_bytes;
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dst_gpu_addr += size_in_bytes;
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num_pages -= pages_per_loop;
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}
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}
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@ -364,11 +364,11 @@ void r600_hdmi_init(struct drm_encoder *encoder);
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int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
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void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
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/* r600 blit */
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int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
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int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_pages);
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void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
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void r600_kms_blit_copy(struct radeon_device *rdev,
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u64 src_gpu_addr, u64 dst_gpu_addr,
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int size_bytes);
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unsigned num_pages);
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/*
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* rv770,rv730,rv710,rv740
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