ARM: S3C2416: Add S3C2416-specific registers definitions
Add macros for S3C2416 SoC support. Signed-off-by: Yauhen Kharuzhy <jekhor@gmail.com> [ben-linux@fluff.org: removed files that need changing] [ben-linux@fluff.org: Fix S3C2416_GPH0_TXD0 definition] Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Yauhen Kharuzhy
Ben Dooks
parent
4fcfce9f33
commit
7cfdee9f67
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@ -54,7 +54,7 @@ enum dma_ch {
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#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
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/* we have 4 dma channels */
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#ifndef CONFIG_CPU_S3C2443
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#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
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#define S3C_DMA_CHANNELS (4)
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#else
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#define S3C_DMA_CHANNELS (6)
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@ -115,6 +115,26 @@
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#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13)
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#define IRQ_S3C2412_CF S3C2410_IRQSUB(14)
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#define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5)
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#define IRQ_S3C2416_DMA S3C2410_IRQ(17)
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#define IRQ_S3C2416_UART3 S3C2410_IRQ(18)
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#define IRQ_S3C2416_SDI1 S3C2410_IRQ(20)
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#define IRQ_S3C2416_SDI0 S3C2410_IRQ(21)
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#define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15)
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#define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16)
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#define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17)
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#define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18)
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#define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19)
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#define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20)
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#define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21)
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#define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22)
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#define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23)
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#define IRQ_S32416_WDT S3C2410_IRQSUB(27)
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#define IRQ_S32416_AC97 S3C2410_IRQSUB(28)
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/* extra irqs for s3c2440 */
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#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */
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@ -152,7 +172,7 @@
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#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27)
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#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28)
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#ifdef CONFIG_CPU_S3C2443
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#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
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#define NR_IRQS (IRQ_S3C2443_AC97+1)
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#else
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#define NR_IRQS (IRQ_S3C2440_AC97+1)
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@ -19,6 +19,42 @@
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#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0)
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#endif
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#if defined(CONFIG_CPU_S3C2416)
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#define S3C2416_DSC0 S3C2410_GPIOREG(0xc0)
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#define S3C2416_DSC1 S3C2410_GPIOREG(0xc4)
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#define S3C2416_DSC2 S3C2410_GPIOREG(0xc8)
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#define S3C2416_DSC3 S3C2410_GPIOREG(0x110)
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#define S3C2416_SELECT_DSC0 (0 << 30)
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#define S3C2416_SELECT_DSC1 (1 << 30)
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#define S3C2416_SELECT_DSC2 (2 << 30)
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#define S3C2416_SELECT_DSC3 (3 << 30)
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#define S3C2416_DSC_GETSHIFT(x) (x & 30)
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#define S3C2416_DSC0_CF (S3C2416_SELECT_DSC0 | 28)
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#define S3C2416_DSC0_CF_5mA (0 << 28)
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#define S3C2416_DSC0_CF_10mA (1 << 28)
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#define S3C2416_DSC0_CF_15mA (2 << 28)
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#define S3C2416_DSC0_CF_21mA (3 << 28)
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#define S3C2416_DSC0_CF_MASK (3 << 28)
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#define S3C2416_DSC0_nRBE (S3C2416_SELECT_DSC0 | 26)
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#define S3C2416_DSC0_nRBE_5mA (0 << 26)
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#define S3C2416_DSC0_nRBE_10mA (1 << 26)
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#define S3C2416_DSC0_nRBE_15mA (2 << 26)
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#define S3C2416_DSC0_nRBE_21mA (3 << 26)
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#define S3C2416_DSC0_nRBE_MASK (3 << 26)
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#define S3C2416_DSC0_nROE (S3C2416_SELECT_DSC0 | 24)
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#define S3C2416_DSC0_nROE_5mA (0 << 24)
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#define S3C2416_DSC0_nROE_10mA (1 << 24)
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#define S3C2416_DSC0_nROE_15mA (2 << 24)
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#define S3C2416_DSC0_nROE_21mA (3 << 24)
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#define S3C2416_DSC0_nROE_MASK (3 << 24)
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#endif
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#if defined(CONFIG_CPU_S3C244X)
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#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4)
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@ -610,29 +610,50 @@
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#define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
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#define S3C2410_GPH0_nCTS0 (0x02 << 0)
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#define S3C2416_GPH0_TXD0 (0x02 << 0)
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#define S3C2410_GPH1_nRTS0 (0x02 << 2)
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#define S3C2416_GPH1_RXD0 (0x02 << 2)
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#define S3C2410_GPH2_TXD0 (0x02 << 4)
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#define S3C2416_GPH2_TXD1 (0x02 << 4)
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#define S3C2410_GPH3_RXD0 (0x02 << 6)
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#define S3C2416_GPH3_RXD1 (0x02 << 6)
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#define S3C2410_GPH4_TXD1 (0x02 << 8)
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#define S3C2416_GPH4_TXD2 (0x02 << 8)
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#define S3C2410_GPH5_RXD1 (0x02 << 10)
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#define S3C2416_GPH5_RXD2 (0x02 << 10)
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#define S3C2410_GPH6_TXD2 (0x02 << 12)
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#define S3C2416_GPH6_TXD3 (0x02 << 12)
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#define S3C2410_GPH6_nRTS1 (0x03 << 12)
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#define S3C2416_GPH6_nRTS2 (0x03 << 12)
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#define S3C2410_GPH7_RXD2 (0x02 << 14)
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#define S3C2416_GPH7_RXD3 (0x02 << 14)
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#define S3C2410_GPH7_nCTS1 (0x03 << 14)
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#define S3C2416_GPH7_nCTS2 (0x03 << 14)
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#define S3C2410_GPH8_UCLK (0x02 << 16)
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#define S3C2416_GPH8_nCTS0 (0x02 << 16)
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#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
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#define S3C2442_GPH9_nSPICS0 (0x03 << 18)
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#define S3C2416_GPH9_nRTS0 (0x02 << 18)
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#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
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#define S3C2416_GPH10_nCTS1 (0x02 << 20)
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#define S3C2416_GPH11_nRTS1 (0x02 << 22)
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#define S3C2416_GPH12_EXTUARTCLK (0x02 << 24)
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#define S3C2416_GPH13_CLKOUT0 (0x02 << 26)
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#define S3C2416_GPH14_CLKOUT1 (0x02 << 28)
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/* The S3C2412 and S3C2413 move the GPJ register set to after
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* GPH, which means all registers after 0x80 are now offset by 0x10
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@ -703,6 +724,7 @@
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#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8)
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#define S3C2410_MISCCR_USBSUSPND0 (1<<12)
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#define S3C2416_MISCCR_SEL_SUSPND (1<<12)
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#define S3C2410_MISCCR_USBSUSPND1 (1<<13)
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#define S3C2410_MISCCR_nRSTCON (1<<16)
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@ -712,6 +734,9 @@
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#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */
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#define S3C2410_MISCCR_SDSLEEP (7<<17)
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#define S3C2416_MISCCR_FLT_I2C (1<<24)
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#define S3C2416_MISCCR_HSSPI_EN2 (1<<31)
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/* external interrupt control... */
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/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
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* S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
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@ -779,8 +804,11 @@
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#define S3C2410_GSTATUS1_IDMASK (0xffff0000)
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#define S3C2410_GSTATUS1_2410 (0x32410000)
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#define S3C2410_GSTATUS1_2412 (0x32412001)
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#define S3C2410_GSTATUS1_2416 (0x32416003)
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#define S3C2410_GSTATUS1_2440 (0x32440000)
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#define S3C2410_GSTATUS1_2442 (0x32440aaa)
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/* some 2416 CPUs report this value also */
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#define S3C2410_GSTATUS1_2450 (0x32450003)
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#define S3C2410_GSTATUS2_WTRESET (1<<2)
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#define S3C2410_GSTATUS2_OFFRESET (1<<1)
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@ -27,6 +27,16 @@
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#define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018)
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#define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C)
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#define S3C2416_PRIORITY_MODE1 S3C2410_IRQREG(0x030)
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#define S3C2416_PRIORITY_UPDATE1 S3C2410_IRQREG(0x034)
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#define S3C2416_SRCPND2 S3C2410_IRQREG(0x040)
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#define S3C2416_INTMOD2 S3C2410_IRQREG(0x044)
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#define S3C2416_INTMSK2 S3C2410_IRQREG(0x048)
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#define S3C2416_INTPND2 S3C2410_IRQREG(0x050)
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#define S3C2416_INTOFFSET2 S3C2410_IRQREG(0x054)
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#define S3C2416_PRIORITY_MODE2 S3C2410_IRQREG(0x070)
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#define S3C2416_PRIORITY_UPDATE2 S3C2410_IRQREG(0x074)
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/* mask: 0=enable, 1=disable
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* 1 bit EINT, 4=EINT4, 23=EINT23
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* EINT0,1,2,3 are not handled here.
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@ -0,0 +1,30 @@
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/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
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*
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* Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
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* as part of OpenInkpot project
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* Copyright (c) 2009 Promwad Innovation Company
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* Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C2416 memory register definitions
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*/
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#ifndef __ASM_ARM_REGS_S3C2416_MEM
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#define __ASM_ARM_REGS_S3C2416_MEM
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#ifndef S3C2416_MEMREG
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#define S3C2416_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
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#endif
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#define S3C2416_BANKCFG S3C2416_MEMREG(0x00)
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#define S3C2416_BANKCON1 S3C2416_MEMREG(0x04)
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#define S3C2416_BANKCON2 S3C2416_MEMREG(0x08)
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#define S3C2416_BANKCON3 S3C2416_MEMREG(0x0C)
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#define S3C2416_REFRESH S3C2416_MEMREG(0x10)
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#define S3C2416_TIMEOUT S3C2416_MEMREG(0x14)
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#endif /* __ASM_ARM_REGS_S3C2416_MEM */
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@ -0,0 +1,24 @@
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/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
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*
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* Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
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* as part of OpenInkpot project
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* Copyright (c) 2009 Promwad Innovation Company
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* Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C2416 specific register definitions
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*/
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#ifndef __ASM_ARCH_REGS_S3C2416_H
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#define __ASM_ARCH_REGS_S3C2416_H "s3c2416"
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#define S3C2416_SWRST (S3C24XX_VA_CLKPWR + 0x44)
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#define S3C2416_SWRST_RESET (0x533C2416)
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/* see regs-power.h for the other registers in the power block. */
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#endif /* __ASM_ARCH_REGS_S3C2416_H */
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