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Merge branch 'for-tony' of git://gitorious.org/linux-omap-dss2/linux into omap-for-linus 

Conflicts:
	arch/arm/mach-omap2/board-3430sdp.c
This commit is contained in:
Tony Lindgren 2011-02-23 12:06:28 -08:00
parent c3bbcf5dc3 d5e13227c3
commit 7cab8713b1
21 changed files with 1185 additions and 146 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/mach-omap2/Makefile
View File

@ -245,3 +245,6 @@ obj-y += $(smc91x-m) $(smc91x-y)
smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o
obj-y += $(smsc911x-m) $(smsc911x-y)
obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o
disp-$(CONFIG_OMAP2_DSS) := display.o
obj-y += $(disp-m) $(disp-y)

15
arch/arm/mach-omap2/board-3430sdp.c
View File

@ -307,17 +307,8 @@ static struct omap_dss_board_info sdp3430_dss_data = {
.default_device = &sdp3430_lcd_device,
};
static struct platform_device sdp3430_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &sdp3430_dss_data,
},
};
static struct platform_device *sdp3430_devices[] __initdata = {
&sdp3430_dss_device,
};
static struct regulator_consumer_supply sdp3430_vdda_dac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss");
static struct omap_board_config_kernel sdp3430_config[] __initdata = {
};
@ -798,7 +789,7 @@ static void __init omap_3430sdp_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap3430_i2c_init();
platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices));
omap_display_init(&sdp3430_dss_data);
if (omap_rev() > OMAP3430_REV_ES1_0)
ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2;
else

16
arch/arm/mach-omap2/board-am3517evm.c
View File

@ -378,24 +378,12 @@ static struct omap_dss_board_info am3517_evm_dss_data = {
.default_device = &am3517_evm_lcd_device,
};
static struct platform_device am3517_evm_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &am3517_evm_dss_data,
},
};
/*
* Board initialization
*/
static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
};
static struct platform_device *am3517_evm_devices[] __initdata = {
&am3517_evm_dss_device,
};
static void __init am3517_evm_init_early(void)
{
omap_board_config = am3517_evm_config;
@ -498,9 +486,7 @@ static void __init am3517_evm_init(void)
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
am3517_evm_i2c_init();
platform_add_devices(am3517_evm_devices,
ARRAY_SIZE(am3517_evm_devices));
omap_display_init(&am3517_evm_dss_data);
omap_serial_init();
/* Configure GPIO for EHCI port */

22
arch/arm/mach-omap2/board-cm-t35.c
View File

@ -401,14 +401,6 @@ static struct omap_dss_board_info cm_t35_dss_data = {
.default_device = &cm_t35_dvi_device,
};
static struct platform_device cm_t35_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &cm_t35_dss_data,
},
};
static struct omap2_mcspi_device_config tdo24m_mcspi_config = {
.turbo_mode = 0,
.single_channel = 1, /* 0: slave, 1: master */
@ -468,7 +460,7 @@ static void __init cm_t35_init_display(void)
msleep(50);
gpio_set_value(lcd_en_gpio, 1);
err = platform_device_register(&cm_t35_dss_device);
err = omap_display_init(&cm_t35_dss_data);
if (err) {
pr_err("CM-T35: failed to register DSS device\n");
goto err_dev_reg;
@ -495,15 +487,11 @@ static struct regulator_consumer_supply cm_t35_vsim_supply = {
.supply = "vmmc_aux",
};
static struct regulator_consumer_supply cm_t35_vdac_supply = {
.supply = "vdda_dac",
.dev = &cm_t35_dss_device.dev,
};
static struct regulator_consumer_supply cm_t35_vdac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss");
static struct regulator_consumer_supply cm_t35_vdvi_supply = {
.supply = "vdvi",
.dev = &cm_t35_dss_device.dev,
};
static struct regulator_consumer_supply cm_t35_vdvi_supply =
REGULATOR_SUPPLY("vdvi", "omapdss");
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
static struct regulator_init_data cm_t35_vmmc1 = {

10
arch/arm/mach-omap2/board-devkit8000.c
View File

@ -195,14 +195,6 @@ static struct omap_dss_board_info devkit8000_dss_data = {
.default_device = &devkit8000_lcd_device,
};
static struct platform_device devkit8000_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &devkit8000_dss_data,
},
};
static struct regulator_consumer_supply devkit8000_vdda_dac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss");
@ -579,7 +571,6 @@ static void __init omap_dm9000_init(void)
}
static struct platform_device *devkit8000_devices[] __initdata = {
&devkit8000_dss_device,
&leds_gpio,
&keys_gpio,
&omap_dm9000_dev,
@ -801,6 +792,7 @@ static void __init devkit8000_init(void)
platform_add_devices(devkit8000_devices,
ARRAY_SIZE(devkit8000_devices));
omap_display_init(&devkit8000_dss_data);
spi_register_board_info(devkit8000_spi_board_info,
ARRAY_SIZE(devkit8000_spi_board_info));

16
arch/arm/mach-omap2/board-igep0020.c
View File

@ -485,18 +485,8 @@ static struct omap_dss_board_info igep2_dss_data = {
.default_device = &igep2_dvi_device,
};
static struct platform_device igep2_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &igep2_dss_data,
},
};
static struct regulator_consumer_supply igep2_vpll2_supply = {
.supply = "vdds_dsi",
.dev = &igep2_dss_device.dev,
};
static struct regulator_consumer_supply igep2_vpll2_supply =
REGULATOR_SUPPLY("vdds_dsi", "omapdss");
static struct regulator_init_data igep2_vpll2 = {
.constraints = {
@ -521,7 +511,6 @@ static void __init igep2_display_init(void)
}
static struct platform_device *igep2_devices[] __initdata = {
&igep2_dss_device,
&igep2_vwlan_device,
};
@ -696,6 +685,7 @@ static void __init igep2_init(void)
/* Register I2C busses and drivers */
igep2_i2c_init();
platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices));
omap_display_init(&igep2_dss_data);
omap_serial_init();
usb_musb_init(&musb_board_data);
usb_ehci_init(&ehci_pdata);

10
arch/arm/mach-omap2/board-omap3beagle.c
View File

@ -228,14 +228,6 @@ static struct omap_dss_board_info beagle_dss_data = {
.default_device = &beagle_dvi_device,
};
static struct platform_device beagle_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &beagle_dss_data,
},
};
static struct regulator_consumer_supply beagle_vdac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss");
@ -554,7 +546,6 @@ static void __init omap3_beagle_init_irq(void)
static struct platform_device *omap3_beagle_devices[] __initdata = {
&leds_gpio,
&keys_gpio,
&beagle_dss_device,
};
static void __init omap3beagle_flash_init(void)
@ -621,6 +612,7 @@ static void __init omap3_beagle_init(void)
omap3_beagle_i2c_init();
platform_add_devices(omap3_beagle_devices,
ARRAY_SIZE(omap3_beagle_devices));
omap_display_init(&beagle_dss_data);
omap_serial_init();
omap_mux_init_gpio(170, OMAP_PIN_INPUT);

20
arch/arm/mach-omap2/board-omap3evm.c
View File

@ -363,14 +363,6 @@ static struct omap_dss_board_info omap3_evm_dss_data = {
.default_device = &omap3_evm_lcd_device,
};
static struct platform_device omap3_evm_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &omap3_evm_dss_data,
},
};
static struct regulator_consumer_supply omap3evm_vmmc1_supply = {
.supply = "vmmc",
};
@ -551,10 +543,8 @@ static struct twl4030_codec_data omap3evm_codec_data = {
.audio = &omap3evm_audio_data,
};
static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = {
.supply = "vdda_dac",
.dev = &omap3_evm_dss_device.dev,
};
static struct regulator_consumer_supply omap3_evm_vdda_dac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss");
/* VDAC for DSS driving S-Video */
static struct regulator_init_data omap3_evm_vdac = {
@ -748,10 +738,6 @@ static void __init omap3_evm_init_early(void)
omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
}
static struct platform_device *omap3_evm_devices[] __initdata = {
&omap3_evm_dss_device,
};
static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
.port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
@ -840,7 +826,7 @@ static void __init omap3_evm_init(void)
omap3_evm_i2c_init();
platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices));
omap_display_init(&omap3_evm_dss_data);
spi_register_board_info(omap3evm_spi_board_info,
ARRAY_SIZE(omap3evm_spi_board_info));

10
arch/arm/mach-omap2/board-omap3pandora.c
View File

@ -253,14 +253,6 @@ static struct omap_dss_board_info pandora_dss_data = {
.default_device = &pandora_lcd_device,
};
static struct platform_device pandora_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &pandora_dss_data,
},
};
static void pandora_wl1251_init_card(struct mmc_card *card)
{
/*
@ -676,7 +668,6 @@ fail:
static struct platform_device *omap3pandora_devices[] __initdata = {
&pandora_leds_gpio,
&pandora_keys_gpio,
&pandora_dss_device,
&pandora_vwlan_device,
};
@ -711,6 +702,7 @@ static void __init omap3pandora_init(void)
pandora_wl1251_init();
platform_add_devices(omap3pandora_devices,
ARRAY_SIZE(omap3pandora_devices));
omap_display_init(&pandora_dss_data);
omap_serial_init();
spi_register_board_info(omap3pandora_spi_board_info,
ARRAY_SIZE(omap3pandora_spi_board_info));

22
arch/arm/mach-omap2/board-omap3stalker.c
View File

@ -240,14 +240,6 @@ static struct omap_dss_board_info omap3_stalker_dss_data = {
.default_device = &omap3_stalker_dvi_device,
};
static struct platform_device omap3_stalker_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &omap3_stalker_dss_data,
},
};
static struct regulator_consumer_supply omap3stalker_vmmc1_supply = {
.supply = "vmmc",
};
@ -448,10 +440,8 @@ static struct twl4030_codec_data omap3stalker_codec_data = {
.audio = &omap3stalker_audio_data,
};
static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = {
.supply = "vdda_dac",
.dev = &omap3_stalker_dss_device.dev,
};
static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss");
/* VDAC for DSS driving S-Video */
static struct regulator_init_data omap3_stalker_vdac = {
@ -469,10 +459,8 @@ static struct regulator_init_data omap3_stalker_vdac = {
};
/* VPLL2 for digital video outputs */
static struct regulator_consumer_supply omap3_stalker_vpll2_supply = {
.supply = "vdds_dsi",
.dev = &omap3_stalker_lcd_device.dev,
};
static struct regulator_consumer_supply omap3_stalker_vpll2_supply =
REGULATOR_SUPPLY("vdds_dsi", "omapdss");
static struct regulator_init_data omap3_stalker_vpll2 = {
.constraints = {
@ -608,7 +596,6 @@ static void __init omap3_stalker_init_irq(void)
}
static struct platform_device *omap3_stalker_devices[] __initdata = {
&omap3_stalker_dss_device,
&keys_gpio,
};
@ -648,6 +635,7 @@ static void __init omap3_stalker_init(void)
platform_add_devices(omap3_stalker_devices,
ARRAY_SIZE(omap3_stalker_devices));
omap_display_init(&omap3_stalker_dss_data);
spi_register_board_info(omap3stalker_spi_board_info,
ARRAY_SIZE(omap3stalker_spi_board_info));

15
arch/arm/mach-omap2/board-rx51-video.c
View File

@ -66,18 +66,6 @@ static struct omap_dss_board_info rx51_dss_board_info = {
.default_device = &rx51_lcd_device,
};
struct platform_device rx51_display_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &rx51_dss_board_info,
},
};
static struct platform_device *rx51_video_devices[] __initdata = {
&rx51_display_device,
};
static int __init rx51_video_init(void)
{
if (!machine_is_nokia_rx51())
@ -95,8 +83,7 @@ static int __init rx51_video_init(void)
gpio_direction_output(RX51_LCD_RESET_GPIO, 1);
platform_add_devices(rx51_video_devices,
ARRAY_SIZE(rx51_video_devices));
omap_display_init(&rx51_dss_board_info);
return 0;
}

15
arch/arm/mach-omap2/board-zoom-display.c
View File

@ -130,14 +130,6 @@ static struct omap_dss_board_info zoom_dss_data = {
.default_device = &zoom_lcd_device,
};
static struct platform_device zoom_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &zoom_dss_data,
},
};
static struct omap2_mcspi_device_config dss_lcd_mcspi_config = {
.turbo_mode = 1,
.single_channel = 1, /* 0: slave, 1: master */
@ -153,14 +145,9 @@ static struct spi_board_info nec_8048_spi_board_info[] __initdata = {
},
};
static struct platform_device *zoom_display_devices[] __initdata = {
&zoom_dss_device,
};
void __init zoom_display_init(void)
{
platform_add_devices(zoom_display_devices,
ARRAY_SIZE(zoom_display_devices));
omap_display_init(&zoom_dss_data);
spi_register_board_info(nec_8048_spi_board_info,
ARRAY_SIZE(nec_8048_spi_board_info));
zoom_lcd_panel_init();

45
arch/arm/mach-omap2/display.c Normal file
View File

@ -0,0 +1,45 @@
/*
* OMAP2plus display device setup / initialization.
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
* Senthilvadivu Guruswamy
* Sumit Semwal
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <plat/display.h>
static struct platform_device omap_display_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = NULL,
},
};
int __init omap_display_init(struct omap_dss_board_info *board_data)
{
int r = 0;
omap_display_device.dev.platform_data = board_data;
r = platform_device_register(&omap_display_device);
if (r < 0)
printk(KERN_ERR "Unable to register OMAP-Display device\n");
return r;
}

310
arch/arm/mach-omap2/omap_hwmod_2420_data.c
View File

@ -19,6 +19,8 @@
#include <plat/i2c.h>
#include <plat/gpio.h>
#include <plat/mcspi.h>
#include <plat/l3_2xxx.h>
#include <plat/l4_2xxx.h>
#include "omap_hwmod_common_data.h"
@ -39,6 +41,10 @@ static struct omap_hwmod omap2420_mpu_hwmod;
static struct omap_hwmod omap2420_iva_hwmod;
static struct omap_hwmod omap2420_l3_main_hwmod;
static struct omap_hwmod omap2420_l4_core_hwmod;
static struct omap_hwmod omap2420_dss_core_hwmod;
static struct omap_hwmod omap2420_dss_dispc_hwmod;
static struct omap_hwmod omap2420_dss_rfbi_hwmod;
static struct omap_hwmod omap2420_dss_venc_hwmod;
static struct omap_hwmod omap2420_wd_timer2_hwmod;
static struct omap_hwmod omap2420_gpio1_hwmod;
static struct omap_hwmod omap2420_gpio2_hwmod;
@ -67,6 +73,19 @@ static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
&omap2420_mpu__l3_main,
};
/* DSS -> l3 */
static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
.master = &omap2420_dss_core_hwmod,
.slave = &omap2420_l3_main_hwmod,
.fw = {
.omap2 = {
.l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
.flags = OMAP_FIREWALL_L3,
}
},
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* Master interfaces on the L3 interconnect */
static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
&omap2420_l3_main__l4_core,
@ -509,6 +528,291 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/*
* 'dss' class
* display sub-system
*/
static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2420_dss_hwmod_class = {
.name = "dss",
.sysc = &omap2420_dss_sysc,
};
/* dss */
static struct omap_hwmod_irq_info omap2420_dss_irqs[] = {
{ .irq = 25 },
};
static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = {
{ .name = "dispc", .dma_req = 5 },
};
/* dss */
/* dss master ports */
static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
&omap2420_dss__l3,
};
static struct omap_hwmod_addr_space omap2420_dss_addrs[] = {
{
.pa_start = 0x48050000,
.pa_end = 0x480503FF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss */
static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_dss_core_hwmod,
.clk = "dss_ick",
.addr = omap2420_dss_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_dss_addrs),
.fw = {
.omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
.flags = OMAP_FIREWALL_L4,
}
},
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dss slave ports */
static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
&omap2420_l4_core__dss,
};
static struct omap_hwmod_opt_clk dss_opt_clks[] = {
{ .role = "tv_clk", .clk = "dss_54m_fck" },
{ .role = "sys_clk", .clk = "dss2_fck" },
};
static struct omap_hwmod omap2420_dss_core_hwmod = {
.name = "dss_core",
.class = &omap2420_dss_hwmod_class,
.main_clk = "dss1_fck", /* instead of dss_fck */
.mpu_irqs = omap2420_dss_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_dss_irqs),
.sdma_reqs = omap2420_dss_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs),
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
.module_bit = OMAP24XX_EN_DSS1_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
},
},
.opt_clks = dss_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
.slaves = omap2420_dss_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves),
.masters = omap2420_dss_masters,
.masters_cnt = ARRAY_SIZE(omap2420_dss_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
.flags = HWMOD_NO_IDLEST,
};
/*
* 'dispc' class
* display controller
*/
static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
.name = "dispc",
.sysc = &omap2420_dispc_sysc,
};
static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = {
{
.pa_start = 0x48050400,
.pa_end = 0x480507FF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_dispc */
static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_dss_dispc_hwmod,
.clk = "dss_ick",
.addr = omap2420_dss_dispc_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_dss_dispc_addrs),
.fw = {
.omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
.flags = OMAP_FIREWALL_L4,
}
},
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dss_dispc slave ports */
static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
&omap2420_l4_core__dss_dispc,
};
static struct omap_hwmod omap2420_dss_dispc_hwmod = {
.name = "dss_dispc",
.class = &omap2420_dispc_hwmod_class,
.main_clk = "dss1_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
.module_bit = OMAP24XX_EN_DSS1_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
},
},
.slaves = omap2420_dss_dispc_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
.flags = HWMOD_NO_IDLEST,
};
/*
* 'rfbi' class
* remote frame buffer interface
*/
static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
.name = "rfbi",
.sysc = &omap2420_rfbi_sysc,
};
static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = {
{
.pa_start = 0x48050800,
.pa_end = 0x48050BFF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_rfbi */
static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_dss_rfbi_hwmod,
.clk = "dss_ick",
.addr = omap2420_dss_rfbi_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_dss_rfbi_addrs),
.fw = {
.omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
.flags = OMAP_FIREWALL_L4,
}
},
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dss_rfbi slave ports */
static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
&omap2420_l4_core__dss_rfbi,
};
static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
.name = "dss_rfbi",
.class = &omap2420_rfbi_hwmod_class,
.main_clk = "dss1_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
.module_bit = OMAP24XX_EN_DSS1_SHIFT,
.module_offs = CORE_MOD,
},
},
.slaves = omap2420_dss_rfbi_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
.flags = HWMOD_NO_IDLEST,
};
/*
* 'venc' class
* video encoder
*/
static struct omap_hwmod_class omap2420_venc_hwmod_class = {
.name = "venc",
};
/* dss_venc */
static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = {
{
.pa_start = 0x48050C00,
.pa_end = 0x48050FFF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_venc */
static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_dss_venc_hwmod,
.clk = "dss_54m_fck",
.addr = omap2420_dss_venc_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_dss_venc_addrs),
.fw = {
.omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
.flags = OMAP_FIREWALL_L4,
}
},
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dss_venc slave ports */
static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
&omap2420_l4_core__dss_venc,
};
static struct omap_hwmod omap2420_dss_venc_hwmod = {
.name = "dss_venc",
.class = &omap2420_venc_hwmod_class,
.main_clk = "dss1_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
.module_bit = OMAP24XX_EN_DSS1_SHIFT,
.module_offs = CORE_MOD,
},
},
.slaves = omap2420_dss_venc_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
.flags = HWMOD_NO_IDLEST,
};
/* I2C common */
static struct omap_hwmod_class_sysconfig i2c_sysc = {
.rev_offs = 0x00,
@ -1026,6 +1330,12 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
&omap2420_uart1_hwmod,
&omap2420_uart2_hwmod,
&omap2420_uart3_hwmod,
/* dss class */
&omap2420_dss_core_hwmod,
&omap2420_dss_dispc_hwmod,
&omap2420_dss_rfbi_hwmod,
&omap2420_dss_venc_hwmod,
/* i2c class */
&omap2420_i2c1_hwmod,
&omap2420_i2c2_hwmod,

284
arch/arm/mach-omap2/omap_hwmod_2430_data.c
View File

@ -19,6 +19,7 @@
#include <plat/i2c.h>
#include <plat/gpio.h>
#include <plat/mcspi.h>
#include <plat/l3_2xxx.h>
#include "omap_hwmod_common_data.h"
@ -39,6 +40,10 @@ static struct omap_hwmod omap2430_mpu_hwmod;
static struct omap_hwmod omap2430_iva_hwmod;
static struct omap_hwmod omap2430_l3_main_hwmod;
static struct omap_hwmod omap2430_l4_core_hwmod;
static struct omap_hwmod omap2430_dss_core_hwmod;
static struct omap_hwmod omap2430_dss_dispc_hwmod;
static struct omap_hwmod omap2430_dss_rfbi_hwmod;
static struct omap_hwmod omap2430_dss_venc_hwmod;
static struct omap_hwmod omap2430_wd_timer2_hwmod;
static struct omap_hwmod omap2430_gpio1_hwmod;
static struct omap_hwmod omap2430_gpio2_hwmod;
@ -69,6 +74,19 @@ static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
&omap2430_mpu__l3_main,
};
/* DSS -> l3 */
static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
.master = &omap2430_dss_core_hwmod,
.slave = &omap2430_l3_main_hwmod,
.fw = {
.omap2 = {
.l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
.flags = OMAP_FIREWALL_L3,
}
},
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* Master interfaces on the L3 interconnect */
static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
&omap2430_l3_main__l4_core,
@ -566,6 +584,266 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/*
* 'dss' class
* display sub-system
*/
static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2430_dss_hwmod_class = {
.name = "dss",
.sysc = &omap2430_dss_sysc,
};
/* dss */
static struct omap_hwmod_irq_info omap2430_dss_irqs[] = {
{ .irq = 25 },
};
static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
{ .name = "dispc", .dma_req = 5 },
};
/* dss */
/* dss master ports */
static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
&omap2430_dss__l3,
};
static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
{
.pa_start = 0x48050000,
.pa_end = 0x480503FF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss */
static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_dss_core_hwmod,
.clk = "dss_ick",
.addr = omap2430_dss_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_dss_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dss slave ports */
static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
&omap2430_l4_core__dss,
};
static struct omap_hwmod_opt_clk dss_opt_clks[] = {
{ .role = "tv_clk", .clk = "dss_54m_fck" },
{ .role = "sys_clk", .clk = "dss2_fck" },
};
static struct omap_hwmod omap2430_dss_core_hwmod = {
.name = "dss_core",
.class = &omap2430_dss_hwmod_class,
.main_clk = "dss1_fck", /* instead of dss_fck */
.mpu_irqs = omap2430_dss_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_dss_irqs),
.sdma_reqs = omap2430_dss_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_dss_sdma_chs),
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
.module_bit = OMAP24XX_EN_DSS1_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
},
},
.opt_clks = dss_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
.slaves = omap2430_dss_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves),
.masters = omap2430_dss_masters,
.masters_cnt = ARRAY_SIZE(omap2430_dss_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.flags = HWMOD_NO_IDLEST,
};
/*
* 'dispc' class
* display controller
*/
static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
.name = "dispc",
.sysc = &omap2430_dispc_sysc,
};
static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
{
.pa_start = 0x48050400,
.pa_end = 0x480507FF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_dispc */
static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_dss_dispc_hwmod,
.clk = "dss_ick",
.addr = omap2430_dss_dispc_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_dss_dispc_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dss_dispc slave ports */
static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
&omap2430_l4_core__dss_dispc,
};
static struct omap_hwmod omap2430_dss_dispc_hwmod = {
.name = "dss_dispc",
.class = &omap2430_dispc_hwmod_class,
.main_clk = "dss1_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
.module_bit = OMAP24XX_EN_DSS1_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
},
},
.slaves = omap2430_dss_dispc_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.flags = HWMOD_NO_IDLEST,
};
/*
* 'rfbi' class
* remote frame buffer interface
*/
static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
.name = "rfbi",
.sysc = &omap2430_rfbi_sysc,
};
static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
{
.pa_start = 0x48050800,
.pa_end = 0x48050BFF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_rfbi */
static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_dss_rfbi_hwmod,
.clk = "dss_ick",
.addr = omap2430_dss_rfbi_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_dss_rfbi_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dss_rfbi slave ports */
static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
&omap2430_l4_core__dss_rfbi,
};
static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
.name = "dss_rfbi",
.class = &omap2430_rfbi_hwmod_class,
.main_clk = "dss1_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
.module_bit = OMAP24XX_EN_DSS1_SHIFT,
.module_offs = CORE_MOD,
},
},
.slaves = omap2430_dss_rfbi_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.flags = HWMOD_NO_IDLEST,
};
/*
* 'venc' class
* video encoder
*/
static struct omap_hwmod_class omap2430_venc_hwmod_class = {
.name = "venc",
};
/* dss_venc */
static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
{
.pa_start = 0x48050C00,
.pa_end = 0x48050FFF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_venc */
static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_dss_venc_hwmod,
.clk = "dss_54m_fck",
.addr = omap2430_dss_venc_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dss_venc slave ports */
static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
&omap2430_l4_core__dss_venc,
};
static struct omap_hwmod omap2430_dss_venc_hwmod = {
.name = "dss_venc",
.class = &omap2430_venc_hwmod_class,
.main_clk = "dss1_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
.module_bit = OMAP24XX_EN_DSS1_SHIFT,
.module_offs = CORE_MOD,
},
},
.slaves = omap2430_dss_venc_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.flags = HWMOD_NO_IDLEST,
};
/* I2C common */
static struct omap_hwmod_class_sysconfig i2c_sysc = {
.rev_offs = 0x00,
@ -1240,6 +1518,12 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
&omap2430_uart1_hwmod,
&omap2430_uart2_hwmod,
&omap2430_uart3_hwmod,
/* dss class */
&omap2430_dss_core_hwmod,
&omap2430_dss_dispc_hwmod,
&omap2430_dss_rfbi_hwmod,
&omap2430_dss_venc_hwmod,
/* i2c class */
&omap2430_i2c1_hwmod,
&omap2430_i2c2_hwmod,

433
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View File

@ -18,6 +18,7 @@
#include <plat/cpu.h>
#include <plat/dma.h>
#include <plat/serial.h>
#include <plat/l3_3xxx.h>
#include <plat/l4_3xxx.h>
#include <plat/i2c.h>
#include <plat/gpio.h>
@ -46,6 +47,12 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod;
static struct omap_hwmod omap3xxx_l4_core_hwmod;
static struct omap_hwmod omap3xxx_l4_per_hwmod;
static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
static struct omap_hwmod omap3430es1_dss_core_hwmod;
static struct omap_hwmod omap3xxx_dss_core_hwmod;
static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
static struct omap_hwmod omap3xxx_dss_venc_hwmod;
static struct omap_hwmod omap3xxx_i2c1_hwmod;
static struct omap_hwmod omap3xxx_i2c2_hwmod;
static struct omap_hwmod omap3xxx_i2c3_hwmod;
@ -91,6 +98,19 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
&omap3xxx_mpu__l3_main,
};
/* DSS -> l3 */
static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
.master = &omap3xxx_dss_core_hwmod,
.slave = &omap3xxx_l3_main_hwmod,
.fw = {
.omap2 = {
.l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
.flags = OMAP_FIREWALL_L3,
}
},
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* Master interfaces on the L3 interconnect */
static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
&omap3xxx_l3_main__l4_core,
@ -742,6 +762,410 @@ static struct omap_hwmod_class i2c_class = {
.sysc = &i2c_sysc,
};
/*
* 'dss' class
* display sub-system
*/
static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
.name = "dss",
.sysc = &omap3xxx_dss_sysc,
};
/* dss */
static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = {
{ .irq = 25 },
};
static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
{ .name = "dispc", .dma_req = 5 },
{ .name = "dsi1", .dma_req = 74 },
};
/* dss */
/* dss master ports */
static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
&omap3xxx_dss__l3,
};
static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
{
.pa_start = 0x48050000,
.pa_end = 0x480503FF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss */
static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3430es1_dss_core_hwmod,
.clk = "dss_ick",
.addr = omap3xxx_dss_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
.fw = {
.omap2 = {
.l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
.flags = OMAP_FIREWALL_L4,
}
},
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_core_hwmod,
.clk = "dss_ick",
.addr = omap3xxx_dss_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
.fw = {
.omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
.flags = OMAP_FIREWALL_L4,
}
},
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dss slave ports */
static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
&omap3430es1_l4_core__dss,
};
static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
&omap3xxx_l4_core__dss,
};
static struct omap_hwmod_opt_clk dss_opt_clks[] = {
{ .role = "tv_clk", .clk = "dss_tv_fck" },
{ .role = "dssclk", .clk = "dss_96m_fck" },
{ .role = "sys_clk", .clk = "dss2_alwon_fck" },
};
static struct omap_hwmod omap3430es1_dss_core_hwmod = {
.name = "dss_core",
.class = &omap3xxx_dss_hwmod_class,
.main_clk = "dss1_alwon_fck", /* instead of dss_fck */
.mpu_irqs = omap3xxx_dss_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs),
.sdma_reqs = omap3xxx_dss_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
.module_bit = OMAP3430_EN_DSS1_SHIFT,
.module_offs = OMAP3430_DSS_MOD,
.idlest_reg_id = 1,
.idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
},
},
.opt_clks = dss_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
.slaves = omap3430es1_dss_slaves,
.slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
.masters = omap3xxx_dss_masters,
.masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
.flags = HWMOD_NO_IDLEST,
};
static struct omap_hwmod omap3xxx_dss_core_hwmod = {
.name = "dss_core",
.class = &omap3xxx_dss_hwmod_class,
.main_clk = "dss1_alwon_fck", /* instead of dss_fck */
.mpu_irqs = omap3xxx_dss_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs),
.sdma_reqs = omap3xxx_dss_sdma_chs,
.sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
.module_bit = OMAP3430_EN_DSS1_SHIFT,
.module_offs = OMAP3430_DSS_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
.idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
},
},
.opt_clks = dss_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
.slaves = omap3xxx_dss_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
.masters = omap3xxx_dss_masters,
.masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
};
/*
* 'dispc' class
* display controller
*/
static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
.name = "dispc",
.sysc = &omap3xxx_dispc_sysc,
};
static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
{
.pa_start = 0x48050400,
.pa_end = 0x480507FF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_dispc */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_dispc_hwmod,
.clk = "dss_ick",
.addr = omap3xxx_dss_dispc_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
.fw = {
.omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
.flags = OMAP_FIREWALL_L4,
}
},
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dss_dispc slave ports */
static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
&omap3xxx_l4_core__dss_dispc,
};
static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
.name = "dss_dispc",
.class = &omap3xxx_dispc_hwmod_class,
.main_clk = "dss1_alwon_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
.module_bit = OMAP3430_EN_DSS1_SHIFT,
.module_offs = OMAP3430_DSS_MOD,
},
},
.slaves = omap3xxx_dss_dispc_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
CHIP_GE_OMAP3630ES1_1),
.flags = HWMOD_NO_IDLEST,
};
/*
* 'dsi' class
* display serial interface controller
*/
static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
.name = "dsi",
};
/* dss_dsi1 */
static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
{
.pa_start = 0x4804FC00,
.pa_end = 0x4804FFFF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_dsi1 */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_dsi1_hwmod,
.addr = omap3xxx_dss_dsi1_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
.fw = {
.omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
.flags = OMAP_FIREWALL_L4,
}
},
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dss_dsi1 slave ports */
static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
&omap3xxx_l4_core__dss_dsi1,
};
static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
.name = "dss_dsi1",
.class = &omap3xxx_dsi_hwmod_class,
.main_clk = "dss1_alwon_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
.module_bit = OMAP3430_EN_DSS1_SHIFT,
.module_offs = OMAP3430_DSS_MOD,
},
},
.slaves = omap3xxx_dss_dsi1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
CHIP_GE_OMAP3630ES1_1),
.flags = HWMOD_NO_IDLEST,
};
/*
* 'rfbi' class
* remote frame buffer interface
*/
static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
.name = "rfbi",
.sysc = &omap3xxx_rfbi_sysc,
};
static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
{
.pa_start = 0x48050800,
.pa_end = 0x48050BFF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_rfbi */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_rfbi_hwmod,
.clk = "dss_ick",
.addr = omap3xxx_dss_rfbi_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
.fw = {
.omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
.flags = OMAP_FIREWALL_L4,
}
},
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dss_rfbi slave ports */
static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
&omap3xxx_l4_core__dss_rfbi,
};
static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
.name = "dss_rfbi",
.class = &omap3xxx_rfbi_hwmod_class,
.main_clk = "dss1_alwon_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
.module_bit = OMAP3430_EN_DSS1_SHIFT,
.module_offs = OMAP3430_DSS_MOD,
},
},
.slaves = omap3xxx_dss_rfbi_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
CHIP_GE_OMAP3630ES1_1),
.flags = HWMOD_NO_IDLEST,
};
/*
* 'venc' class
* video encoder
*/
static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
.name = "venc",
};
/* dss_venc */
static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
{
.pa_start = 0x48050C00,
.pa_end = 0x48050FFF,
.flags = ADDR_TYPE_RT
},
};
/* l4_core -> dss_venc */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_venc_hwmod,
.clk = "dss_tv_fck",
.addr = omap3xxx_dss_venc_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
.fw = {
.omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
.flags = OMAP_FIREWALL_L4,
}
},
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dss_venc slave ports */
static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
&omap3xxx_l4_core__dss_venc,
};
static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
.name = "dss_venc",
.class = &omap3xxx_venc_hwmod_class,
.main_clk = "dss1_alwon_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
.module_bit = OMAP3430_EN_DSS1_SHIFT,
.module_offs = OMAP3430_DSS_MOD,
},
},
.slaves = omap3xxx_dss_venc_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
CHIP_GE_OMAP3630ES1_1),
.flags = HWMOD_NO_IDLEST,
};
/* I2C1 */
static struct omap_i2c_dev_attr i2c1_dev_attr = {
@ -1800,6 +2224,15 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
&omap3xxx_uart2_hwmod,
&omap3xxx_uart3_hwmod,
&omap3xxx_uart4_hwmod,
/* dss class */
&omap3430es1_dss_core_hwmod,
&omap3xxx_dss_core_hwmod,
&omap3xxx_dss_dispc_hwmod,
&omap3xxx_dss_dsi1_hwmod,
&omap3xxx_dss_rfbi_hwmod,
&omap3xxx_dss_venc_hwmod,
/* i2c class */
&omap3xxx_i2c1_hwmod,
&omap3xxx_i2c2_hwmod,
&omap3xxx_i2c3_hwmod,

11
arch/arm/plat-omap/include/plat/display.h
View File

@ -23,6 +23,7 @@
#include <linux/list.h>
#include <linux/kobject.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <asm/atomic.h>
#define DISPC_IRQ_FRAMEDONE (1 << 0)
@ -226,6 +227,16 @@ struct omap_dss_board_info {
struct omap_dss_device *default_device;
};
#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
/* Init with the board info */
extern int omap_display_init(struct omap_dss_board_info *board_data);
#else
static inline int omap_display_init(struct omap_dss_board_info *board_data)
{
return 0;
}
#endif
struct omap_video_timings {
/* Unit: pixels */
u16 x_res;

20
arch/arm/plat-omap/include/plat/l3_2xxx.h Normal file
View File

@ -0,0 +1,20 @@
/*
* arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
* Sumit Semwal
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
/* L3 CONNIDs */
/* Display Sub system (DSS) */
#define OMAP2_L3_CORE_FW_CONNID_DSS 8
#endif

20
arch/arm/plat-omap/include/plat/l3_3xxx.h Normal file
View File

@ -0,0 +1,20 @@
/*
* arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
* Sumit Semwal
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
/* L3 Initiator IDs */
/* Display Sub system (DSS) */
#define OMAP3_L3_CORE_FW_INIT_ID_DSS 29
#endif

24
arch/arm/plat-omap/include/plat/l4_2xxx.h Normal file
View File

@ -0,0 +1,24 @@
/*
* arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
* Sumit Semwal
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
/* L4 CORE */
/* Display Sub system (DSS) */
#define OMAP2420_L4_CORE_FW_DSS_CORE_REGION 28
#define OMAP2420_L4_CORE_FW_DSS_DISPC_REGION 29
#define OMAP2420_L4_CORE_FW_DSS_RFBI_REGION 30
#define OMAP2420_L4_CORE_FW_DSS_VENC_REGION 31
#define OMAP2420_L4_CORE_FW_DSS_TA_REGION 32
#endif

10
arch/arm/plat-omap/include/plat/l4_3xxx.h
View File

@ -21,4 +21,14 @@
#define OMAP3_L4_CORE_FW_I2C3_REGION 73
#define OMAP3_L4_CORE_FW_I2C3_TA_REGION 74
/* Display Sub system (DSS) */
#define OMAP3_L4_CORE_FW_DSS_PROT_GROUP 2
#define OMAP3_L4_CORE_FW_DSS_DSI_REGION 104
#define OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION 3
#define OMAP3_L4_CORE_FW_DSS_CORE_REGION 4
#define OMAP3_L4_CORE_FW_DSS_DISPC_REGION 4
#define OMAP3_L4_CORE_FW_DSS_RFBI_REGION 5
#define OMAP3_L4_CORE_FW_DSS_VENC_REGION 6
#define OMAP3_L4_CORE_FW_DSS_TA_REGION 7
#endif