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treewide: transciever/transceiver spelling fixes 

Just tyops.

Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
This commit is contained in:
Joe Perches 2011-06-23 11:39:20 -07:00 committed by Jiri Kosina
parent dbc6221be7
commit 7c9d440e90
12 changed files with 15 additions and 15 deletions
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2
arch/arm/mach-pxa/include/mach/corgi.h
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@ -34,7 +34,7 @@
#define CORGI_GPIO_LCDCON_CS (19) /* LCD Control Chip Select */ #define CORGI_GPIO_LCDCON_CS (19) /* LCD Control Chip Select */
#define CORGI_GPIO_MAX1111_CS (20) /* MAX1111 Chip Select */ #define CORGI_GPIO_MAX1111_CS (20) /* MAX1111 Chip Select */
#define CORGI_GPIO_ADC_TEMP_ON (21) /* Select battery voltage or temperature */ #define CORGI_GPIO_ADC_TEMP_ON (21) /* Select battery voltage or temperature */
#define CORGI_GPIO_IR_ON (22) /* Enable IR Transciever */ #define CORGI_GPIO_IR_ON (22) /* Enable IR Transceiver */
#define CORGI_GPIO_ADS7846_CS (24) /* ADS7846 Chip Select */ #define CORGI_GPIO_ADS7846_CS (24) /* ADS7846 Chip Select */
#define CORGI_GPIO_SD_PWR (33) /* MMC/SD Power */ #define CORGI_GPIO_SD_PWR (33) /* MMC/SD Power */
#define CORGI_GPIO_CHRG_ON (38) /* Enable battery Charging */ #define CORGI_GPIO_CHRG_ON (38) /* Enable battery Charging */

4
arch/arm/mach-pxa/include/mach/pxa27x-udc.h
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@ -56,9 +56,9 @@
#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ #define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt #define UDCOTGICR_IEXR (1 << 17) /* Extra Transceiver Interrupt
Rising Edge Interrupt Enable */ Rising Edge Interrupt Enable */
#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt #define UDCOTGICR_IEXF (1 << 16) /* Extra Transceiver Interrupt
Falling Edge Interrupt Enable */ Falling Edge Interrupt Enable */
#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge #define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
Interrupt Enable */ Interrupt Enable */

2
arch/arm/mach-ux500/board-mop500-regulators.c
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@ -77,7 +77,7 @@ static struct regulator_consumer_supply ab8500_vtvout_consumers[] = {
static struct regulator_consumer_supply ab8500_vintcore_consumers[] = { static struct regulator_consumer_supply ab8500_vintcore_consumers[] = {
/* SoC core supply, no device */ /* SoC core supply, no device */
REGULATOR_SUPPLY("v-intcore", NULL), REGULATOR_SUPPLY("v-intcore", NULL),
/* USB Transciever */ /* USB Transceiver */
REGULATOR_SUPPLY("vddulpivio18", "ab8500-usb.0"), REGULATOR_SUPPLY("vddulpivio18", "ab8500-usb.0"),
}; };

2
drivers/i2c/busses/i2c-highlander.c
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@ -227,7 +227,7 @@ static int highlander_i2c_read(struct highlander_i2c_dev *dev)
/* /*
* The R0P7780LC0011RL FPGA needs a significant delay between * The R0P7780LC0011RL FPGA needs a significant delay between
* data read cycles, otherwise the transciever gets confused and * data read cycles, otherwise the transceiver gets confused and
* garbage is returned when the read is subsequently aborted. * garbage is returned when the read is subsequently aborted.
* *
* It is not sufficient to wait for BBSY. * It is not sufficient to wait for BBSY.

2
drivers/net/eexpress.c
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@ -365,7 +365,7 @@ static int __init do_express_probe(struct net_device *dev)
dev->irq = mca_irqmap[(pos1>>4)&0x7]; dev->irq = mca_irqmap[(pos1>>4)&0x7];
/* /*
* XXX: Transciever selection is done * XXX: Transceiver selection is done
* differently on the MCA version. * differently on the MCA version.
* How to get it to select something * How to get it to select something
* other than external/AUI is currently * other than external/AUI is currently

2
drivers/net/irda/toim3232-sir.c
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@ -78,7 +78,7 @@
* Target hardware: IRWave IR320ST-2 * Target hardware: IRWave IR320ST-2
* *
* The IRWave IR320ST-2 is a simple dongle based on the Vishay/Temic * The IRWave IR320ST-2 is a simple dongle based on the Vishay/Temic
* TOIM3232 SIR Endec and the Vishay/Temic TFDS4500 SIR IRDA transciever. * TOIM3232 SIR Endec and the Vishay/Temic TFDS4500 SIR IRDA transceiver.
* It uses a hex inverter and some discrete components to buffer and * It uses a hex inverter and some discrete components to buffer and
* line convert the RS232 down to 5V. * line convert the RS232 down to 5V.
* *

2
drivers/net/natsemi.c
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@ -2919,7 +2919,7 @@ static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
/* /*
* If we're ignoring the PHY then autoneg and the internal * If we're ignoring the PHY then autoneg and the internal
* transciever are really not going to work so don't let the * transceiver are really not going to work so don't let the
* user select them. * user select them.
*/ */
if (np->ignore_phy && (ecmd->autoneg == AUTONEG_ENABLE || if (np->ignore_phy && (ecmd->autoneg == AUTONEG_ENABLE ||

2
drivers/tty/serial/8250_pci.c
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@ -743,7 +743,7 @@ pci_ni8430_setup(struct serial_private *priv,
len = pci_resource_len(priv->dev, bar); len = pci_resource_len(priv->dev, bar);
p = ioremap_nocache(base, len); p = ioremap_nocache(base, len);
/* enable the transciever */ /* enable the transceiver */
writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
p + offset + NI8430_PORTCON); p + offset + NI8430_PORTCON);

4
drivers/usb/gadget/pxa27x_udc.h
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@ -88,9 +88,9 @@
#define UDCISR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL) #define UDCISR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL)
#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ #define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt #define UDCOTGICR_IEXR (1 << 17) /* Extra Transceiver Interrupt
Rising Edge Interrupt Enable */ Rising Edge Interrupt Enable */
#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt #define UDCOTGICR_IEXF (1 << 16) /* Extra Transceiver Interrupt
Falling Edge Interrupt Enable */ Falling Edge Interrupt Enable */
#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge #define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
Interrupt Enable */ Interrupt Enable */

2
drivers/usb/musb/musb_core.c
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@ -1955,7 +1955,7 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
* - initializes musb->xceiv, usually by otg_get_transceiver() * - initializes musb->xceiv, usually by otg_get_transceiver()
* - stops powering VBUS * - stops powering VBUS
* *
* There are various transciever configurations. Blackfin, * There are various transceiver configurations. Blackfin,
* DaVinci, TUSB60x0, and others integrate them. OMAP3 uses * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
* external/discrete ones in various flavors (twl4030 family, * external/discrete ones in various flavors (twl4030 family,
* isp1504, non-OTG, etc) mostly hooking up through ULPI. * isp1504, non-OTG, etc) mostly hooking up through ULPI.

4
drivers/usb/otg/isp1301_omap.c
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@ -660,7 +660,7 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp)
int ret = IRQ_NONE; int ret = IRQ_NONE;
struct isp1301 *isp = _isp; struct isp1301 *isp = _isp;
/* update ISP1301 transciever from OTG controller */ /* update ISP1301 transceiver from OTG controller */
if (otg_irq & OPRT_CHG) { if (otg_irq & OPRT_CHG) {
omap_writew(OPRT_CHG, OTG_IRQ_SRC); omap_writew(OPRT_CHG, OTG_IRQ_SRC);
isp1301_defer_work(isp, WORK_UPDATE_ISP); isp1301_defer_work(isp, WORK_UPDATE_ISP);
@ -755,7 +755,7 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp)
omap_writew(A_VBUS_ERR, OTG_IRQ_SRC); omap_writew(A_VBUS_ERR, OTG_IRQ_SRC);
ret = IRQ_HANDLED; ret = IRQ_HANDLED;
/* switch driver; the transciever code activates it, /* switch driver; the transceiver code activates it,
* ungating the udc clock or resuming OHCI. * ungating the udc clock or resuming OHCI.
*/ */
} else if (otg_irq & DRIVER_SWITCH) { } else if (otg_irq & DRIVER_SWITCH) {

2
sound/pci/ice1712/ice1712.c
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@ -87,7 +87,7 @@ static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
static char *model[SNDRV_CARDS]; static char *model[SNDRV_CARDS];
static int omni[SNDRV_CARDS]; /* Delta44 & 66 Omni I/O support */ static int omni[SNDRV_CARDS]; /* Delta44 & 66 Omni I/O support */
static int cs8427_timeout[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 500}; /* CS8427 S/PDIF transciever reset timeout value in msec */ static int cs8427_timeout[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 500}; /* CS8427 S/PDIF transceiver reset timeout value in msec */
static int dxr_enable[SNDRV_CARDS]; /* DXR enable for DMX6FIRE */ static int dxr_enable[SNDRV_CARDS]; /* DXR enable for DMX6FIRE */
module_param_array(index, int, NULL, 0444); module_param_array(index, int, NULL, 0444);