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ARM: tegra: fix overflow in tegra20_pll_clk_round_rate() 

32-bit math isn't enough when e.g. *prate=12000000, and sel->n=1000.
Use 64-bit math to prevent this.

Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Stephen Warren 2012-09-10 17:02:45 -06:00
parent fa67ccb61d
commit 7a74a4436b
1 changed files with 1 additions and 1 deletions
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2
arch/arm/mach-tegra/tegra20_clocks.c
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@ -789,7 +789,7 @@ static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
struct clk_tegra *c = to_clk_tegra(hw);
const struct clk_pll_freq_table *sel;
unsigned long input_rate = *prate;
unsigned long output_rate = *prate;
u64 output_rate = *prate;
int mul;
int div;