drm/dp: Document DP spec versions for various DPCD registers
Note with a comment anything newer than DP 1.1a. Obviously this needs some work still... Signed-off-by: Adam Jackson <ajax@redhat.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Adam Jackson
Daniel Vetter
parent
caf9ab24e3
commit
7883dc55e1
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@ -26,7 +26,19 @@
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#include <linux/types.h>
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#include <linux/i2c.h>
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/* From the VESA DisplayPort spec */
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/*
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* Unless otherwise noted, all values are from the DP 1.1a spec. Note that
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* DP and DPCD versions are independent. Differences from 1.0 are not noted,
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* 1.0 devices basically don't exist in the wild.
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*
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* Abbreviations, in chronological order:
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*
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* eDP: Embedded DisplayPort version 1
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* DPI: DisplayPort Interoperability Guideline v1.1a
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* 1.2: DisplayPort 1.2
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*
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* 1.2 formally includes both eDP and DPI definitions.
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*/
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#define AUX_NATIVE_WRITE 0x8
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#define AUX_NATIVE_READ 0x9
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@ -53,7 +65,7 @@
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#define DP_MAX_LANE_COUNT 0x002
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# define DP_MAX_LANE_COUNT_MASK 0x1f
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# define DP_TPS3_SUPPORTED (1 << 6)
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# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
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# define DP_ENHANCED_FRAME_CAP (1 << 7)
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#define DP_MAX_DOWNSPREAD 0x003
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@ -69,16 +81,16 @@
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/* 10b = TMDS or HDMI */
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/* 11b = Other */
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# define DP_FORMAT_CONVERSION (1 << 3)
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# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4)
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# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
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#define DP_MAIN_LINK_CHANNEL_CODING 0x006
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#define DP_DOWN_STREAM_PORT_COUNT 0x007
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# define DP_PORT_COUNT_MASK 0x0f
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# define DP_MSA_TIMING_PAR_IGNORED (1 << 6)
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# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
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# define DP_OUI_SUPPORT (1 << 7)
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#define DP_I2C_SPEED_CAP 0x00c
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#define DP_I2C_SPEED_CAP 0x00c /* DPI */
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# define DP_I2C_SPEED_1K 0x01
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# define DP_I2C_SPEED_5K 0x02
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# define DP_I2C_SPEED_10K 0x04
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@ -86,16 +98,16 @@
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# define DP_I2C_SPEED_400K 0x10
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# define DP_I2C_SPEED_1M 0x20
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#define DP_EDP_CONFIGURATION_CAP 0x00d
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#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
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#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
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#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
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/* Multiple stream transport */
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#define DP_MSTM_CAP 0x021
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#define DP_MSTM_CAP 0x021 /* 1.2 */
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# define DP_MST_CAP (1 << 0)
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#define DP_PSR_SUPPORT 0x070
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#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
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# define DP_PSR_IS_SUPPORTED 1
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#define DP_PSR_CAPS 0x071
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#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
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# define DP_PSR_NO_TRAIN_ON_EXIT 1
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# define DP_PSR_SETUP_TIME_330 (0 << 1)
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# define DP_PSR_SETUP_TIME_275 (1 << 1)
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@ -136,7 +148,7 @@
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#define DP_LINK_BW_SET 0x100
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# define DP_LINK_BW_1_62 0x06
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# define DP_LINK_BW_2_7 0x0a
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# define DP_LINK_BW_5_4 0x14
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# define DP_LINK_BW_5_4 0x14 /* 1.2 */
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#define DP_LANE_COUNT_SET 0x101
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# define DP_LANE_COUNT_MASK 0x0f
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@ -146,7 +158,7 @@
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# define DP_TRAINING_PATTERN_DISABLE 0
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# define DP_TRAINING_PATTERN_1 1
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# define DP_TRAINING_PATTERN_2 2
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# define DP_TRAINING_PATTERN_3 3
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# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
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# define DP_TRAINING_PATTERN_MASK 0x3
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# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
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@ -187,22 +199,22 @@
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#define DP_DOWNSPREAD_CTRL 0x107
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# define DP_SPREAD_AMP_0_5 (1 << 4)
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# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7)
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# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
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#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
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# define DP_SET_ANSI_8B10B (1 << 0)
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#define DP_I2C_SPEED_CONTROL_STATUS 0x109
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#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
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/* bitmask as for DP_I2C_SPEED_CAP */
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#define DP_EDP_CONFIGURATION_SET 0x10a
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#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
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#define DP_MSTM_CTRL 0x111
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#define DP_MSTM_CTRL 0x111 /* 1.2 */
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# define DP_MST_EN (1 << 0)
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# define DP_UP_REQ_EN (1 << 1)
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# define DP_UPSTREAM_IS_SRC (1 << 2)
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#define DP_PSR_EN_CFG 0x170
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#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
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# define DP_PSR_ENABLE (1 << 0)
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# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
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# define DP_PSR_CRC_VERIFICATION (1 << 2)
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@ -277,14 +289,14 @@
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# define DP_SET_POWER_D0 0x1
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# define DP_SET_POWER_D3 0x2
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#define DP_PSR_ERROR_STATUS 0x2006
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#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
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# define DP_PSR_LINK_CRC_ERROR (1 << 0)
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# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
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#define DP_PSR_ESI 0x2007
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#define DP_PSR_ESI 0x2007 /* XXX 1.2? */
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# define DP_PSR_CAPS_CHANGE (1 << 0)
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#define DP_PSR_STATUS 0x2008
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#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
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# define DP_PSR_SINK_INACTIVE 0
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# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
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# define DP_PSR_SINK_ACTIVE_RFB 2
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