ARM: imx5x: clean up ARCH_MX5X
Move to SOC_SOC_IMX5X. Leave only places which prevent multi-soc using ARCH_MX5X. Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
parent
48f6b09996
commit
7685167128
|
@ -1,5 +1,6 @@
|
||||||
if ARCH_MX5
|
if ARCH_MX5
|
||||||
# ARCH_MX51 and ARCH_MX50 are left for compatibility
|
# ARCH_MX50/51/53 are left to mark places where prevent multi-soc in single
|
||||||
|
# image. So for most time, SOC_IMX50/51/53 should be used.
|
||||||
|
|
||||||
config ARCH_MX50
|
config ARCH_MX50
|
||||||
bool
|
bool
|
||||||
|
|
|
@ -194,7 +194,7 @@ static int __init imxXX_add_imx_dma(void)
|
||||||
} else
|
} else
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_ARCH_MX51)
|
#if defined(CONFIG_SOC_IMX51)
|
||||||
if (cpu_is_mx51()) {
|
if (cpu_is_mx51()) {
|
||||||
imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1;
|
imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1;
|
||||||
ret = imx_add_imx_sdma(&imx51_imx_sdma_data);
|
ret = imx_add_imx_sdma(&imx51_imx_sdma_data);
|
||||||
|
|
|
@ -23,17 +23,17 @@
|
||||||
#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
|
#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
|
||||||
|
|
||||||
/* these are ordered by size to support multi-SoC kernels */
|
/* these are ordered by size to support multi-SoC kernels */
|
||||||
#if defined CONFIG_ARCH_MX53
|
#if defined CONFIG_SOC_IMX53
|
||||||
#define MXC_GPIO_IRQS (32 * 7)
|
#define MXC_GPIO_IRQS (32 * 7)
|
||||||
#elif defined CONFIG_ARCH_MX2
|
#elif defined CONFIG_ARCH_MX2
|
||||||
#define MXC_GPIO_IRQS (32 * 6)
|
#define MXC_GPIO_IRQS (32 * 6)
|
||||||
#elif defined CONFIG_ARCH_MX50
|
#elif defined CONFIG_SOC_IMX50
|
||||||
#define MXC_GPIO_IRQS (32 * 6)
|
#define MXC_GPIO_IRQS (32 * 6)
|
||||||
#elif defined CONFIG_ARCH_MX1
|
#elif defined CONFIG_ARCH_MX1
|
||||||
#define MXC_GPIO_IRQS (32 * 4)
|
#define MXC_GPIO_IRQS (32 * 4)
|
||||||
#elif defined CONFIG_ARCH_MX25
|
#elif defined CONFIG_ARCH_MX25
|
||||||
#define MXC_GPIO_IRQS (32 * 4)
|
#define MXC_GPIO_IRQS (32 * 4)
|
||||||
#elif defined CONFIG_ARCH_MX51
|
#elif defined CONFIG_SOC_IMX51
|
||||||
#define MXC_GPIO_IRQS (32 * 4)
|
#define MXC_GPIO_IRQS (32 * 4)
|
||||||
#elif defined CONFIG_ARCH_MXC91231
|
#elif defined CONFIG_ARCH_MXC91231
|
||||||
#define MXC_GPIO_IRQS (32 * 4)
|
#define MXC_GPIO_IRQS (32 * 4)
|
||||||
|
|
|
@ -127,7 +127,7 @@ extern unsigned int __mxc_cpu_type;
|
||||||
# define cpu_is_mx35() (0)
|
# define cpu_is_mx35() (0)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_MX50
|
#ifdef CONFIG_SOC_IMX50
|
||||||
# ifdef mxc_cpu_type
|
# ifdef mxc_cpu_type
|
||||||
# undef mxc_cpu_type
|
# undef mxc_cpu_type
|
||||||
# define mxc_cpu_type __mxc_cpu_type
|
# define mxc_cpu_type __mxc_cpu_type
|
||||||
|
@ -139,7 +139,7 @@ extern unsigned int __mxc_cpu_type;
|
||||||
# define cpu_is_mx50() (0)
|
# define cpu_is_mx50() (0)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_MX51
|
#ifdef CONFIG_SOC_IMX51
|
||||||
# ifdef mxc_cpu_type
|
# ifdef mxc_cpu_type
|
||||||
# undef mxc_cpu_type
|
# undef mxc_cpu_type
|
||||||
# define mxc_cpu_type __mxc_cpu_type
|
# define mxc_cpu_type __mxc_cpu_type
|
||||||
|
@ -151,7 +151,7 @@ extern unsigned int __mxc_cpu_type;
|
||||||
# define cpu_is_mx51() (0)
|
# define cpu_is_mx51() (0)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_MX53
|
#ifdef CONFIG_SOC_IMX53
|
||||||
# ifdef mxc_cpu_type
|
# ifdef mxc_cpu_type
|
||||||
# undef mxc_cpu_type
|
# undef mxc_cpu_type
|
||||||
# define mxc_cpu_type __mxc_cpu_type
|
# define mxc_cpu_type __mxc_cpu_type
|
||||||
|
|
|
@ -476,7 +476,7 @@ config MTD_NAND_MPC5121_NFC
|
||||||
|
|
||||||
config MTD_NAND_MXC
|
config MTD_NAND_MXC
|
||||||
tristate "MXC NAND support"
|
tristate "MXC NAND support"
|
||||||
depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3 || ARCH_MX51
|
depends on IMX_HAVE_PLATFORM_MXC_NAND
|
||||||
help
|
help
|
||||||
This enables the driver for the NAND flash controller on the
|
This enables the driver for the NAND flash controller on the
|
||||||
MXC processors.
|
MXC processors.
|
||||||
|
|
|
@ -164,10 +164,10 @@ config SPI_IMX_VER_0_4
|
||||||
def_bool y if ARCH_MX31
|
def_bool y if ARCH_MX31
|
||||||
|
|
||||||
config SPI_IMX_VER_0_7
|
config SPI_IMX_VER_0_7
|
||||||
def_bool y if ARCH_MX25 || ARCH_MX35 || ARCH_MX51 || ARCH_MX53
|
def_bool y if ARCH_MX25 || ARCH_MX35 || SOC_IMX51 || SOC_IMX53
|
||||||
|
|
||||||
config SPI_IMX_VER_2_3
|
config SPI_IMX_VER_2_3
|
||||||
def_bool y if ARCH_MX51 || ARCH_MX53
|
def_bool y if SOC_IMX51 || SOC_IMX53
|
||||||
|
|
||||||
config SPI_IMX
|
config SPI_IMX
|
||||||
tristate "Freescale i.MX SPI controllers"
|
tristate "Freescale i.MX SPI controllers"
|
||||||
|
|
Reference in New Issue