sdhci-of: reorganize driver to support additional hardware
This patch breaks down sdhci-of into a core portion and a eSDHC portion, clearing the path to easily support additional hardware using the same OF driver. Signed-off-by: Albert Herranz <albert_herranz@yahoo.es> Cc: <linux-mmc@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Albert Herranz
Linus Torvalds
parent
bc1ad567b1
commit
7657c3a7d4
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@ -44,6 +44,19 @@ config MMC_SDHCI_IO_ACCESSORS
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This is silent Kconfig symbol that is selected by the drivers that
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need to overwrite SDHCI IO memory accessors.
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config MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
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bool
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select MMC_SDHCI_IO_ACCESSORS
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help
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This option is selected by drivers running on big endian hosts
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and performing I/O to a SDHCI controller through a bus that
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implements a hardware byte swapper using a 32-bit datum.
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This endian mapping mode is called "data invariance" and
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has the effect of scrambling the addresses and formats of data
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accessed in sizes other than the datum size.
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This is the case for the Freescale eSDHC.
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config MMC_SDHCI_PCI
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tristate "SDHCI support on PCI bus"
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depends on MMC_SDHCI && PCI
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@ -75,11 +88,18 @@ config MMC_RICOH_MMC
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config MMC_SDHCI_OF
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tristate "SDHCI support on OpenFirmware platforms"
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depends on MMC_SDHCI && PPC_OF
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select MMC_SDHCI_IO_ACCESSORS
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help
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This selects the OF support for Secure Digital Host Controller
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Interfaces. So far, only the Freescale eSDHC controller is known
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to exist on OF platforms.
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Interfaces.
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If unsure, say N.
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config MMC_SDHCI_OF_ESDHC
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bool "SDHCI OF support for the Freescale eSDHC controller"
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depends on MMC_SDHCI_OF
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select MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
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help
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This selects the Freescale eSDHC controller support.
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If unsure, say N.
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@ -38,6 +38,7 @@ obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o
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obj-$(CONFIG_MMC_SDHCI_OF) += sdhci-of.o
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sdhci-of-y := sdhci-of-core.o
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sdhci-of-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
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ifeq ($(CONFIG_CB710_DEBUG),y)
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CFLAGS-cb710-mmc += -DDEBUG
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@ -22,62 +22,37 @@
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#include <linux/of_platform.h>
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#include <linux/mmc/host.h>
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#include <asm/machdep.h>
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#include "sdhci-of.h"
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#include "sdhci.h"
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struct sdhci_of_data {
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unsigned int quirks;
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struct sdhci_ops ops;
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};
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struct sdhci_of_host {
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unsigned int clock;
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u16 xfer_mode_shadow;
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};
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#ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
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/*
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* Ops and quirks for the Freescale eSDHC controller.
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* These accessors are designed for big endian hosts doing I/O to
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* little endian controllers incorporating a 32-bit hardware byte swapper.
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*/
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#define ESDHC_DMA_SYSCTL 0x40c
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#define ESDHC_DMA_SNOOP 0x00000040
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#define ESDHC_SYSTEM_CONTROL 0x2c
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#define ESDHC_CLOCK_MASK 0x0000fff0
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#define ESDHC_PREDIV_SHIFT 8
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#define ESDHC_DIVIDER_SHIFT 4
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#define ESDHC_CLOCK_PEREN 0x00000004
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#define ESDHC_CLOCK_HCKEN 0x00000002
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#define ESDHC_CLOCK_IPGEN 0x00000001
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#define ESDHC_HOST_CONTROL_RES 0x05
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static u32 esdhc_readl(struct sdhci_host *host, int reg)
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u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg)
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{
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return in_be32(host->ioaddr + reg);
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}
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static u16 esdhc_readw(struct sdhci_host *host, int reg)
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u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg)
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{
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u16 ret;
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if (unlikely(reg == SDHCI_HOST_VERSION))
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ret = in_be16(host->ioaddr + reg);
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else
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ret = in_be16(host->ioaddr + (reg ^ 0x2));
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return ret;
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return in_be16(host->ioaddr + (reg ^ 0x2));
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}
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static u8 esdhc_readb(struct sdhci_host *host, int reg)
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u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg)
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{
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return in_8(host->ioaddr + (reg ^ 0x3));
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}
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static void esdhc_writel(struct sdhci_host *host, u32 val, int reg)
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void sdhci_be32bs_writel(struct sdhci_host *host, u32 val, int reg)
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{
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out_be32(host->ioaddr + reg, val);
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}
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static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
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void sdhci_be32bs_writew(struct sdhci_host *host, u16 val, int reg)
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{
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struct sdhci_of_host *of_host = sdhci_priv(host);
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int base = reg & ~0x3;
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@ -92,106 +67,21 @@ static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
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of_host->xfer_mode_shadow = val;
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return;
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case SDHCI_COMMAND:
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esdhc_writel(host, val << 16 | of_host->xfer_mode_shadow,
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SDHCI_TRANSFER_MODE);
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sdhci_be32bs_writel(host, val << 16 | of_host->xfer_mode_shadow,
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SDHCI_TRANSFER_MODE);
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return;
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case SDHCI_BLOCK_SIZE:
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/*
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* Two last DMA bits are reserved, and first one is used for
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* non-standard blksz of 4096 bytes that we don't support
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* yet. So clear the DMA boundary bits.
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*/
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val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
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/* fall through */
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}
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clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);
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}
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static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
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void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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int base = reg & ~0x3;
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int shift = (reg & 0x3) * 8;
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/* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
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if (reg == SDHCI_HOST_CONTROL)
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val &= ~ESDHC_HOST_CONTROL_RES;
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clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
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}
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static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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int pre_div = 2;
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int div = 1;
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clrbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
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ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
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if (clock == 0)
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goto out;
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while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
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pre_div *= 2;
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while (host->max_clk / pre_div / div > clock && div < 16)
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div++;
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dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
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clock, host->max_clk / pre_div / div);
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pre_div >>= 1;
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div--;
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setbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
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ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
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div << ESDHC_DIVIDER_SHIFT | pre_div << ESDHC_PREDIV_SHIFT);
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mdelay(100);
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out:
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host->clock = clock;
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}
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static int esdhc_enable_dma(struct sdhci_host *host)
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{
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setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
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return 0;
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}
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static unsigned int esdhc_get_max_clock(struct sdhci_host *host)
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{
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struct sdhci_of_host *of_host = sdhci_priv(host);
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return of_host->clock;
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}
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static unsigned int esdhc_get_min_clock(struct sdhci_host *host)
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{
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struct sdhci_of_host *of_host = sdhci_priv(host);
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return of_host->clock / 256 / 16;
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}
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static struct sdhci_of_data sdhci_esdhc = {
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.quirks = SDHCI_QUIRK_FORCE_BLK_SZ_2048 |
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SDHCI_QUIRK_BROKEN_CARD_DETECTION |
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SDHCI_QUIRK_NO_BUSY_IRQ |
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SDHCI_QUIRK_NONSTANDARD_CLOCK |
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SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
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SDHCI_QUIRK_PIO_NEEDS_DELAY |
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SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET |
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SDHCI_QUIRK_NO_CARD_NO_RESET,
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.ops = {
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.readl = esdhc_readl,
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.readw = esdhc_readw,
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.readb = esdhc_readb,
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.writel = esdhc_writel,
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.writew = esdhc_writew,
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.writeb = esdhc_writeb,
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.set_clock = esdhc_set_clock,
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.enable_dma = esdhc_enable_dma,
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.get_max_clock = esdhc_get_max_clock,
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.get_min_clock = esdhc_get_min_clock,
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},
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};
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#endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */
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#ifdef CONFIG_PM
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@ -301,9 +191,11 @@ static int __devexit sdhci_of_remove(struct of_device *ofdev)
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}
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static const struct of_device_id sdhci_of_match[] = {
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#ifdef CONFIG_MMC_SDHCI_OF_ESDHC
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{ .compatible = "fsl,mpc8379-esdhc", .data = &sdhci_esdhc, },
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{ .compatible = "fsl,mpc8536-esdhc", .data = &sdhci_esdhc, },
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{ .compatible = "fsl,esdhc", .data = &sdhci_esdhc, },
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#endif
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{ .compatible = "generic-sdhci", },
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{},
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};
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@ -0,0 +1,143 @@
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/*
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* Freescale eSDHC controller driver.
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*
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* Copyright (c) 2007 Freescale Semiconductor, Inc.
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* Copyright (c) 2009 MontaVista Software, Inc.
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*
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* Authors: Xiaobo Xie <X.Xie@freescale.com>
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/mmc/host.h>
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#include "sdhci-of.h"
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#include "sdhci.h"
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/*
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* Ops and quirks for the Freescale eSDHC controller.
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*/
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#define ESDHC_DMA_SYSCTL 0x40c
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#define ESDHC_DMA_SNOOP 0x00000040
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#define ESDHC_SYSTEM_CONTROL 0x2c
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#define ESDHC_CLOCK_MASK 0x0000fff0
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#define ESDHC_PREDIV_SHIFT 8
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#define ESDHC_DIVIDER_SHIFT 4
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#define ESDHC_CLOCK_PEREN 0x00000004
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#define ESDHC_CLOCK_HCKEN 0x00000002
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#define ESDHC_CLOCK_IPGEN 0x00000001
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#define ESDHC_HOST_CONTROL_RES 0x05
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static u16 esdhc_readw(struct sdhci_host *host, int reg)
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{
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u16 ret;
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if (unlikely(reg == SDHCI_HOST_VERSION))
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ret = in_be16(host->ioaddr + reg);
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else
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ret = sdhci_be32bs_readw(host, reg);
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return ret;
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}
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static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
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{
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if (reg == SDHCI_BLOCK_SIZE) {
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/*
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* Two last DMA bits are reserved, and first one is used for
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* non-standard blksz of 4096 bytes that we don't support
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* yet. So clear the DMA boundary bits.
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*/
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val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
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}
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sdhci_be32bs_writew(host, val, reg);
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}
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static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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/* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
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if (reg == SDHCI_HOST_CONTROL)
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val &= ~ESDHC_HOST_CONTROL_RES;
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sdhci_be32bs_writeb(host, val, reg);
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}
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static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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int pre_div = 2;
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int div = 1;
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clrbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
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ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
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if (clock == 0)
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goto out;
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while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
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pre_div *= 2;
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while (host->max_clk / pre_div / div > clock && div < 16)
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div++;
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dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
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clock, host->max_clk / pre_div / div);
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pre_div >>= 1;
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div--;
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setbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
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ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
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div << ESDHC_DIVIDER_SHIFT | pre_div << ESDHC_PREDIV_SHIFT);
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mdelay(100);
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out:
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host->clock = clock;
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}
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static int esdhc_enable_dma(struct sdhci_host *host)
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{
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setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
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return 0;
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}
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static unsigned int esdhc_get_max_clock(struct sdhci_host *host)
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{
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struct sdhci_of_host *of_host = sdhci_priv(host);
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return of_host->clock;
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}
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static unsigned int esdhc_get_min_clock(struct sdhci_host *host)
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{
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struct sdhci_of_host *of_host = sdhci_priv(host);
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return of_host->clock / 256 / 16;
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}
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struct sdhci_of_data sdhci_esdhc = {
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.quirks = SDHCI_QUIRK_FORCE_BLK_SZ_2048 |
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SDHCI_QUIRK_BROKEN_CARD_DETECTION |
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SDHCI_QUIRK_NO_BUSY_IRQ |
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SDHCI_QUIRK_NONSTANDARD_CLOCK |
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SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
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SDHCI_QUIRK_PIO_NEEDS_DELAY |
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SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET |
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SDHCI_QUIRK_NO_CARD_NO_RESET,
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.ops = {
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.readl = sdhci_be32bs_readl,
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.readw = esdhc_readw,
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.readb = sdhci_be32bs_readb,
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.writel = sdhci_be32bs_writel,
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.writew = esdhc_writew,
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.writeb = esdhc_writeb,
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.set_clock = esdhc_set_clock,
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.enable_dma = esdhc_enable_dma,
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.get_max_clock = esdhc_get_max_clock,
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.get_min_clock = esdhc_get_min_clock,
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},
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};
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@ -0,0 +1,41 @@
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/*
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* OpenFirmware bindings for Secure Digital Host Controller Interface.
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*
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* Copyright (c) 2007 Freescale Semiconductor, Inc.
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* Copyright (c) 2009 MontaVista Software, Inc.
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*
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* Authors: Xiaobo Xie <X.Xie@freescale.com>
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#ifndef __SDHCI_OF_H
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#define __SDHCI_OF_H
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#include <linux/types.h>
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#include "sdhci.h"
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struct sdhci_of_data {
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unsigned int quirks;
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struct sdhci_ops ops;
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};
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struct sdhci_of_host {
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unsigned int clock;
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u16 xfer_mode_shadow;
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};
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extern u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg);
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extern u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg);
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extern u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg);
|
||||
extern void sdhci_be32bs_writel(struct sdhci_host *host, u32 val, int reg);
|
||||
extern void sdhci_be32bs_writew(struct sdhci_host *host, u16 val, int reg);
|
||||
extern void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg);
|
||||
|
||||
extern struct sdhci_of_data sdhci_esdhc;
|
||||
|
||||
#endif /* __SDHCI_OF_H */
|
||||
Reference in New Issue