ath9k_hw: Fix PLL initialization for AR9485.
Increase the delay to make sure the initialization of pll passes. Signed-off-by: Vivek Natarajan <vnatarajan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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1 changed files with 2 additions and 2 deletions
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@ -701,7 +701,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
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AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
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REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
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udelay(100);
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udelay(1000);
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REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
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@ -713,7 +713,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
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AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
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REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c);
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udelay(110);
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udelay(1000);
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}
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pll = ath9k_hw_compute_pll_control(ah, chan);
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