drm/i915: use transcoder select bits on VGA and HDMI on CPT
Required for 3 pipe functionality. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-By: Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-By: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: Keith Packard <keithp@keithp.com>
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d9d444cbc5
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75770564c9
2 changed files with 11 additions and 17 deletions
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@ -152,17 +152,13 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
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if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
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if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
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adpa |= ADPA_VSYNC_ACTIVE_HIGH;
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adpa |= ADPA_VSYNC_ACTIVE_HIGH;
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if (intel_crtc->pipe == 0) {
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/* For CPT allow 3 pipe config, for others just use A or B */
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if (HAS_PCH_CPT(dev))
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if (HAS_PCH_CPT(dev))
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adpa |= PORT_TRANS_A_SEL_CPT;
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adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
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else
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else if (intel_crtc->pipe == 0)
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adpa |= ADPA_PIPE_A_SELECT;
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adpa |= ADPA_PIPE_A_SELECT;
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} else {
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else
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if (HAS_PCH_CPT(dev))
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adpa |= ADPA_PIPE_B_SELECT;
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adpa |= PORT_TRANS_B_SEL_CPT;
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else
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adpa |= ADPA_PIPE_B_SELECT;
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}
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if (!HAS_PCH_SPLIT(dev))
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if (!HAS_PCH_SPLIT(dev))
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I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
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I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
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@ -252,12 +252,10 @@ static void intel_hdmi_mode_set(struct drm_encoder *encoder,
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intel_write_eld(encoder, adjusted_mode);
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intel_write_eld(encoder, adjusted_mode);
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}
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}
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if (intel_crtc->pipe == 1) {
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if (HAS_PCH_CPT(dev))
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if (HAS_PCH_CPT(dev))
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sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
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sdvox |= PORT_TRANS_B_SEL_CPT;
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else if (intel_crtc->pipe == 1)
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else
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sdvox |= SDVO_PIPE_B_SELECT;
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sdvox |= SDVO_PIPE_B_SELECT;
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}
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I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
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I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
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POSTING_READ(intel_hdmi->sdvox_reg);
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POSTING_READ(intel_hdmi->sdvox_reg);
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