cxgb3 - T3C support update
Update GPIO mapping for T3C. Update xgmac for T3C support. Fix typo in mtu table. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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75758e8aa4
3 changed files with 58 additions and 19 deletions
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@ -1937,6 +1937,10 @@
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#define A_XGM_RXFIFO_CFG 0x884
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#define S_RXFIFO_EMPTY 31
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#define V_RXFIFO_EMPTY(x) ((x) << S_RXFIFO_EMPTY)
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#define F_RXFIFO_EMPTY V_RXFIFO_EMPTY(1U)
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#define S_RXFIFOPAUSEHWM 17
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#define M_RXFIFOPAUSEHWM 0xfff
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@ -1961,6 +1965,10 @@
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#define A_XGM_TXFIFO_CFG 0x888
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#define S_UNDERUNFIX 22
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#define V_UNDERUNFIX(x) ((x) << S_UNDERUNFIX)
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#define F_UNDERUNFIX V_UNDERUNFIX(1U)
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#define S_TXIPG 13
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#define M_TXIPG 0xff
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#define V_TXIPG(x) ((x) << S_TXIPG)
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@ -2034,10 +2042,27 @@
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#define V_XAUIIMP(x) ((x) << S_XAUIIMP)
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#define A_XGM_RX_MAX_PKT_SIZE 0x8a8
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#define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4
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#define S_RXMAXFRAMERSIZE 17
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#define M_RXMAXFRAMERSIZE 0x3fff
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#define V_RXMAXFRAMERSIZE(x) ((x) << S_RXMAXFRAMERSIZE)
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#define G_RXMAXFRAMERSIZE(x) (((x) >> S_RXMAXFRAMERSIZE) & M_RXMAXFRAMERSIZE)
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#define S_RXENFRAMER 14
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#define V_RXENFRAMER(x) ((x) << S_RXENFRAMER)
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#define F_RXENFRAMER V_RXENFRAMER(1U)
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#define S_RXMAXPKTSIZE 0
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#define M_RXMAXPKTSIZE 0x3fff
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#define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE)
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#define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE)
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#define A_XGM_RESET_CTRL 0x8ac
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#define S_XGMAC_STOP_EN 4
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#define V_XGMAC_STOP_EN(x) ((x) << S_XGMAC_STOP_EN)
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#define F_XGMAC_STOP_EN V_XGMAC_STOP_EN(1U)
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#define S_XG2G_RESET_ 3
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#define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_)
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#define F_XG2G_RESET_ V_XG2G_RESET_(1U)
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@ -447,8 +447,8 @@ static const struct adapter_info t3_adap_info[] = {
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&mi1_mdio_ops, "Chelsio T302"},
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{1, 0, 0, 0,
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F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN |
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F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, 0,
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SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
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F_GPIO11_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
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0, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
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&mi1_mdio_ext_ops, "Chelsio T310"},
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{2, 0, 0, 0,
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F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN |
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@ -2613,7 +2613,7 @@ static void __devinit init_mtus(unsigned short mtus[])
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* it can accomodate max size TCP/IP headers when SACK and timestamps
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* are enabled and still have at least 8 bytes of payload.
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*/
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mtus[1] = 88;
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mtus[0] = 88;
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mtus[1] = 88;
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mtus[2] = 256;
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mtus[3] = 512;
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@ -106,6 +106,7 @@ int t3_mac_reset(struct cmac *mac)
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t3_set_reg_field(adap, A_XGM_RXFIFO_CFG + oft,
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F_RXSTRFRWRD | F_DISERRFRAMES,
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uses_xaui(adap) ? 0 : F_RXSTRFRWRD);
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t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft, 0, F_UNDERUNFIX);
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if (uses_xaui(adap)) {
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if (adap->params.rev == 0) {
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@ -124,7 +125,11 @@ int t3_mac_reset(struct cmac *mac)
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xaui_serdes_reset(mac);
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}
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val = F_MAC_RESET_;
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t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + oft,
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V_RXMAXFRAMERSIZE(M_RXMAXFRAMERSIZE),
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V_RXMAXFRAMERSIZE(MAX_FRAME_SIZE) | F_RXENFRAMER);
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val = F_MAC_RESET_ | F_XGMAC_STOP_EN;
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if (is_10G(adap))
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val |= F_PCS_RESET_;
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else if (uses_xaui(adap))
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@ -313,8 +318,9 @@ static int rx_fifo_hwm(int mtu)
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int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
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{
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int hwm, lwm;
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unsigned int thres, v;
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int hwm, lwm, divisor;
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int ipg;
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unsigned int thres, v, reg;
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struct adapter *adap = mac->adapter;
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/*
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@ -335,27 +341,32 @@ int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
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hwm = min(hwm, MAC_RXFIFO_SIZE - 8192);
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lwm = min(3 * (int)mtu, MAC_RXFIFO_SIZE / 4);
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if (adap->params.rev == T3_REV_B2 &&
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if (adap->params.rev >= T3_REV_B2 &&
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(t3_read_reg(adap, A_XGM_RX_CTRL + mac->offset) & F_RXEN)) {
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disable_exact_filters(mac);
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v = t3_read_reg(adap, A_XGM_RX_CFG + mac->offset);
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t3_set_reg_field(adap, A_XGM_RX_CFG + mac->offset,
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F_ENHASHMCAST | F_COPYALLFRAMES, F_DISBCAST);
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/* drain rx FIFO */
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if (t3_wait_op_done(adap,
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A_XGM_RX_MAX_PKT_SIZE_ERR_CNT +
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mac->offset,
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1 << 31, 1, 20, 5)) {
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reg = adap->params.rev == T3_REV_B2 ?
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A_XGM_RX_MAX_PKT_SIZE_ERR_CNT : A_XGM_RXFIFO_CFG;
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/* drain RX FIFO */
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if (t3_wait_op_done(adap, reg + mac->offset,
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F_RXFIFO_EMPTY, 1, 20, 5)) {
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t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
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enable_exact_filters(mac);
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return -EIO;
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}
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t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);
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t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset,
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V_RXMAXPKTSIZE(M_RXMAXPKTSIZE),
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V_RXMAXPKTSIZE(mtu));
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t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
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enable_exact_filters(mac);
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} else
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t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);
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t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset,
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V_RXMAXPKTSIZE(M_RXMAXPKTSIZE),
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V_RXMAXPKTSIZE(mtu));
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/*
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* Adjust the PAUSE frame watermarks. We always set the LWM, and the
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@ -379,13 +390,16 @@ int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
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thres /= 10;
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thres = mtu > thres ? (mtu - thres + 7) / 8 : 0;
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thres = max(thres, 8U); /* need at least 8 */
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ipg = (adap->params.rev == T3_REV_C) ? 0 : 1;
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t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset,
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V_TXFIFOTHRESH(M_TXFIFOTHRESH) | V_TXIPG(M_TXIPG),
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V_TXFIFOTHRESH(thres) | V_TXIPG(1));
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V_TXFIFOTHRESH(thres) | V_TXIPG(ipg));
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if (adap->params.rev > 0)
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if (adap->params.rev > 0) {
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divisor = (adap->params.rev == T3_REV_C) ? 64 : 8;
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t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset,
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(hwm - lwm) * 4 / 8);
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(hwm - lwm) * 4 / divisor);
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}
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t3_write_reg(adap, A_XGM_TX_PAUSE_QUANTA + mac->offset,
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MAC_RXFIFO_SIZE * 4 * 8 / 512);
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return 0;
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@ -522,7 +536,7 @@ int t3b2_mac_watchdog_task(struct cmac *mac)
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goto rxcheck;
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}
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if ((tx_tcnt != mac->tx_tcnt) && (mac->tx_xcnt == 0)) {
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if ((tx_tcnt != mac->tx_tcnt) && (mac->tx_xcnt == 0)) {
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if (mac->toggle_cnt > 4) {
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status = 2;
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goto out;
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