ixgbe: A fix to VF TX rate limit
There is a need to configure MMW_SIZE in register RTTBCNRM with a correct value (0x4 for non jumbo frames and 0x14 for jumbo frames support). For 82599 the value is 0x4 and for X540 the value is 0x14. Signed-off-by: Lior Levy <lior.levy@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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2 changed files with 17 additions and 1 deletions
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@ -605,6 +605,22 @@ static void ixgbe_set_vf_rate_limit(struct ixgbe_hw *hw, int vf, int tx_rate,
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}
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IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, 2*vf); /* vf Y uses queue 2*Y */
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/*
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* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
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* register. Typically MMW_SIZE=0x014 if 9728-byte jumbo is supported
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* and 0x004 otherwise.
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*/
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switch (hw->mac.type) {
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case ixgbe_mac_82599EB:
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IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 0x4);
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break;
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case ixgbe_mac_X540:
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IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 0x14);
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break;
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default:
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break;
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}
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IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
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}
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@ -534,7 +534,7 @@
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#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14
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#define IXGBE_RTTBCNRC_RF_INT_MASK \
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(IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
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#define IXGBE_RTTBCNRM 0x04980
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/* FCoE DMA Context Registers */
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#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */
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