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Merge branch 'stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile into akpm 

Pull tile bugfixes from Chris Metcalf:
 "This includes a variety of minor bug fixes, mostly to do with testing
  "make allyesconfig", "make allmodconfig", "make allnoconfig", inspired
  to Tejun Heo's observation about Kconfig.freezer not being included.

  The largest changes are just syntax changes removing the tile-specific
  use of a macro named INT_MASK, which is way too commonly redefined
  throughout driver code"

* 'stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile:
  tile: tag some code with #ifdef CONFIG_COMPAT
  tile: fix memcpy_*io functions for allnoconfig
  tile: export a handful of symbols appropriately
  drm: fix compile failure by including <linux/swiotlb.h>
  tile: avoid defining INT_MASK macro in <arch/interrupts.h>
  tile: provide "screen_info" when enabling VT
  drivers/input/joystick/analog.c: enable precise timer
  tile: include kernel/Kconfig.freezer in tile Kconfig
  tile: remove an unused variable in copy_thread()
This commit is contained in:
Linus Torvalds 2013-02-12 15:13:42 -08:00
parent 983ca83634 570fd50153
commit 73c0d7522c
17 changed files with 413 additions and 394 deletions
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2
arch/tile/Kconfig
View File

@ -140,6 +140,8 @@ config ARCH_DEFCONFIG
source "init/Kconfig"
source "kernel/Kconfig.freezer"
menu "Tilera-specific configuration"
config NR_CPUS

6
arch/tile/include/asm/io.h
View File

@ -250,7 +250,9 @@ static inline void writeq(u64 val, unsigned long addr)
#define iowrite32 writel
#define iowrite64 writeq
static inline void memset_io(void *dst, int val, size_t len)
#if CHIP_HAS_MMIO() || defined(CONFIG_PCI)
static inline void memset_io(volatile void *dst, int val, size_t len)
{
int x;
BUG_ON((unsigned long)dst & 0x3);
@ -277,6 +279,8 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
writel(*(u32 *)(src + x), dst + x);
}
#endif
/*
* The Tile architecture does not support IOPORT, even with PCI.
* Unfortunately we can't yet simply not declare these methods,

32
arch/tile/include/asm/irqflags.h
View File

@ -18,32 +18,20 @@
#include <arch/interrupts.h>
#include <arch/chip.h>
#if !defined(__tilegx__) && defined(__ASSEMBLY__)
/*
* The set of interrupts we want to allow when interrupts are nominally
* disabled. The remainder are effectively "NMI" interrupts from
* the point of view of the generic Linux code. Note that synchronous
* interrupts (aka "non-queued") are not blocked by the mask in any case.
*/
#if CHIP_HAS_AUX_PERF_COUNTERS()
#define LINUX_MASKABLE_INTERRUPTS_HI \
(~(INT_MASK_HI(INT_PERF_COUNT) | INT_MASK_HI(INT_AUX_PERF_COUNT)))
#else
#define LINUX_MASKABLE_INTERRUPTS_HI \
(~(INT_MASK_HI(INT_PERF_COUNT)))
#endif
#else
#if CHIP_HAS_AUX_PERF_COUNTERS()
#define LINUX_MASKABLE_INTERRUPTS \
(~(INT_MASK(INT_PERF_COUNT) | INT_MASK(INT_AUX_PERF_COUNT)))
#else
#define LINUX_MASKABLE_INTERRUPTS \
(~(INT_MASK(INT_PERF_COUNT)))
#endif
(~((_AC(1,ULL) << INT_PERF_COUNT) | (_AC(1,ULL) << INT_AUX_PERF_COUNT)))
#if CHIP_HAS_SPLIT_INTR_MASK()
/* The same macro, but for the two 32-bit SPRs separately. */
#define LINUX_MASKABLE_INTERRUPTS_LO (-1)
#define LINUX_MASKABLE_INTERRUPTS_HI \
(~((1 << (INT_PERF_COUNT - 32)) | (1 << (INT_AUX_PERF_COUNT - 32))))
#endif
#ifndef __ASSEMBLY__
@ -126,7 +114,7 @@
* to know our current state.
*/
DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
#define INITIAL_INTERRUPTS_ENABLED INT_MASK(INT_MEM_ERROR)
#define INITIAL_INTERRUPTS_ENABLED (1ULL << INT_MEM_ERROR)
/* Disable interrupts. */
#define arch_local_irq_disable() \
@ -165,7 +153,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
/* Prevent the given interrupt from being enabled next time we enable irqs. */
#define arch_local_irq_mask(interrupt) \
(__get_cpu_var(interrupts_enabled_mask) &= ~INT_MASK(interrupt))
(__get_cpu_var(interrupts_enabled_mask) &= ~(1ULL << (interrupt)))
/* Prevent the given interrupt from being enabled immediately. */
#define arch_local_irq_mask_now(interrupt) do { \
@ -175,7 +163,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
/* Allow the given interrupt to be enabled next time we enable irqs. */
#define arch_local_irq_unmask(interrupt) \
(__get_cpu_var(interrupts_enabled_mask) |= INT_MASK(interrupt))
(__get_cpu_var(interrupts_enabled_mask) |= (1ULL << (interrupt)))
/* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */
#define arch_local_irq_unmask_now(interrupt) do { \
@ -250,7 +238,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
/* Disable interrupts. */
#define IRQ_DISABLE(tmp0, tmp1) \
{ \
movei tmp0, -1; \
movei tmp0, LINUX_MASKABLE_INTERRUPTS_LO; \
moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS_HI) \
}; \
{ \

394
arch/tile/include/uapi/arch/interrupts_32.h
View File

@ -15,6 +15,7 @@
#ifndef __ARCH_INTERRUPTS_H__
#define __ARCH_INTERRUPTS_H__
#ifndef __KERNEL__
/** Mask for an interrupt. */
/* Note: must handle breaking interrupts into high and low words manually. */
#define INT_MASK_LO(intno) (1 << (intno))
@ -23,6 +24,7 @@
#ifndef __ASSEMBLER__
#define INT_MASK(intno) (1ULL << (intno))
#endif
#endif
/** Where a given interrupt executes */
@ -92,216 +94,216 @@
#ifndef __ASSEMBLER__
#define QUEUED_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_DMATLB_MISS) | \
INT_MASK(INT_DMATLB_ACCESS) | \
INT_MASK(INT_SNITLB_MISS) | \
INT_MASK(INT_SN_NOTIFY) | \
INT_MASK(INT_SN_FIREWALL) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_DMA_NOTIFY) | \
INT_MASK(INT_IDN_CA) | \
INT_MASK(INT_UDN_CA) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DMA_ASID) | \
INT_MASK(INT_SNI_ASID) | \
INT_MASK(INT_DMA_CPL) | \
INT_MASK(INT_SN_CPL) | \
INT_MASK(INT_DOUBLE_FAULT) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_DMATLB_MISS) | \
(1ULL << INT_DMATLB_ACCESS) | \
(1ULL << INT_SNITLB_MISS) | \
(1ULL << INT_SN_NOTIFY) | \
(1ULL << INT_SN_FIREWALL) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_DMA_NOTIFY) | \
(1ULL << INT_IDN_CA) | \
(1ULL << INT_UDN_CA) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DMA_ASID) | \
(1ULL << INT_SNI_ASID) | \
(1ULL << INT_DMA_CPL) | \
(1ULL << INT_SN_CPL) | \
(1ULL << INT_DOUBLE_FAULT) | \
(1ULL << INT_AUX_PERF_COUNT) | \
0)
#define NONQUEUED_INTERRUPTS ( \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_SN_ACCESS) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_IDN_REFILL) | \
INT_MASK(INT_UDN_REFILL) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
INT_MASK(INT_SN_STATIC_ACCESS) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_SN_ACCESS) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_IDN_REFILL) | \
(1ULL << INT_UDN_REFILL) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
(1ULL << INT_SN_STATIC_ACCESS) | \
0)
#define CRITICAL_MASKED_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_DMATLB_MISS) | \
INT_MASK(INT_DMATLB_ACCESS) | \
INT_MASK(INT_SNITLB_MISS) | \
INT_MASK(INT_SN_NOTIFY) | \
INT_MASK(INT_SN_FIREWALL) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_DMA_NOTIFY) | \
INT_MASK(INT_IDN_CA) | \
INT_MASK(INT_UDN_CA) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_DMATLB_MISS) | \
(1ULL << INT_DMATLB_ACCESS) | \
(1ULL << INT_SNITLB_MISS) | \
(1ULL << INT_SN_NOTIFY) | \
(1ULL << INT_SN_FIREWALL) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_DMA_NOTIFY) | \
(1ULL << INT_IDN_CA) | \
(1ULL << INT_UDN_CA) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
(1ULL << INT_AUX_PERF_COUNT) | \
0)
#define CRITICAL_UNMASKED_INTERRUPTS ( \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_SN_ACCESS) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_IDN_REFILL) | \
INT_MASK(INT_UDN_REFILL) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DMA_ASID) | \
INT_MASK(INT_SNI_ASID) | \
INT_MASK(INT_DMA_CPL) | \
INT_MASK(INT_SN_CPL) | \
INT_MASK(INT_DOUBLE_FAULT) | \
INT_MASK(INT_SN_STATIC_ACCESS) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_SN_ACCESS) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_IDN_REFILL) | \
(1ULL << INT_UDN_REFILL) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DMA_ASID) | \
(1ULL << INT_SNI_ASID) | \
(1ULL << INT_DMA_CPL) | \
(1ULL << INT_SN_CPL) | \
(1ULL << INT_DOUBLE_FAULT) | \
(1ULL << INT_SN_STATIC_ACCESS) | \
0)
#define MASKABLE_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_IDN_REFILL) | \
INT_MASK(INT_UDN_REFILL) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_DMATLB_MISS) | \
INT_MASK(INT_DMATLB_ACCESS) | \
INT_MASK(INT_SNITLB_MISS) | \
INT_MASK(INT_SN_NOTIFY) | \
INT_MASK(INT_SN_FIREWALL) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_DMA_NOTIFY) | \
INT_MASK(INT_IDN_CA) | \
INT_MASK(INT_UDN_CA) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_IDN_REFILL) | \
(1ULL << INT_UDN_REFILL) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_DMATLB_MISS) | \
(1ULL << INT_DMATLB_ACCESS) | \
(1ULL << INT_SNITLB_MISS) | \
(1ULL << INT_SN_NOTIFY) | \
(1ULL << INT_SN_FIREWALL) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_DMA_NOTIFY) | \
(1ULL << INT_IDN_CA) | \
(1ULL << INT_UDN_CA) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
(1ULL << INT_AUX_PERF_COUNT) | \
0)
#define UNMASKABLE_INTERRUPTS ( \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_SN_ACCESS) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DMA_ASID) | \
INT_MASK(INT_SNI_ASID) | \
INT_MASK(INT_DMA_CPL) | \
INT_MASK(INT_SN_CPL) | \
INT_MASK(INT_DOUBLE_FAULT) | \
INT_MASK(INT_SN_STATIC_ACCESS) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_SN_ACCESS) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DMA_ASID) | \
(1ULL << INT_SNI_ASID) | \
(1ULL << INT_DMA_CPL) | \
(1ULL << INT_SN_CPL) | \
(1ULL << INT_DOUBLE_FAULT) | \
(1ULL << INT_SN_STATIC_ACCESS) | \
0)
#define SYNC_INTERRUPTS ( \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_SN_ACCESS) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_IDN_REFILL) | \
INT_MASK(INT_UDN_REFILL) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
INT_MASK(INT_SN_STATIC_ACCESS) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_SN_ACCESS) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_IDN_REFILL) | \
(1ULL << INT_UDN_REFILL) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
(1ULL << INT_SN_STATIC_ACCESS) | \
0)
#define NON_SYNC_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_DMATLB_MISS) | \
INT_MASK(INT_DMATLB_ACCESS) | \
INT_MASK(INT_SNITLB_MISS) | \
INT_MASK(INT_SN_NOTIFY) | \
INT_MASK(INT_SN_FIREWALL) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_DMA_NOTIFY) | \
INT_MASK(INT_IDN_CA) | \
INT_MASK(INT_UDN_CA) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DMA_ASID) | \
INT_MASK(INT_SNI_ASID) | \
INT_MASK(INT_DMA_CPL) | \
INT_MASK(INT_SN_CPL) | \
INT_MASK(INT_DOUBLE_FAULT) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_DMATLB_MISS) | \
(1ULL << INT_DMATLB_ACCESS) | \
(1ULL << INT_SNITLB_MISS) | \
(1ULL << INT_SN_NOTIFY) | \
(1ULL << INT_SN_FIREWALL) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_DMA_NOTIFY) | \
(1ULL << INT_IDN_CA) | \
(1ULL << INT_UDN_CA) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DMA_ASID) | \
(1ULL << INT_SNI_ASID) | \
(1ULL << INT_DMA_CPL) | \
(1ULL << INT_SN_CPL) | \
(1ULL << INT_DOUBLE_FAULT) | \
(1ULL << INT_AUX_PERF_COUNT) | \
0)
#endif /* !__ASSEMBLER__ */
#endif /* !__ARCH_INTERRUPTS_H__ */

346
arch/tile/include/uapi/arch/interrupts_64.h
View File

@ -15,6 +15,7 @@
#ifndef __ARCH_INTERRUPTS_H__
#define __ARCH_INTERRUPTS_H__
#ifndef __KERNEL__
/** Mask for an interrupt. */
#ifdef __ASSEMBLER__
/* Note: must handle breaking interrupts into high and low words manually. */
@ -22,6 +23,7 @@
#else
#define INT_MASK(intno) (1ULL << (intno))
#endif
#endif
/** Where a given interrupt executes */
@ -85,192 +87,192 @@
#ifndef __ASSEMBLER__
#define QUEUED_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_AUX_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_IPI_3) | \
INT_MASK(INT_IPI_2) | \
INT_MASK(INT_IPI_1) | \
INT_MASK(INT_IPI_0) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DOUBLE_FAULT) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_AUX_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_IPI_3) | \
(1ULL << INT_IPI_2) | \
(1ULL << INT_IPI_1) | \
(1ULL << INT_IPI_0) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_AUX_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DOUBLE_FAULT) | \
0)
#define NONQUEUED_INTERRUPTS ( \
INT_MASK(INT_SINGLE_STEP_3) | \
INT_MASK(INT_SINGLE_STEP_2) | \
INT_MASK(INT_SINGLE_STEP_1) | \
INT_MASK(INT_SINGLE_STEP_0) | \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_ILL_TRANS) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
(1ULL << INT_SINGLE_STEP_3) | \
(1ULL << INT_SINGLE_STEP_2) | \
(1ULL << INT_SINGLE_STEP_1) | \
(1ULL << INT_SINGLE_STEP_0) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_ILL_TRANS) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
0)
#define CRITICAL_MASKED_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_SINGLE_STEP_3) | \
INT_MASK(INT_SINGLE_STEP_2) | \
INT_MASK(INT_SINGLE_STEP_1) | \
INT_MASK(INT_SINGLE_STEP_0) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_AUX_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_IPI_3) | \
INT_MASK(INT_IPI_2) | \
INT_MASK(INT_IPI_1) | \
INT_MASK(INT_IPI_0) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_SINGLE_STEP_3) | \
(1ULL << INT_SINGLE_STEP_2) | \
(1ULL << INT_SINGLE_STEP_1) | \
(1ULL << INT_SINGLE_STEP_0) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_AUX_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_IPI_3) | \
(1ULL << INT_IPI_2) | \
(1ULL << INT_IPI_1) | \
(1ULL << INT_IPI_0) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_AUX_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
0)
#define CRITICAL_UNMASKED_INTERRUPTS ( \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_ILL_TRANS) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DOUBLE_FAULT) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_ILL_TRANS) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DOUBLE_FAULT) | \
0)
#define MASKABLE_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_SINGLE_STEP_3) | \
INT_MASK(INT_SINGLE_STEP_2) | \
INT_MASK(INT_SINGLE_STEP_1) | \
INT_MASK(INT_SINGLE_STEP_0) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_AUX_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_IPI_3) | \
INT_MASK(INT_IPI_2) | \
INT_MASK(INT_IPI_1) | \
INT_MASK(INT_IPI_0) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_SINGLE_STEP_3) | \
(1ULL << INT_SINGLE_STEP_2) | \
(1ULL << INT_SINGLE_STEP_1) | \
(1ULL << INT_SINGLE_STEP_0) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_AUX_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_IPI_3) | \
(1ULL << INT_IPI_2) | \
(1ULL << INT_IPI_1) | \
(1ULL << INT_IPI_0) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_AUX_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
0)
#define UNMASKABLE_INTERRUPTS ( \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_ILL_TRANS) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DOUBLE_FAULT) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_ILL_TRANS) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DOUBLE_FAULT) | \
0)
#define SYNC_INTERRUPTS ( \
INT_MASK(INT_SINGLE_STEP_3) | \
INT_MASK(INT_SINGLE_STEP_2) | \
INT_MASK(INT_SINGLE_STEP_1) | \
INT_MASK(INT_SINGLE_STEP_0) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_ILL_TRANS) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
(1ULL << INT_SINGLE_STEP_3) | \
(1ULL << INT_SINGLE_STEP_2) | \
(1ULL << INT_SINGLE_STEP_1) | \
(1ULL << INT_SINGLE_STEP_0) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_ILL_TRANS) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
0)
#define NON_SYNC_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_AUX_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_IPI_3) | \
INT_MASK(INT_IPI_2) | \
INT_MASK(INT_IPI_1) | \
INT_MASK(INT_IPI_0) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DOUBLE_FAULT) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_AUX_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_IPI_3) | \
(1ULL << INT_IPI_2) | \
(1ULL << INT_IPI_1) | \
(1ULL << INT_IPI_0) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_AUX_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DOUBLE_FAULT) | \
0)
#endif /* !__ASSEMBLER__ */
#endif /* !__ARCH_INTERRUPTS_H__ */

4
arch/tile/kernel/intvec_64.S
View File

@ -1035,7 +1035,9 @@ handle_syscall:
/* Ensure that the syscall number is within the legal range. */
{
moveli r20, hw2(sys_call_table)
#ifdef CONFIG_COMPAT
blbs r30, .Lcompat_syscall
#endif
}
{
cmpltu r21, TREG_SYSCALL_NR_NAME, r21
@ -1093,6 +1095,7 @@ handle_syscall:
j .Lresume_userspace /* jump into middle of interrupt_return */
}
#ifdef CONFIG_COMPAT
.Lcompat_syscall:
/*
* Load the base of the compat syscall table in r20, and
@ -1117,6 +1120,7 @@ handle_syscall:
{ move r15, r4; addxi r4, r4, 0 }
{ move r16, r5; addxi r5, r5, 0 }
j .Lload_syscall_pointer
#endif
.Linvalid_syscall:
/* Report an invalid syscall back to the user program */

2
arch/tile/kernel/process.c
View File

@ -159,7 +159,7 @@ static void save_arch_state(struct thread_struct *t);
int copy_thread(unsigned long clone_flags, unsigned long sp,
unsigned long arg, struct task_struct *p)
{
struct pt_regs *childregs = task_pt_regs(p), *regs = current_pt_regs();
struct pt_regs *childregs = task_pt_regs(p);
unsigned long ksp;
unsigned long *callee_regs;

2
arch/tile/kernel/reboot.c
View File

@ -16,6 +16,7 @@
#include <linux/reboot.h>
#include <linux/smp.h>
#include <linux/pm.h>
#include <linux/export.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <hv/hypervisor.h>
@ -49,3 +50,4 @@ void machine_restart(char *cmd)
/* No interesting distinction to be made here. */
void (*pm_power_off)(void) = NULL;
EXPORT_SYMBOL(pm_power_off);

5
arch/tile/kernel/setup.c
View File

@ -31,6 +31,7 @@
#include <linux/timex.h>
#include <linux/hugetlb.h>
#include <linux/start_kernel.h>
#include <linux/screen_info.h>
#include <asm/setup.h>
#include <asm/sections.h>
#include <asm/cacheflush.h>
@ -49,6 +50,10 @@ static inline int ABS(int x) { return x >= 0 ? x : -x; }
/* Chip information */
char chip_model[64] __write_once;
#ifdef CONFIG_VT
struct screen_info screen_info;
#endif
struct pglist_data node_data[MAX_NUMNODES] __read_mostly;
EXPORT_SYMBOL(node_data);

3
arch/tile/kernel/stack.c
View File

@ -112,7 +112,7 @@ static struct pt_regs *valid_fault_handler(struct KBacktraceIterator* kbt)
p->pc, p->sp, p->ex1);
p = NULL;
}
if (!kbt->profile || (INT_MASK(p->faultnum) & QUEUED_INTERRUPTS) == 0)
if (!kbt->profile || ((1ULL << p->faultnum) & QUEUED_INTERRUPTS) == 0)
return p;
return NULL;
}
@ -484,6 +484,7 @@ void save_stack_trace(struct stack_trace *trace)
{
save_stack_trace_tsk(NULL, trace);
}
EXPORT_SYMBOL_GPL(save_stack_trace);
#endif

2
arch/tile/lib/cacheflush.c
View File

@ -12,6 +12,7 @@
* more details.
*/
#include <linux/export.h>
#include <asm/page.h>
#include <asm/cacheflush.h>
#include <arch/icache.h>
@ -165,3 +166,4 @@ void finv_buffer_remote(void *buffer, size_t size, int hfh)
__insn_mtspr(SPR_DSTREAM_PF, old_dstream_pf);
#endif
}
EXPORT_SYMBOL_GPL(finv_buffer_remote);

2
arch/tile/lib/cpumask.c
View File

@ -16,6 +16,7 @@
#include <linux/ctype.h>
#include <linux/errno.h>
#include <linux/smp.h>
#include <linux/export.h>
/*
* Allow cropping out bits beyond the end of the array.
@ -50,3 +51,4 @@ int bitmap_parselist_crop(const char *bp, unsigned long *maskp, int nmaskbits)
} while (*bp != '\0' && *bp != '\n');
return 0;
}
EXPORT_SYMBOL(bitmap_parselist_crop);

2
arch/tile/lib/exports.c
View File

@ -55,6 +55,8 @@ EXPORT_SYMBOL(hv_dev_poll_cancel);
EXPORT_SYMBOL(hv_dev_close);
EXPORT_SYMBOL(hv_sysconf);
EXPORT_SYMBOL(hv_confstr);
EXPORT_SYMBOL(hv_get_rtc);
EXPORT_SYMBOL(hv_set_rtc);
/* libgcc.a */
uint32_t __udivsi3(uint32_t dividend, uint32_t divisor);

1
arch/tile/mm/homecache.c
View File

@ -408,6 +408,7 @@ void homecache_change_page_home(struct page *page, int order, int home)
__set_pte(ptep, pte_set_home(pteval, home));
}
}
EXPORT_SYMBOL(homecache_change_page_home);
struct page *homecache_alloc_pages(gfp_t gfp_mask,
unsigned int order, int home)

1
drivers/gpu/drm/nouveau/nouveau_bo.c
View File

@ -28,6 +28,7 @@
*/
#include <core/engine.h>
#include <linux/swiotlb.h>
#include <subdev/fb.h>
#include <subdev/vm.h>

1
drivers/gpu/drm/radeon/radeon_ttm.c
View File

@ -38,6 +38,7 @@
#include <drm/radeon_drm.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/swiotlb.h>
#include "radeon_reg.h"
#include "radeon.h"

2
drivers/input/joystick/analog.c
View File

@ -162,7 +162,7 @@ static unsigned int get_time_pit(void)
#define GET_TIME(x) do { x = get_cycles(); } while (0)
#define DELTA(x,y) ((y)-(x))
#define TIME_NAME "PCC"
#elif defined(CONFIG_MN10300)
#elif defined(CONFIG_MN10300) || defined(CONFIG_TILE)
#define GET_TIME(x) do { x = get_cycles(); } while (0)
#define DELTA(x, y) ((x) - (y))
#define TIME_NAME "TSC"