gma500: Add VBLANK support for Poulsbo hardware
Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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84b08fe62c
commit
700e59f692
2 changed files with 44 additions and 30 deletions
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@ -134,6 +134,9 @@ enum {
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#define _PSB_IRQ_MSVDX_FLAG (1<<19)
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#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
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#define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
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_PSB_VSYNC_PIPEB_FLAG)
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/* This flag includes all the display IRQ bits excepts the vblank irqs. */
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#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
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_MDFLD_PIPEB_EVENT_FLAG | \
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@ -137,22 +137,11 @@ void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
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}
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}
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/**
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* Display controller interrupt handler for vsync/vblank.
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*
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*/
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static void mid_vblank_handler(struct drm_device *dev, uint32_t pipe)
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{
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drm_handle_vblank(dev, pipe);
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}
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/**
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* Display controller interrupt handler for pipe event.
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*
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*/
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#define WAIT_STATUS_CLEAR_LOOP_COUNT 0xffff
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static void mid_pipe_event_handler(struct drm_device *dev, uint32_t pipe)
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static void mid_pipe_event_handler(struct drm_device *dev, int pipe)
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{
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struct drm_psb_private *dev_priv =
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(struct drm_psb_private *) dev->dev_private;
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@ -161,6 +150,7 @@ static void mid_pipe_event_handler(struct drm_device *dev, uint32_t pipe)
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uint32_t pipe_stat_reg = psb_pipestat(pipe);
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uint32_t pipe_enable = dev_priv->pipestat[pipe];
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uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
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uint32_t pipe_clear;
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uint32_t i = 0;
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spin_lock(&dev_priv->irqmask_lock);
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@ -171,27 +161,23 @@ static void mid_pipe_event_handler(struct drm_device *dev, uint32_t pipe)
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spin_unlock(&dev_priv->irqmask_lock);
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/* clear the 2nd level interrupt status bits */
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/**
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* FIXME: shouldn't use while loop here. However, the interrupt
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* status 'sticky' bits cannot be cleared by setting '1' to that
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* bit once...
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*/
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for (i = 0; i < WAIT_STATUS_CLEAR_LOOP_COUNT; i++) {
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/* Clear the 2nd level interrupt status bits
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* Sometimes the bits are very sticky so we repeat until they unstick */
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for (i = 0; i < 0xffff; i++) {
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PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
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(void) PSB_RVDC32(pipe_stat_reg);
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pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status;
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if ((PSB_RVDC32(pipe_stat_reg) & pipe_status) == 0)
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if (pipe_clear == 0)
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break;
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}
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if (i == WAIT_STATUS_CLEAR_LOOP_COUNT)
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if (pipe_clear)
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dev_err(dev->dev,
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"%s, can't clear the status bits in pipe_stat_reg, its value = 0x%x.\n",
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__func__, PSB_RVDC32(pipe_stat_reg));
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"%s, can't clear status bits for pipe %d, its value = 0x%x.\n",
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__func__, pipe, PSB_RVDC32(pipe_stat_reg));
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if (pipe_stat_val & PIPE_VBLANK_STATUS)
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mid_vblank_handler(dev, pipe);
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drm_handle_vblank(dev, pipe);
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if (pipe_stat_val & PIPE_TE_STATUS)
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drm_handle_vblank(dev, pipe);
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@ -202,8 +188,11 @@ static void mid_pipe_event_handler(struct drm_device *dev, uint32_t pipe)
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*/
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static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
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{
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if (vdc_stat & _PSB_PIPEA_EVENT_FLAG)
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if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)
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mid_pipe_event_handler(dev, 0);
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if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)
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mid_pipe_event_handler(dev, 1);
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}
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irqreturn_t psb_irq_handler(DRM_IRQ_ARGS)
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@ -219,8 +208,13 @@ irqreturn_t psb_irq_handler(DRM_IRQ_ARGS)
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vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
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if (vdc_stat & _PSB_PIPE_EVENT_FLAG)
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dsp_int = 1;
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/* FIXME: Handle Medfield
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if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG)
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dsp_int = 1;
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*/
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if (vdc_stat & _PSB_IRQ_SGX_FLAG)
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sgx_int = 1;
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@ -266,13 +260,18 @@ void psb_irq_preinstall(struct drm_device *dev)
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if (gma_power_is_on(dev))
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PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
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if (dev->vblank_enabled[0])
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dev_priv->vdc_irq_mask |= _PSB_PIPEA_EVENT_FLAG;
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dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
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if (dev->vblank_enabled[1])
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dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
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/* FIXME: Handle Medfield irq mask
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if (dev->vblank_enabled[1])
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dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
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if (dev->vblank_enabled[2])
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dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
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*/
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/*This register is safe even if display island is off*/
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/* This register is safe even if display island is off */
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PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
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spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
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}
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@ -464,7 +463,13 @@ int psb_enable_vblank(struct drm_device *dev, int pipe)
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spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
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mid_enable_pipe_event(dev_priv, pipe);
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if (pipe == 0)
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dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
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else if (pipe == 1)
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dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
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PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
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PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
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psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
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spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
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@ -482,7 +487,13 @@ void psb_disable_vblank(struct drm_device *dev, int pipe)
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spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
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mid_disable_pipe_event(dev_priv, pipe);
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if (pipe == 0)
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dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG;
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else if (pipe == 1)
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dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG;
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PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
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PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
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psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
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spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
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